1 files changed, 5 insertions, 7 deletions

diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 2efee3f196f5..177de814286f 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -59,7 +59,7 @@ static bool is_event_valid(u64 event)
 {
         u64 valid_mask = EVENT_VALID_MASK;
 
-        if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
+        if (cpu_has_feature(CPU_FTR_ARCH_300))
                 valid_mask = p9_EVENT_VALID_MASK;
 
         return !(event & ~valid_mask);
@@ -86,8 +86,6 @@ static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
          * Incase of Power9:
          * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
          *               or if group already have any marked events.
-         * Non-Marked events (for DD1):
-         *      MMCRA[SDAR_MODE] will be set to 0b01
          * For rest
          *      MMCRA[SDAR_MODE] will be set from event code.
          *      If sdar_mode from event is zero, default to 0b01. Hardware
@@ -96,7 +94,7 @@ static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
                 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
                         *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
-                else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event))
+                else if (p9_SDAR_MODE(event))
                         *mmcra |=  p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
                 else
                         *mmcra |= MMCRA_SDAR_MODE_DCACHE;
@@ -106,7 +104,7 @@ static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
 
 static u64 thresh_cmp_val(u64 value)
 {
-        if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
+        if (cpu_has_feature(CPU_FTR_ARCH_300))
                 return value << p9_MMCRA_THR_CMP_SHIFT;
 
         return value << MMCRA_THR_CMP_SHIFT;
@@ -114,7 +112,7 @@ static u64 thresh_cmp_val(u64 value)
 
 static unsigned long combine_from_event(u64 event)
 {
-        if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
+        if (cpu_has_feature(CPU_FTR_ARCH_300))
                 return p9_EVENT_COMBINE(event);
 
         return EVENT_COMBINE(event);
@@ -122,7 +120,7 @@ static unsigned long combine_from_event(u64 event)
 
 static unsigned long combine_shift(unsigned long pmc)
 {
-        if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
+        if (cpu_has_feature(CPU_FTR_ARCH_300))
                 return p9_MMCR1_COMBINE_SHIFT(pmc);
 
         return MMCR1_COMBINE_SHIFT(pmc);