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-rw-r--r--arch/powerpc/perf/core-book3s.c34
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3f66fcf8ad99..01f92c4a9f02 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -128,10 +128,6 @@ static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
128static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 128static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
129static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 129static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
130static void pmao_restore_workaround(bool ebb) { } 130static void pmao_restore_workaround(bool ebb) { }
131static bool use_ic(u64 event)
132{
133 return false;
134}
135#endif /* CONFIG_PPC32 */ 131#endif /* CONFIG_PPC32 */
136 132
137static bool regs_use_siar(struct pt_regs *regs) 133static bool regs_use_siar(struct pt_regs *regs)
@@ -714,14 +710,6 @@ static void pmao_restore_workaround(bool ebb)
714 mtspr(SPRN_PMC6, pmcs[5]); 710 mtspr(SPRN_PMC6, pmcs[5]);
715} 711}
716 712
717static bool use_ic(u64 event)
718{
719 if (cpu_has_feature(CPU_FTR_POWER9_DD1) &&
720 (event == 0x200f2 || event == 0x300f2))
721 return true;
722
723 return false;
724}
725#endif /* CONFIG_PPC64 */ 713#endif /* CONFIG_PPC64 */
726 714
727static void perf_event_interrupt(struct pt_regs *regs); 715static void perf_event_interrupt(struct pt_regs *regs);
@@ -1046,7 +1034,6 @@ static u64 check_and_compute_delta(u64 prev, u64 val)
1046static void power_pmu_read(struct perf_event *event) 1034static void power_pmu_read(struct perf_event *event)
1047{ 1035{
1048 s64 val, delta, prev; 1036 s64 val, delta, prev;
1049 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1050 1037
1051 if (event->hw.state & PERF_HES_STOPPED) 1038 if (event->hw.state & PERF_HES_STOPPED)
1052 return; 1039 return;
@@ -1056,13 +1043,6 @@ static void power_pmu_read(struct perf_event *event)
1056 1043
1057 if (is_ebb_event(event)) { 1044 if (is_ebb_event(event)) {
1058 val = read_pmc(event->hw.idx); 1045 val = read_pmc(event->hw.idx);
1059 if (use_ic(event->attr.config)) {
1060 val = mfspr(SPRN_IC);
1061 if (val > cpuhw->ic_init)
1062 val = val - cpuhw->ic_init;
1063 else
1064 val = val + (0 - cpuhw->ic_init);
1065 }
1066 local64_set(&event->hw.prev_count, val); 1046 local64_set(&event->hw.prev_count, val);
1067 return; 1047 return;
1068 } 1048 }
@@ -1076,13 +1056,6 @@ static void power_pmu_read(struct perf_event *event)
1076 prev = local64_read(&event->hw.prev_count); 1056 prev = local64_read(&event->hw.prev_count);
1077 barrier(); 1057 barrier();
1078 val = read_pmc(event->hw.idx); 1058 val = read_pmc(event->hw.idx);
1079 if (use_ic(event->attr.config)) {
1080 val = mfspr(SPRN_IC);
1081 if (val > cpuhw->ic_init)
1082 val = val - cpuhw->ic_init;
1083 else
1084 val = val + (0 - cpuhw->ic_init);
1085 }
1086 delta = check_and_compute_delta(prev, val); 1059 delta = check_and_compute_delta(prev, val);
1087 if (!delta) 1060 if (!delta)
1088 return; 1061 return;
@@ -1535,13 +1508,6 @@ nocheck:
1535 event->attr.branch_sample_type); 1508 event->attr.branch_sample_type);
1536 } 1509 }
1537 1510
1538 /*
1539 * Workaround for POWER9 DD1 to use the Instruction Counter
1540 * register value for instruction counting
1541 */
1542 if (use_ic(event->attr.config))
1543 cpuhw->ic_init = mfspr(SPRN_IC);
1544
1545 perf_pmu_enable(event->pmu); 1511 perf_pmu_enable(event->pmu);
1546 local_irq_restore(flags); 1512 local_irq_restore(flags);
1547 return ret; 1513 return ret;