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-rw-r--r--arch/powerpc/include/asm/atomic.h48
-rw-r--r--arch/powerpc/include/asm/bitops.h12
-rw-r--r--arch/powerpc/include/asm/compat.h3
-rw-r--r--arch/powerpc/include/asm/device.h2
-rw-r--r--arch/powerpc/include/asm/firmware.h10
-rw-r--r--arch/powerpc/include/asm/floppy.h4
-rw-r--r--arch/powerpc/include/asm/futex.h7
-rw-r--r--arch/powerpc/include/asm/hugetlb.h63
-rw-r--r--arch/powerpc/include/asm/kexec.h2
-rw-r--r--arch/powerpc/include/asm/kvm.h5
-rw-r--r--arch/powerpc/include/asm/kvm_book3s.h38
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_asm.h2
-rw-r--r--arch/powerpc/include/asm/kvm_host.h30
-rw-r--r--arch/powerpc/include/asm/kvm_ppc.h1
-rw-r--r--arch/powerpc/include/asm/lv1call.h3
-rw-r--r--arch/powerpc/include/asm/machdep.h4
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h7
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h3
-rw-r--r--arch/powerpc/include/asm/mmu.h18
-rw-r--r--arch/powerpc/include/asm/mpic.h2
-rw-r--r--arch/powerpc/include/asm/opal.h443
-rw-r--r--arch/powerpc/include/asm/paca.h8
-rw-r--r--arch/powerpc/include/asm/page.h31
-rw-r--r--arch/powerpc/include/asm/page_64.h11
-rw-r--r--arch/powerpc/include/asm/pte-book3e.h3
-rw-r--r--arch/powerpc/include/asm/qe.h2
-rw-r--r--arch/powerpc/include/asm/reg_booke.h5
-rw-r--r--arch/powerpc/include/asm/rtas.h6
-rw-r--r--arch/powerpc/include/asm/sections.h2
-rw-r--r--arch/powerpc/include/asm/smp.h1
-rw-r--r--arch/powerpc/include/asm/sparsemem.h2
-rw-r--r--arch/powerpc/include/asm/spu.h1
-rw-r--r--arch/powerpc/include/asm/synch.h9
-rw-r--r--arch/powerpc/include/asm/systbl.h4
-rw-r--r--arch/powerpc/include/asm/topology.h14
-rw-r--r--arch/powerpc/include/asm/udbg.h4
-rw-r--r--arch/powerpc/include/asm/unistd.h4
-rw-r--r--arch/powerpc/include/asm/xics.h23
38 files changed, 736 insertions, 101 deletions
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index e2a4c26ad377..02e41b53488d 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -49,13 +49,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
49 int t; 49 int t;
50 50
51 __asm__ __volatile__( 51 __asm__ __volatile__(
52 PPC_RELEASE_BARRIER 52 PPC_ATOMIC_ENTRY_BARRIER
53"1: lwarx %0,0,%2 # atomic_add_return\n\ 53"1: lwarx %0,0,%2 # atomic_add_return\n\
54 add %0,%1,%0\n" 54 add %0,%1,%0\n"
55 PPC405_ERR77(0,%2) 55 PPC405_ERR77(0,%2)
56" stwcx. %0,0,%2 \n\ 56" stwcx. %0,0,%2 \n\
57 bne- 1b" 57 bne- 1b"
58 PPC_ACQUIRE_BARRIER 58 PPC_ATOMIC_EXIT_BARRIER
59 : "=&r" (t) 59 : "=&r" (t)
60 : "r" (a), "r" (&v->counter) 60 : "r" (a), "r" (&v->counter)
61 : "cc", "memory"); 61 : "cc", "memory");
@@ -85,13 +85,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
85 int t; 85 int t;
86 86
87 __asm__ __volatile__( 87 __asm__ __volatile__(
88 PPC_RELEASE_BARRIER 88 PPC_ATOMIC_ENTRY_BARRIER
89"1: lwarx %0,0,%2 # atomic_sub_return\n\ 89"1: lwarx %0,0,%2 # atomic_sub_return\n\
90 subf %0,%1,%0\n" 90 subf %0,%1,%0\n"
91 PPC405_ERR77(0,%2) 91 PPC405_ERR77(0,%2)
92" stwcx. %0,0,%2 \n\ 92" stwcx. %0,0,%2 \n\
93 bne- 1b" 93 bne- 1b"
94 PPC_ACQUIRE_BARRIER 94 PPC_ATOMIC_EXIT_BARRIER
95 : "=&r" (t) 95 : "=&r" (t)
96 : "r" (a), "r" (&v->counter) 96 : "r" (a), "r" (&v->counter)
97 : "cc", "memory"); 97 : "cc", "memory");
@@ -119,13 +119,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
119 int t; 119 int t;
120 120
121 __asm__ __volatile__( 121 __asm__ __volatile__(
122 PPC_RELEASE_BARRIER 122 PPC_ATOMIC_ENTRY_BARRIER
123"1: lwarx %0,0,%1 # atomic_inc_return\n\ 123"1: lwarx %0,0,%1 # atomic_inc_return\n\
124 addic %0,%0,1\n" 124 addic %0,%0,1\n"
125 PPC405_ERR77(0,%1) 125 PPC405_ERR77(0,%1)
126" stwcx. %0,0,%1 \n\ 126" stwcx. %0,0,%1 \n\
127 bne- 1b" 127 bne- 1b"
128 PPC_ACQUIRE_BARRIER 128 PPC_ATOMIC_EXIT_BARRIER
129 : "=&r" (t) 129 : "=&r" (t)
130 : "r" (&v->counter) 130 : "r" (&v->counter)
131 : "cc", "xer", "memory"); 131 : "cc", "xer", "memory");
@@ -163,13 +163,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
163 int t; 163 int t;
164 164
165 __asm__ __volatile__( 165 __asm__ __volatile__(
166 PPC_RELEASE_BARRIER 166 PPC_ATOMIC_ENTRY_BARRIER
167"1: lwarx %0,0,%1 # atomic_dec_return\n\ 167"1: lwarx %0,0,%1 # atomic_dec_return\n\
168 addic %0,%0,-1\n" 168 addic %0,%0,-1\n"
169 PPC405_ERR77(0,%1) 169 PPC405_ERR77(0,%1)
170" stwcx. %0,0,%1\n\ 170" stwcx. %0,0,%1\n\
171 bne- 1b" 171 bne- 1b"
172 PPC_ACQUIRE_BARRIER 172 PPC_ATOMIC_EXIT_BARRIER
173 : "=&r" (t) 173 : "=&r" (t)
174 : "r" (&v->counter) 174 : "r" (&v->counter)
175 : "cc", "xer", "memory"); 175 : "cc", "xer", "memory");
@@ -194,7 +194,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
194 int t; 194 int t;
195 195
196 __asm__ __volatile__ ( 196 __asm__ __volatile__ (
197 PPC_RELEASE_BARRIER 197 PPC_ATOMIC_ENTRY_BARRIER
198"1: lwarx %0,0,%1 # __atomic_add_unless\n\ 198"1: lwarx %0,0,%1 # __atomic_add_unless\n\
199 cmpw 0,%0,%3 \n\ 199 cmpw 0,%0,%3 \n\
200 beq- 2f \n\ 200 beq- 2f \n\
@@ -202,7 +202,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
202 PPC405_ERR77(0,%2) 202 PPC405_ERR77(0,%2)
203" stwcx. %0,0,%1 \n\ 203" stwcx. %0,0,%1 \n\
204 bne- 1b \n" 204 bne- 1b \n"
205 PPC_ACQUIRE_BARRIER 205 PPC_ATOMIC_EXIT_BARRIER
206" subf %0,%2,%0 \n\ 206" subf %0,%2,%0 \n\
2072:" 2072:"
208 : "=&r" (t) 208 : "=&r" (t)
@@ -226,7 +226,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
226 int t; 226 int t;
227 227
228 __asm__ __volatile__( 228 __asm__ __volatile__(
229 PPC_RELEASE_BARRIER 229 PPC_ATOMIC_ENTRY_BARRIER
230"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\ 230"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
231 cmpwi %0,1\n\ 231 cmpwi %0,1\n\
232 addi %0,%0,-1\n\ 232 addi %0,%0,-1\n\
@@ -234,7 +234,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
234 PPC405_ERR77(0,%1) 234 PPC405_ERR77(0,%1)
235" stwcx. %0,0,%1\n\ 235" stwcx. %0,0,%1\n\
236 bne- 1b" 236 bne- 1b"
237 PPC_ACQUIRE_BARRIER 237 PPC_ATOMIC_EXIT_BARRIER
238 "\n\ 238 "\n\
2392:" : "=&b" (t) 2392:" : "=&b" (t)
240 : "r" (&v->counter) 240 : "r" (&v->counter)
@@ -285,12 +285,12 @@ static __inline__ long atomic64_add_return(long a, atomic64_t *v)
285 long t; 285 long t;
286 286
287 __asm__ __volatile__( 287 __asm__ __volatile__(
288 PPC_RELEASE_BARRIER 288 PPC_ATOMIC_ENTRY_BARRIER
289"1: ldarx %0,0,%2 # atomic64_add_return\n\ 289"1: ldarx %0,0,%2 # atomic64_add_return\n\
290 add %0,%1,%0\n\ 290 add %0,%1,%0\n\
291 stdcx. %0,0,%2 \n\ 291 stdcx. %0,0,%2 \n\
292 bne- 1b" 292 bne- 1b"
293 PPC_ACQUIRE_BARRIER 293 PPC_ATOMIC_EXIT_BARRIER
294 : "=&r" (t) 294 : "=&r" (t)
295 : "r" (a), "r" (&v->counter) 295 : "r" (a), "r" (&v->counter)
296 : "cc", "memory"); 296 : "cc", "memory");
@@ -319,12 +319,12 @@ static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
319 long t; 319 long t;
320 320
321 __asm__ __volatile__( 321 __asm__ __volatile__(
322 PPC_RELEASE_BARRIER 322 PPC_ATOMIC_ENTRY_BARRIER
323"1: ldarx %0,0,%2 # atomic64_sub_return\n\ 323"1: ldarx %0,0,%2 # atomic64_sub_return\n\
324 subf %0,%1,%0\n\ 324 subf %0,%1,%0\n\
325 stdcx. %0,0,%2 \n\ 325 stdcx. %0,0,%2 \n\
326 bne- 1b" 326 bne- 1b"
327 PPC_ACQUIRE_BARRIER 327 PPC_ATOMIC_EXIT_BARRIER
328 : "=&r" (t) 328 : "=&r" (t)
329 : "r" (a), "r" (&v->counter) 329 : "r" (a), "r" (&v->counter)
330 : "cc", "memory"); 330 : "cc", "memory");
@@ -351,12 +351,12 @@ static __inline__ long atomic64_inc_return(atomic64_t *v)
351 long t; 351 long t;
352 352
353 __asm__ __volatile__( 353 __asm__ __volatile__(
354 PPC_RELEASE_BARRIER 354 PPC_ATOMIC_ENTRY_BARRIER
355"1: ldarx %0,0,%1 # atomic64_inc_return\n\ 355"1: ldarx %0,0,%1 # atomic64_inc_return\n\
356 addic %0,%0,1\n\ 356 addic %0,%0,1\n\
357 stdcx. %0,0,%1 \n\ 357 stdcx. %0,0,%1 \n\
358 bne- 1b" 358 bne- 1b"
359 PPC_ACQUIRE_BARRIER 359 PPC_ATOMIC_EXIT_BARRIER
360 : "=&r" (t) 360 : "=&r" (t)
361 : "r" (&v->counter) 361 : "r" (&v->counter)
362 : "cc", "xer", "memory"); 362 : "cc", "xer", "memory");
@@ -393,12 +393,12 @@ static __inline__ long atomic64_dec_return(atomic64_t *v)
393 long t; 393 long t;
394 394
395 __asm__ __volatile__( 395 __asm__ __volatile__(
396 PPC_RELEASE_BARRIER 396 PPC_ATOMIC_ENTRY_BARRIER
397"1: ldarx %0,0,%1 # atomic64_dec_return\n\ 397"1: ldarx %0,0,%1 # atomic64_dec_return\n\
398 addic %0,%0,-1\n\ 398 addic %0,%0,-1\n\
399 stdcx. %0,0,%1\n\ 399 stdcx. %0,0,%1\n\
400 bne- 1b" 400 bne- 1b"
401 PPC_ACQUIRE_BARRIER 401 PPC_ATOMIC_EXIT_BARRIER
402 : "=&r" (t) 402 : "=&r" (t)
403 : "r" (&v->counter) 403 : "r" (&v->counter)
404 : "cc", "xer", "memory"); 404 : "cc", "xer", "memory");
@@ -418,13 +418,13 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
418 long t; 418 long t;
419 419
420 __asm__ __volatile__( 420 __asm__ __volatile__(
421 PPC_RELEASE_BARRIER 421 PPC_ATOMIC_ENTRY_BARRIER
422"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\ 422"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
423 addic. %0,%0,-1\n\ 423 addic. %0,%0,-1\n\
424 blt- 2f\n\ 424 blt- 2f\n\
425 stdcx. %0,0,%1\n\ 425 stdcx. %0,0,%1\n\
426 bne- 1b" 426 bne- 1b"
427 PPC_ACQUIRE_BARRIER 427 PPC_ATOMIC_EXIT_BARRIER
428 "\n\ 428 "\n\
4292:" : "=&r" (t) 4292:" : "=&r" (t)
430 : "r" (&v->counter) 430 : "r" (&v->counter)
@@ -450,14 +450,14 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
450 long t; 450 long t;
451 451
452 __asm__ __volatile__ ( 452 __asm__ __volatile__ (
453 PPC_RELEASE_BARRIER 453 PPC_ATOMIC_ENTRY_BARRIER
454"1: ldarx %0,0,%1 # __atomic_add_unless\n\ 454"1: ldarx %0,0,%1 # __atomic_add_unless\n\
455 cmpd 0,%0,%3 \n\ 455 cmpd 0,%0,%3 \n\
456 beq- 2f \n\ 456 beq- 2f \n\
457 add %0,%2,%0 \n" 457 add %0,%2,%0 \n"
458" stdcx. %0,0,%1 \n\ 458" stdcx. %0,0,%1 \n\
459 bne- 1b \n" 459 bne- 1b \n"
460 PPC_ACQUIRE_BARRIER 460 PPC_ATOMIC_EXIT_BARRIER
461" subf %0,%2,%0 \n\ 461" subf %0,%2,%0 \n\
4622:" 4622:"
463 : "=&r" (t) 463 : "=&r" (t)
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index e137afcc10fa..efdc92618b38 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -124,14 +124,14 @@ static __inline__ unsigned long fn( \
124 return (old & mask); \ 124 return (old & mask); \
125} 125}
126 126
127DEFINE_TESTOP(test_and_set_bits, or, PPC_RELEASE_BARRIER, 127DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER,
128 PPC_ACQUIRE_BARRIER, 0) 128 PPC_ATOMIC_EXIT_BARRIER, 0)
129DEFINE_TESTOP(test_and_set_bits_lock, or, "", 129DEFINE_TESTOP(test_and_set_bits_lock, or, "",
130 PPC_ACQUIRE_BARRIER, 1) 130 PPC_ACQUIRE_BARRIER, 1)
131DEFINE_TESTOP(test_and_clear_bits, andc, PPC_RELEASE_BARRIER, 131DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER,
132 PPC_ACQUIRE_BARRIER, 0) 132 PPC_ATOMIC_EXIT_BARRIER, 0)
133DEFINE_TESTOP(test_and_change_bits, xor, PPC_RELEASE_BARRIER, 133DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
134 PPC_ACQUIRE_BARRIER, 0) 134 PPC_ATOMIC_EXIT_BARRIER, 0)
135 135
136static __inline__ int test_and_set_bit(unsigned long nr, 136static __inline__ int test_and_set_bit(unsigned long nr,
137 volatile unsigned long *addr) 137 volatile unsigned long *addr)
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index 91010e8f8479..88e602f6430d 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -100,7 +100,8 @@ struct compat_statfs {
100 compat_fsid_t f_fsid; 100 compat_fsid_t f_fsid;
101 int f_namelen; /* SunOS ignores this field. */ 101 int f_namelen; /* SunOS ignores this field. */
102 int f_frsize; 102 int f_frsize;
103 int f_spare[5]; 103 int f_flags;
104 int f_spare[4];
104}; 105};
105 106
106#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff 107#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 16d25c0974be..d57c08acedfc 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -37,4 +37,6 @@ struct pdev_archdata {
37 u64 dma_mask; 37 u64 dma_mask;
38}; 38};
39 39
40#define ARCH_HAS_DMA_GET_REQUIRED_MASK
41
40#endif /* _ASM_POWERPC_DEVICE_H */ 42#endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 3a6c586c4e40..14db29b18d0e 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -48,6 +48,8 @@
48#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000) 48#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
49#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000) 49#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
50#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000) 50#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
51#define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000)
52#define FW_FEATURE_OPALv2 ASM_CONST(0x0000000020000000)
51 53
52#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
53 55
@@ -65,6 +67,8 @@ enum {
65 FW_FEATURE_PSERIES_ALWAYS = 0, 67 FW_FEATURE_PSERIES_ALWAYS = 0,
66 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 68 FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
67 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR, 69 FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
70 FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2,
71 FW_FEATURE_POWERNV_ALWAYS = 0,
68 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 72 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
69 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 73 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
70 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT, 74 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
@@ -78,6 +82,9 @@ enum {
78#ifdef CONFIG_PPC_ISERIES 82#ifdef CONFIG_PPC_ISERIES
79 FW_FEATURE_ISERIES_POSSIBLE | 83 FW_FEATURE_ISERIES_POSSIBLE |
80#endif 84#endif
85#ifdef CONFIG_PPC_POWERNV
86 FW_FEATURE_POWERNV_POSSIBLE |
87#endif
81#ifdef CONFIG_PPC_PS3 88#ifdef CONFIG_PPC_PS3
82 FW_FEATURE_PS3_POSSIBLE | 89 FW_FEATURE_PS3_POSSIBLE |
83#endif 90#endif
@@ -95,6 +102,9 @@ enum {
95#ifdef CONFIG_PPC_ISERIES 102#ifdef CONFIG_PPC_ISERIES
96 FW_FEATURE_ISERIES_ALWAYS & 103 FW_FEATURE_ISERIES_ALWAYS &
97#endif 104#endif
105#ifdef CONFIG_PPC_POWERNV
106 FW_FEATURE_POWERNV_ALWAYS &
107#endif
98#ifdef CONFIG_PPC_PS3 108#ifdef CONFIG_PPC_PS3
99 FW_FEATURE_PS3_ALWAYS & 109 FW_FEATURE_PS3_ALWAYS &
100#endif 110#endif
diff --git a/arch/powerpc/include/asm/floppy.h b/arch/powerpc/include/asm/floppy.h
index 24bd34c57e9d..936a904ae78c 100644
--- a/arch/powerpc/include/asm/floppy.h
+++ b/arch/powerpc/include/asm/floppy.h
@@ -108,10 +108,10 @@ static int fd_request_irq(void)
108{ 108{
109 if (can_use_virtual_dma) 109 if (can_use_virtual_dma)
110 return request_irq(FLOPPY_IRQ, floppy_hardint, 110 return request_irq(FLOPPY_IRQ, floppy_hardint,
111 IRQF_DISABLED, "floppy", NULL); 111 0, "floppy", NULL);
112 else 112 else
113 return request_irq(FLOPPY_IRQ, floppy_interrupt, 113 return request_irq(FLOPPY_IRQ, floppy_interrupt,
114 IRQF_DISABLED, "floppy", NULL); 114 0, "floppy", NULL);
115} 115}
116 116
117static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) 117static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io)
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
index c94e4a3fe2ef..2a9cf845473b 100644
--- a/arch/powerpc/include/asm/futex.h
+++ b/arch/powerpc/include/asm/futex.h
@@ -11,12 +11,13 @@
11 11
12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
13 __asm__ __volatile ( \ 13 __asm__ __volatile ( \
14 PPC_RELEASE_BARRIER \ 14 PPC_ATOMIC_ENTRY_BARRIER \
15"1: lwarx %0,0,%2\n" \ 15"1: lwarx %0,0,%2\n" \
16 insn \ 16 insn \
17 PPC405_ERR77(0, %2) \ 17 PPC405_ERR77(0, %2) \
18"2: stwcx. %1,0,%2\n" \ 18"2: stwcx. %1,0,%2\n" \
19 "bne- 1b\n" \ 19 "bne- 1b\n" \
20 PPC_ATOMIC_EXIT_BARRIER \
20 "li %1,0\n" \ 21 "li %1,0\n" \
21"3: .section .fixup,\"ax\"\n" \ 22"3: .section .fixup,\"ax\"\n" \
22"4: li %1,%3\n" \ 23"4: li %1,%3\n" \
@@ -92,14 +93,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
92 return -EFAULT; 93 return -EFAULT;
93 94
94 __asm__ __volatile__ ( 95 __asm__ __volatile__ (
95 PPC_RELEASE_BARRIER 96 PPC_ATOMIC_ENTRY_BARRIER
96"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\ 97"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
97 cmpw 0,%1,%4\n\ 98 cmpw 0,%1,%4\n\
98 bne- 3f\n" 99 bne- 3f\n"
99 PPC405_ERR77(0,%3) 100 PPC405_ERR77(0,%3)
100"2: stwcx. %5,0,%3\n\ 101"2: stwcx. %5,0,%3\n\
101 bne- 1b\n" 102 bne- 1b\n"
102 PPC_ACQUIRE_BARRIER 103 PPC_ATOMIC_EXIT_BARRIER
103"3: .section .fixup,\"ax\"\n\ 104"3: .section .fixup,\"ax\"\n\
1044: li %0,%6\n\ 1054: li %0,%6\n\
105 b 3b\n\ 106 b 3b\n\
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 5856a66ab404..86004930a78e 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -1,15 +1,60 @@
1#ifndef _ASM_POWERPC_HUGETLB_H 1#ifndef _ASM_POWERPC_HUGETLB_H
2#define _ASM_POWERPC_HUGETLB_H 2#define _ASM_POWERPC_HUGETLB_H
3 3
4#ifdef CONFIG_HUGETLB_PAGE
4#include <asm/page.h> 5#include <asm/page.h>
5 6
7extern struct kmem_cache *hugepte_cache;
8extern void __init reserve_hugetlb_gpages(void);
9
10static inline pte_t *hugepd_page(hugepd_t hpd)
11{
12 BUG_ON(!hugepd_ok(hpd));
13 return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE);
14}
15
16static inline unsigned int hugepd_shift(hugepd_t hpd)
17{
18 return hpd.pd & HUGEPD_SHIFT_MASK;
19}
20
21static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
22 unsigned pdshift)
23{
24 /*
25 * On 32-bit, we have multiple higher-level table entries that point to
26 * the same hugepte. Just use the first one since they're all
27 * identical. So for that case, idx=0.
28 */
29 unsigned long idx = 0;
30
31 pte_t *dir = hugepd_page(*hpdp);
32#ifdef CONFIG_PPC64
33 idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(*hpdp);
34#endif
35
36 return dir + idx;
37}
38
6pte_t *huge_pte_offset_and_shift(struct mm_struct *mm, 39pte_t *huge_pte_offset_and_shift(struct mm_struct *mm,
7 unsigned long addr, unsigned *shift); 40 unsigned long addr, unsigned *shift);
8 41
9void flush_dcache_icache_hugepage(struct page *page); 42void flush_dcache_icache_hugepage(struct page *page);
10 43
44#if defined(CONFIG_PPC_MM_SLICES) || defined(CONFIG_PPC_SUBPAGE_PROT)
11int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, 45int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
12 unsigned long len); 46 unsigned long len);
47#else
48static inline int is_hugepage_only_range(struct mm_struct *mm,
49 unsigned long addr,
50 unsigned long len)
51{
52 return 0;
53}
54#endif
55
56void book3e_hugetlb_preload(struct mm_struct *mm, unsigned long ea, pte_t pte);
57void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
13 58
14void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, 59void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
15 unsigned long end, unsigned long floor, 60 unsigned long end, unsigned long floor,
@@ -50,8 +95,11 @@ static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
50static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, 95static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
51 unsigned long addr, pte_t *ptep) 96 unsigned long addr, pte_t *ptep)
52{ 97{
53 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 1); 98#ifdef CONFIG_PPC64
54 return __pte(old); 99 return __pte(pte_update(mm, addr, ptep, ~0UL, 1));
100#else
101 return __pte(pte_update(ptep, ~0UL, 0));
102#endif
55} 103}
56 104
57static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, 105static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
@@ -93,4 +141,15 @@ static inline void arch_release_hugepage(struct page *page)
93{ 141{
94} 142}
95 143
144#else /* ! CONFIG_HUGETLB_PAGE */
145static inline void reserve_hugetlb_gpages(void)
146{
147 pr_err("Cannot reserve gpages without hugetlb enabled\n");
148}
149static inline void flush_hugetlb_page(struct vm_area_struct *vma,
150 unsigned long vmaddr)
151{
152}
153#endif
154
96#endif /* _ASM_POWERPC_HUGETLB_H */ 155#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 8a33698c61bd..f921eb121d39 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -2,7 +2,7 @@
2#define _ASM_POWERPC_KEXEC_H 2#define _ASM_POWERPC_KEXEC_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#ifdef CONFIG_FSL_BOOKE 5#if defined(CONFIG_FSL_BOOKE) || defined(CONFIG_44x)
6 6
7/* 7/*
8 * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory 8 * On FSL-BookE we setup a 1:1 mapping which covers the first 2GiB of memory
diff --git a/arch/powerpc/include/asm/kvm.h b/arch/powerpc/include/asm/kvm.h
index a4f6c85431f8..0ad432bc81d6 100644
--- a/arch/powerpc/include/asm/kvm.h
+++ b/arch/powerpc/include/asm/kvm.h
@@ -276,6 +276,11 @@ struct kvm_guest_debug_arch {
276#define KVM_INTERRUPT_UNSET -2U 276#define KVM_INTERRUPT_UNSET -2U
277#define KVM_INTERRUPT_SET_LEVEL -3U 277#define KVM_INTERRUPT_SET_LEVEL -3U
278 278
279#define KVM_CPU_440 1
280#define KVM_CPU_E500V2 2
281#define KVM_CPU_3S_32 3
282#define KVM_CPU_3S_64 4
283
279/* for KVM_CAP_SPAPR_TCE */ 284/* for KVM_CAP_SPAPR_TCE */
280struct kvm_create_spapr_tce { 285struct kvm_create_spapr_tce {
281 __u64 liobn; 286 __u64 liobn;
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 98da010252a3..d4df013ad779 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -139,15 +139,14 @@ extern void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr);
139extern int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu); 139extern int kvmppc_emulate_paired_single(struct kvm_run *run, struct kvm_vcpu *vcpu);
140extern pfn_t kvmppc_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn); 140extern pfn_t kvmppc_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn);
141 141
142extern void kvmppc_handler_lowmem_trampoline(void); 142extern void kvmppc_entry_trampoline(void);
143extern void kvmppc_handler_trampoline_enter(void);
144extern void kvmppc_rmcall(ulong srr0, ulong srr1);
145extern void kvmppc_hv_entry_trampoline(void); 143extern void kvmppc_hv_entry_trampoline(void);
146extern void kvmppc_load_up_fpu(void); 144extern void kvmppc_load_up_fpu(void);
147extern void kvmppc_load_up_altivec(void); 145extern void kvmppc_load_up_altivec(void);
148extern void kvmppc_load_up_vsx(void); 146extern void kvmppc_load_up_vsx(void);
149extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst); 147extern u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst);
150extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst); 148extern ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst);
149extern int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd);
151 150
152static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu) 151static inline struct kvmppc_vcpu_book3s *to_book3s(struct kvm_vcpu *vcpu)
153{ 152{
@@ -382,6 +381,39 @@ static inline bool kvmppc_critical_section(struct kvm_vcpu *vcpu)
382} 381}
383#endif 382#endif
384 383
384static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
385 unsigned long pte_index)
386{
387 unsigned long rb, va_low;
388
389 rb = (v & ~0x7fUL) << 16; /* AVA field */
390 va_low = pte_index >> 3;
391 if (v & HPTE_V_SECONDARY)
392 va_low = ~va_low;
393 /* xor vsid from AVA */
394 if (!(v & HPTE_V_1TB_SEG))
395 va_low ^= v >> 12;
396 else
397 va_low ^= v >> 24;
398 va_low &= 0x7ff;
399 if (v & HPTE_V_LARGE) {
400 rb |= 1; /* L field */
401 if (cpu_has_feature(CPU_FTR_ARCH_206) &&
402 (r & 0xff000)) {
403 /* non-16MB large page, must be 64k */
404 /* (masks depend on page size) */
405 rb |= 0x1000; /* page encoding in LP field */
406 rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
407 rb |= (va_low & 0xfe); /* AVAL field (P7 doesn't seem to care) */
408 }
409 } else {
410 /* 4kB page */
411 rb |= (va_low & 0x7ff) << 12; /* remaining 11b of VA */
412 }
413 rb |= (v >> 54) & 0x300; /* B field */
414 return rb;
415}
416
385/* Magic register values loaded into r3 and r4 before the 'sc' assembly 417/* Magic register values loaded into r3 and r4 before the 'sc' assembly
386 * instruction for the OSI hypercalls */ 418 * instruction for the OSI hypercalls */
387#define OSI_SC_MAGIC_R3 0x113724FA 419#define OSI_SC_MAGIC_R3 0x113724FA
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index ef7b3688c3b6..1f2f5b6156bd 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -75,6 +75,8 @@ struct kvmppc_host_state {
75 ulong scratch0; 75 ulong scratch0;
76 ulong scratch1; 76 ulong scratch1;
77 u8 in_guest; 77 u8 in_guest;
78 u8 restore_hid5;
79 u8 napping;
78 80
79#ifdef CONFIG_KVM_BOOK3S_64_HV 81#ifdef CONFIG_KVM_BOOK3S_64_HV
80 struct kvm_vcpu *kvm_vcpu; 82 struct kvm_vcpu *kvm_vcpu;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index cc22b282d755..bf8af5d5d5dc 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -198,21 +198,29 @@ struct kvm_arch {
198 */ 198 */
199struct kvmppc_vcore { 199struct kvmppc_vcore {
200 int n_runnable; 200 int n_runnable;
201 int n_blocked; 201 int n_busy;
202 int num_threads; 202 int num_threads;
203 int entry_exit_count; 203 int entry_exit_count;
204 int n_woken; 204 int n_woken;
205 int nap_count; 205 int nap_count;
206 int napping_threads;
206 u16 pcpu; 207 u16 pcpu;
207 u8 vcore_running; 208 u8 vcore_state;
208 u8 in_guest; 209 u8 in_guest;
209 struct list_head runnable_threads; 210 struct list_head runnable_threads;
210 spinlock_t lock; 211 spinlock_t lock;
212 wait_queue_head_t wq;
211}; 213};
212 214
213#define VCORE_ENTRY_COUNT(vc) ((vc)->entry_exit_count & 0xff) 215#define VCORE_ENTRY_COUNT(vc) ((vc)->entry_exit_count & 0xff)
214#define VCORE_EXIT_COUNT(vc) ((vc)->entry_exit_count >> 8) 216#define VCORE_EXIT_COUNT(vc) ((vc)->entry_exit_count >> 8)
215 217
218/* Values for vcore_state */
219#define VCORE_INACTIVE 0
220#define VCORE_RUNNING 1
221#define VCORE_EXITING 2
222#define VCORE_SLEEPING 3
223
216struct kvmppc_pte { 224struct kvmppc_pte {
217 ulong eaddr; 225 ulong eaddr;
218 u64 vpage; 226 u64 vpage;
@@ -258,14 +266,6 @@ struct kvm_vcpu_arch {
258 ulong host_stack; 266 ulong host_stack;
259 u32 host_pid; 267 u32 host_pid;
260#ifdef CONFIG_PPC_BOOK3S 268#ifdef CONFIG_PPC_BOOK3S
261 ulong host_msr;
262 ulong host_r2;
263 void *host_retip;
264 ulong trampoline_lowmem;
265 ulong trampoline_enter;
266 ulong highmem_handler;
267 ulong rmcall;
268 ulong host_paca_phys;
269 struct kvmppc_slb slb[64]; 269 struct kvmppc_slb slb[64];
270 int slb_max; /* 1 + index of last valid entry in slb[] */ 270 int slb_max; /* 1 + index of last valid entry in slb[] */
271 int slb_nr; /* total number of entries in SLB */ 271 int slb_nr; /* total number of entries in SLB */
@@ -389,6 +389,9 @@ struct kvm_vcpu_arch {
389 u8 dcr_is_write; 389 u8 dcr_is_write;
390 u8 osi_needed; 390 u8 osi_needed;
391 u8 osi_enabled; 391 u8 osi_enabled;
392 u8 papr_enabled;
393 u8 sane;
394 u8 cpu_type;
392 u8 hcall_needed; 395 u8 hcall_needed;
393 396
394 u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */ 397 u32 cpr0_cfgaddr; /* holds the last set cpr0_cfgaddr */
@@ -408,11 +411,13 @@ struct kvm_vcpu_arch {
408 struct dtl *dtl; 411 struct dtl *dtl;
409 struct dtl *dtl_end; 412 struct dtl *dtl_end;
410 413
414 wait_queue_head_t *wqp;
411 struct kvmppc_vcore *vcore; 415 struct kvmppc_vcore *vcore;
412 int ret; 416 int ret;
413 int trap; 417 int trap;
414 int state; 418 int state;
415 int ptid; 419 int ptid;
420 bool timer_running;
416 wait_queue_head_t cpu_run; 421 wait_queue_head_t cpu_run;
417 422
418 struct kvm_vcpu_arch_shared *shared; 423 struct kvm_vcpu_arch_shared *shared;
@@ -428,8 +433,9 @@ struct kvm_vcpu_arch {
428#endif 433#endif
429}; 434};
430 435
431#define KVMPPC_VCPU_BUSY_IN_HOST 0 436/* Values for vcpu->arch.state */
432#define KVMPPC_VCPU_BLOCKED 1 437#define KVMPPC_VCPU_STOPPED 0
438#define KVMPPC_VCPU_BUSY_IN_HOST 1
433#define KVMPPC_VCPU_RUNNABLE 2 439#define KVMPPC_VCPU_RUNNABLE 2
434 440
435#endif /* __POWERPC_KVM_HOST_H__ */ 441#endif /* __POWERPC_KVM_HOST_H__ */
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index d121f49d62b8..46efd1a265c9 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -66,6 +66,7 @@ extern int kvmppc_emulate_instruction(struct kvm_run *run,
66extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu); 66extern int kvmppc_emulate_mmio(struct kvm_run *run, struct kvm_vcpu *vcpu);
67extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu); 67extern void kvmppc_emulate_dec(struct kvm_vcpu *vcpu);
68extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb); 68extern u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb);
69extern int kvmppc_sanity_check(struct kvm_vcpu *vcpu);
69 70
70/* Core-specific hooks */ 71/* Core-specific hooks */
71 72
diff --git a/arch/powerpc/include/asm/lv1call.h b/arch/powerpc/include/asm/lv1call.h
index 81713acf7529..f77c708c67a0 100644
--- a/arch/powerpc/include/asm/lv1call.h
+++ b/arch/powerpc/include/asm/lv1call.h
@@ -25,6 +25,7 @@
25#if !defined(__ASSEMBLY__) 25#if !defined(__ASSEMBLY__)
26 26
27#include <linux/types.h> 27#include <linux/types.h>
28#include <linux/export.h>
28 29
29/* lv1 call declaration macros */ 30/* lv1 call declaration macros */
30 31
@@ -315,7 +316,7 @@ LV1_CALL(gpu_context_free, 1, 0, 218 )
315LV1_CALL(gpu_context_iomap, 5, 0, 221 ) 316LV1_CALL(gpu_context_iomap, 5, 0, 221 )
316LV1_CALL(gpu_context_attribute, 6, 0, 225 ) 317LV1_CALL(gpu_context_attribute, 6, 0, 225 )
317LV1_CALL(gpu_context_intr, 1, 1, 227 ) 318LV1_CALL(gpu_context_intr, 1, 1, 227 )
318LV1_CALL(gpu_attribute, 5, 0, 228 ) 319LV1_CALL(gpu_attribute, 3, 0, 228 )
319LV1_CALL(get_rtc, 0, 2, 232 ) 320LV1_CALL(get_rtc, 0, 2, 232 )
320LV1_CALL(set_ppe_periodic_tracer_frequency, 1, 0, 240 ) 321LV1_CALL(set_ppe_periodic_tracer_frequency, 1, 0, 240 )
321LV1_CALL(start_ppe_periodic_tracer, 5, 0, 241 ) 322LV1_CALL(start_ppe_periodic_tracer, 5, 0, 241 )
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 47cacddb14cf..b540d6fcedd6 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -12,6 +12,7 @@
12#include <linux/seq_file.h> 12#include <linux/seq_file.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
15#include <linux/export.h>
15 16
16#include <asm/setup.h> 17#include <asm/setup.h>
17 18
@@ -85,8 +86,9 @@ struct machdep_calls {
85 void (*pci_dma_dev_setup)(struct pci_dev *dev); 86 void (*pci_dma_dev_setup)(struct pci_dev *dev);
86 void (*pci_dma_bus_setup)(struct pci_bus *bus); 87 void (*pci_dma_bus_setup)(struct pci_bus *bus);
87 88
88 /* Platform set_dma_mask override */ 89 /* Platform set_dma_mask and dma_get_required_mask overrides */
89 int (*dma_set_mask)(struct device *dev, u64 dma_mask); 90 int (*dma_set_mask)(struct device *dev, u64 dma_mask);
91 u64 (*dma_get_required_mask)(struct device *dev);
90 92
91 int (*probe)(void); 93 int (*probe)(void);
92 void (*setup_arch)(void); /* Optional, may be NULL */ 94 void (*setup_arch)(void); /* Optional, may be NULL */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 3ea0f9a259d8..0260ea5ec3c2 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -66,6 +66,7 @@
66#define MAS2_M 0x00000004 66#define MAS2_M 0x00000004
67#define MAS2_G 0x00000002 67#define MAS2_G 0x00000002
68#define MAS2_E 0x00000001 68#define MAS2_E 0x00000001
69#define MAS2_WIMGE_MASK 0x0000001f
69#define MAS2_EPN_MASK(size) (~0 << (size + 10)) 70#define MAS2_EPN_MASK(size) (~0 << (size + 10))
70#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags)) 71#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
71 72
@@ -80,6 +81,7 @@
80#define MAS3_SW 0x00000004 81#define MAS3_SW 0x00000004
81#define MAS3_UR 0x00000002 82#define MAS3_UR 0x00000002
82#define MAS3_SR 0x00000001 83#define MAS3_SR 0x00000001
84#define MAS3_BAP_MASK 0x0000003f
83#define MAS3_SPSIZE 0x0000003e 85#define MAS3_SPSIZE 0x0000003e
84#define MAS3_SPSIZE_SHIFT 1 86#define MAS3_SPSIZE_SHIFT 1
85 87
@@ -212,6 +214,11 @@ typedef struct {
212 unsigned int id; 214 unsigned int id;
213 unsigned int active; 215 unsigned int active;
214 unsigned long vdso_base; 216 unsigned long vdso_base;
217#ifdef CONFIG_PPC_MM_SLICES
218 u64 low_slices_psize; /* SLB page size encodings */
219 u64 high_slices_psize; /* 4 bits per slice for now */
220 u16 user_psize; /* page size index */
221#endif
215} mm_context_t; 222} mm_context_t;
216 223
217/* Page size definitions, common between 32 and 64-bit 224/* Page size definitions, common between 32 and 64-bit
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index b445e0af4c2b..db645ec842bd 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -262,8 +262,7 @@ extern void hash_failure_debug(unsigned long ea, unsigned long access,
262extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 262extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
263 unsigned long pstart, unsigned long prot, 263 unsigned long pstart, unsigned long prot,
264 int psize, int ssize); 264 int psize, int ssize);
265extern void add_gpage(unsigned long addr, unsigned long page_size, 265extern void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
266 unsigned long number_of_pages);
267extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); 266extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
268 267
269extern void hpte_init_native(void); 268extern void hpte_init_native(void);
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 698b30638681..f0145522cfba 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -175,14 +175,16 @@ extern u64 ppc64_rma_size;
175#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 175#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
176#define MMU_PAGE_256K 4 176#define MMU_PAGE_256K 4
177#define MMU_PAGE_1M 5 177#define MMU_PAGE_1M 5
178#define MMU_PAGE_8M 6 178#define MMU_PAGE_4M 6
179#define MMU_PAGE_16M 7 179#define MMU_PAGE_8M 7
180#define MMU_PAGE_256M 8 180#define MMU_PAGE_16M 8
181#define MMU_PAGE_1G 9 181#define MMU_PAGE_64M 9
182#define MMU_PAGE_16G 10 182#define MMU_PAGE_256M 10
183#define MMU_PAGE_64G 11 183#define MMU_PAGE_1G 11
184#define MMU_PAGE_COUNT 12 184#define MMU_PAGE_16G 12
185 185#define MMU_PAGE_64G 13
186
187#define MMU_PAGE_COUNT 14
186 188
187#if defined(CONFIG_PPC_STD_MMU_64) 189#if defined(CONFIG_PPC_STD_MMU_64)
188/* 64-bit classic hash table MMU */ 190/* 64-bit classic hash table MMU */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index df18989e78d4..e6fae49e0b74 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -273,8 +273,6 @@ struct mpic
273 unsigned int irq_count; 273 unsigned int irq_count;
274 /* Number of sources */ 274 /* Number of sources */
275 unsigned int num_sources; 275 unsigned int num_sources;
276 /* Number of CPUs */
277 unsigned int num_cpus;
278 /* default senses array */ 276 /* default senses array */
279 unsigned char *senses; 277 unsigned char *senses;
280 unsigned int senses_count; 278 unsigned int senses_count;
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
new file mode 100644
index 000000000000..2893e8f5406d
--- /dev/null
+++ b/arch/powerpc/include/asm/opal.h
@@ -0,0 +1,443 @@
1/*
2 * PowerNV OPAL definitions.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __OPAL_H
13#define __OPAL_H
14
15/****** Takeover interface ********/
16
17/* PAPR H-Call used to querty the HAL existence and/or instanciate
18 * it from within pHyp (tech preview only).
19 *
20 * This is exclusively used in prom_init.c
21 */
22
23#ifndef __ASSEMBLY__
24
25struct opal_takeover_args {
26 u64 k_image; /* r4 */
27 u64 k_size; /* r5 */
28 u64 k_entry; /* r6 */
29 u64 k_entry2; /* r7 */
30 u64 hal_addr; /* r8 */
31 u64 rd_image; /* r9 */
32 u64 rd_size; /* r10 */
33 u64 rd_loc; /* r11 */
34};
35
36extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
37
38extern long opal_do_takeover(struct opal_takeover_args *args);
39
40struct rtas_args;
41extern int opal_enter_rtas(struct rtas_args *args,
42 unsigned long data,
43 unsigned long entry);
44
45#endif /* __ASSEMBLY__ */
46
47/****** OPAL APIs ******/
48
49/* Return codes */
50#define OPAL_SUCCESS 0
51#define OPAL_PARAMETER -1
52#define OPAL_BUSY -2
53#define OPAL_PARTIAL -3
54#define OPAL_CONSTRAINED -4
55#define OPAL_CLOSED -5
56#define OPAL_HARDWARE -6
57#define OPAL_UNSUPPORTED -7
58#define OPAL_PERMISSION -8
59#define OPAL_NO_MEM -9
60#define OPAL_RESOURCE -10
61#define OPAL_INTERNAL_ERROR -11
62#define OPAL_BUSY_EVENT -12
63#define OPAL_HARDWARE_FROZEN -13
64
65/* API Tokens (in r0) */
66#define OPAL_CONSOLE_WRITE 1
67#define OPAL_CONSOLE_READ 2
68#define OPAL_RTC_READ 3
69#define OPAL_RTC_WRITE 4
70#define OPAL_CEC_POWER_DOWN 5
71#define OPAL_CEC_REBOOT 6
72#define OPAL_READ_NVRAM 7
73#define OPAL_WRITE_NVRAM 8
74#define OPAL_HANDLE_INTERRUPT 9
75#define OPAL_POLL_EVENTS 10
76#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
77#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
78#define OPAL_PCI_CONFIG_READ_BYTE 13
79#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
80#define OPAL_PCI_CONFIG_READ_WORD 15
81#define OPAL_PCI_CONFIG_WRITE_BYTE 16
82#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
83#define OPAL_PCI_CONFIG_WRITE_WORD 18
84#define OPAL_SET_XIVE 19
85#define OPAL_GET_XIVE 20
86#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
87#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
88#define OPAL_PCI_EEH_FREEZE_STATUS 23
89#define OPAL_PCI_SHPC 24
90#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
91#define OPAL_PCI_EEH_FREEZE_CLEAR 26
92#define OPAL_PCI_PHB_MMIO_ENABLE 27
93#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
94#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
95#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
96#define OPAL_PCI_SET_PE 31
97#define OPAL_PCI_SET_PELTV 32
98#define OPAL_PCI_SET_MVE 33
99#define OPAL_PCI_SET_MVE_ENABLE 34
100#define OPAL_PCI_GET_XIVE_REISSUE 35
101#define OPAL_PCI_SET_XIVE_REISSUE 36
102#define OPAL_PCI_SET_XIVE_PE 37
103#define OPAL_GET_XIVE_SOURCE 38
104#define OPAL_GET_MSI_32 39
105#define OPAL_GET_MSI_64 40
106#define OPAL_START_CPU 41
107#define OPAL_QUERY_CPU_STATUS 42
108#define OPAL_WRITE_OPPANEL 43
109#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
110#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
111#define OPAL_PCI_RESET 49
112
113#ifndef __ASSEMBLY__
114
115/* Other enums */
116enum OpalVendorApiTokens {
117 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
118};
119enum OpalFreezeState {
120 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
121 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
122 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
123 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
124 OPAL_EEH_STOPPED_RESET = 4,
125 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
126 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
127};
128enum OpalEehFreezeActionToken {
129 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
130 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
131 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
132};
133enum OpalPciStatusToken {
134 OPAL_EEH_PHB_NO_ERROR = 0,
135 OPAL_EEH_PHB_FATAL = 1,
136 OPAL_EEH_PHB_RECOVERABLE = 2,
137 OPAL_EEH_PHB_BUS_ERROR = 3,
138 OPAL_EEH_PCI_NO_DEVSEL = 4,
139 OPAL_EEH_PCI_TA = 5,
140 OPAL_EEH_PCIEX_UR = 6,
141 OPAL_EEH_PCIEX_CA = 7,
142 OPAL_EEH_PCI_MMIO_ERROR = 8,
143 OPAL_EEH_PCI_DMA_ERROR = 9
144};
145enum OpalShpcAction {
146 OPAL_SHPC_GET_LINK_STATE = 0,
147 OPAL_SHPC_GET_SLOT_STATE = 1
148};
149enum OpalShpcLinkState {
150 OPAL_SHPC_LINK_DOWN = 0,
151 OPAL_SHPC_LINK_UP = 1
152};
153enum OpalMmioWindowType {
154 OPAL_M32_WINDOW_TYPE = 1,
155 OPAL_M64_WINDOW_TYPE = 2,
156 OPAL_IO_WINDOW_TYPE = 3
157};
158enum OpalShpcSlotState {
159 OPAL_SHPC_DEV_NOT_PRESENT = 0,
160 OPAL_SHPC_DEV_PRESENT = 1
161};
162enum OpalExceptionHandler {
163 OPAL_MACHINE_CHECK_HANDLER = 1,
164 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
165 OPAL_SOFTPATCH_HANDLER = 3
166};
167enum OpalPendingState {
168 OPAL_EVENT_OPAL_INTERNAL = 0x1,
169 OPAL_EVENT_NVRAM = 0x2,
170 OPAL_EVENT_RTC = 0x4,
171 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
172 OPAL_EVENT_CONSOLE_INPUT = 0x10
173};
174
175/* Machine check related definitions */
176enum OpalMCE_Version {
177 OpalMCE_V1 = 1,
178};
179
180enum OpalMCE_Severity {
181 OpalMCE_SEV_NO_ERROR = 0,
182 OpalMCE_SEV_WARNING = 1,
183 OpalMCE_SEV_ERROR_SYNC = 2,
184 OpalMCE_SEV_FATAL = 3,
185};
186
187enum OpalMCE_Disposition {
188 OpalMCE_DISPOSITION_RECOVERED = 0,
189 OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
190};
191
192enum OpalMCE_Initiator {
193 OpalMCE_INITIATOR_UNKNOWN = 0,
194 OpalMCE_INITIATOR_CPU = 1,
195};
196
197enum OpalMCE_ErrorType {
198 OpalMCE_ERROR_TYPE_UNKNOWN = 0,
199 OpalMCE_ERROR_TYPE_UE = 1,
200 OpalMCE_ERROR_TYPE_SLB = 2,
201 OpalMCE_ERROR_TYPE_ERAT = 3,
202 OpalMCE_ERROR_TYPE_TLB = 4,
203};
204
205enum OpalMCE_UeErrorType {
206 OpalMCE_UE_ERROR_INDETERMINATE = 0,
207 OpalMCE_UE_ERROR_IFETCH = 1,
208 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
209 OpalMCE_UE_ERROR_LOAD_STORE = 3,
210 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
211};
212
213enum OpalMCE_SlbErrorType {
214 OpalMCE_SLB_ERROR_INDETERMINATE = 0,
215 OpalMCE_SLB_ERROR_PARITY = 1,
216 OpalMCE_SLB_ERROR_MULTIHIT = 2,
217};
218
219enum OpalMCE_EratErrorType {
220 OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
221 OpalMCE_ERAT_ERROR_PARITY = 1,
222 OpalMCE_ERAT_ERROR_MULTIHIT = 2,
223};
224
225enum OpalMCE_TlbErrorType {
226 OpalMCE_TLB_ERROR_INDETERMINATE = 0,
227 OpalMCE_TLB_ERROR_PARITY = 1,
228 OpalMCE_TLB_ERROR_MULTIHIT = 2,
229};
230
231enum OpalThreadStatus {
232 OPAL_THREAD_INACTIVE = 0x0,
233 OPAL_THREAD_STARTED = 0x1
234};
235
236enum OpalPciBusCompare {
237 OpalPciBusAny = 0, /* Any bus number match */
238 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
239 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
240 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
241 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
242 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
243 OpalPciBusAll = 7, /* Match bus number exactly */
244};
245
246enum OpalDeviceCompare {
247 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
248 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
249};
250
251enum OpalFuncCompare {
252 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
253 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
254};
255
256enum OpalPeAction {
257 OPAL_UNMAP_PE = 0,
258 OPAL_MAP_PE = 1
259};
260
261enum OpalPciResetAndReinitScope {
262 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
263 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
264 OPAL_PCI_IODA_RESET = 6,
265};
266
267enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
268
269struct opal_machine_check_event {
270 enum OpalMCE_Version version:8; /* 0x00 */
271 uint8_t in_use; /* 0x01 */
272 enum OpalMCE_Severity severity:8; /* 0x02 */
273 enum OpalMCE_Initiator initiator:8; /* 0x03 */
274 enum OpalMCE_ErrorType error_type:8; /* 0x04 */
275 enum OpalMCE_Disposition disposition:8; /* 0x05 */
276 uint8_t reserved_1[2]; /* 0x06 */
277 uint64_t gpr3; /* 0x08 */
278 uint64_t srr0; /* 0x10 */
279 uint64_t srr1; /* 0x18 */
280 union { /* 0x20 */
281 struct {
282 enum OpalMCE_UeErrorType ue_error_type:8;
283 uint8_t effective_address_provided;
284 uint8_t physical_address_provided;
285 uint8_t reserved_1[5];
286 uint64_t effective_address;
287 uint64_t physical_address;
288 uint8_t reserved_2[8];
289 } ue_error;
290
291 struct {
292 enum OpalMCE_SlbErrorType slb_error_type:8;
293 uint8_t effective_address_provided;
294 uint8_t reserved_1[6];
295 uint64_t effective_address;
296 uint8_t reserved_2[16];
297 } slb_error;
298
299 struct {
300 enum OpalMCE_EratErrorType erat_error_type:8;
301 uint8_t effective_address_provided;
302 uint8_t reserved_1[6];
303 uint64_t effective_address;
304 uint8_t reserved_2[16];
305 } erat_error;
306
307 struct {
308 enum OpalMCE_TlbErrorType tlb_error_type:8;
309 uint8_t effective_address_provided;
310 uint8_t reserved_1[6];
311 uint64_t effective_address;
312 uint8_t reserved_2[16];
313 } tlb_error;
314 } u;
315};
316
317typedef struct oppanel_line {
318 /* XXX */
319} oppanel_line_t;
320
321/* API functions */
322int64_t opal_console_write(int64_t term_number, int64_t *length,
323 const uint8_t *buffer);
324int64_t opal_console_read(int64_t term_number, int64_t *length,
325 uint8_t *buffer);
326int64_t opal_console_write_buffer_space(int64_t term_number,
327 int64_t *length);
328int64_t opal_rtc_read(uint32_t *year_month_day,
329 uint64_t *hour_minute_second_millisecond);
330int64_t opal_rtc_write(uint32_t year_month_day,
331 uint64_t hour_minute_second_millisecond);
332int64_t opal_cec_power_down(uint64_t request);
333int64_t opal_cec_reboot(void);
334int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
335int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
336int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
337int64_t opal_poll_events(uint64_t *outstanding_event_mask);
338int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
339 uint64_t tce_mem_size);
340int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
341 uint64_t tce_mem_size);
342int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
343 uint64_t offset, uint8_t *data);
344int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
345 uint64_t offset, uint16_t *data);
346int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
347 uint64_t offset, uint32_t *data);
348int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
349 uint64_t offset, uint8_t data);
350int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
351 uint64_t offset, uint16_t data);
352int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
353 uint64_t offset, uint32_t data);
354int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
355int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
356int64_t opal_register_exception_handler(uint64_t opal_exception,
357 uint64_t handler_address,
358 uint64_t glue_cache_line);
359int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
360 uint8_t *freeze_state,
361 uint16_t *pci_error_type,
362 uint64_t *phb_status);
363int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
364 uint64_t eeh_action_token);
365int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
366
367
368
369int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
370 uint16_t window_num, uint16_t enable);
371int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
372 uint16_t window_num,
373 uint64_t starting_real_address,
374 uint64_t starting_pci_address,
375 uint16_t segment_size);
376int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
377 uint16_t window_type, uint16_t window_num,
378 uint16_t segment_num);
379int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
380 uint64_t ivt_addr, uint64_t ivt_len,
381 uint64_t reject_array_addr,
382 uint64_t peltv_addr);
383int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
384 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
385 uint8_t pe_action);
386int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
387 uint8_t state);
388int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
389int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
390 uint32_t state);
391int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
392 uint8_t *p_bit, uint8_t *q_bit);
393int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
394 uint8_t p_bit, uint8_t q_bit);
395int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
396 uint32_t xive_num);
397int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
398 int32_t *interrupt_source_number);
399int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
400 uint8_t msi_range, uint32_t *msi_address,
401 uint32_t *message_data);
402int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
403 uint32_t xive_num, uint8_t msi_range,
404 uint64_t *msi_address, uint32_t *message_data);
405int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
406int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
407int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
408int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
409 uint16_t tce_levels, uint64_t tce_table_addr,
410 uint64_t tce_table_size, uint64_t tce_page_size);
411int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
412 uint16_t dma_window_number, uint64_t pci_start_addr,
413 uint64_t pci_mem_size);
414int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
415
416/* Internal functions */
417extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
418
419extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
420extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
421
422extern void hvc_opal_init_early(void);
423
424/* Internal functions */
425extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
426 int depth, void *data);
427
428extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
429extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
430
431extern void hvc_opal_init_early(void);
432
433struct rtc_time;
434extern int opal_set_rtc_time(struct rtc_time *tm);
435extern void opal_get_rtc_time(struct rtc_time *tm);
436extern unsigned long opal_get_boot_time(void);
437extern void opal_nvram_init(void);
438
439extern int opal_machine_check(struct pt_regs *regs);
440
441#endif /* __ASSEMBLY__ */
442
443#endif /* __OPAL_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index 516bfb3f47d9..17722c73ba2e 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -43,6 +43,7 @@ extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
43#define get_slb_shadow() (get_paca()->slb_shadow_ptr) 43#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
44 44
45struct task_struct; 45struct task_struct;
46struct opal_machine_check_event;
46 47
47/* 48/*
48 * Defines the layout of the paca. 49 * Defines the layout of the paca.
@@ -135,6 +136,13 @@ struct paca_struct {
135 u8 io_sync; /* writel() needs spin_unlock sync */ 136 u8 io_sync; /* writel() needs spin_unlock sync */
136 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 137 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
137 138
139#ifdef CONFIG_PPC_POWERNV
140 /* Pointer to OPAL machine check event structure set by the
141 * early exception handler for use by high level C handler
142 */
143 struct opal_machine_check_event *opal_mc_evt;
144#endif
145
138 /* Stuff for accurate time accounting */ 146 /* Stuff for accurate time accounting */
139 u64 user_time; /* accumulated usermode TB ticks */ 147 u64 user_time; /* accumulated usermode TB ticks */
140 u64 system_time; /* accumulated system TB ticks */ 148 u64 system_time; /* accumulated system TB ticks */
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 2cd664ef0a5e..dd9c4fd038e0 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -36,6 +36,18 @@
36 36
37#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT) 37#define PAGE_SIZE (ASM_CONST(1) << PAGE_SHIFT)
38 38
39#ifndef __ASSEMBLY__
40#ifdef CONFIG_HUGETLB_PAGE
41extern unsigned int HPAGE_SHIFT;
42#else
43#define HPAGE_SHIFT PAGE_SHIFT
44#endif
45#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
46#define HPAGE_MASK (~(HPAGE_SIZE - 1))
47#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
48#define HUGE_MAX_HSTATE (MMU_PAGE_COUNT-1)
49#endif
50
39/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */ 51/* We do define AT_SYSINFO_EHDR but don't use the gate mechanism */
40#define __HAVE_ARCH_GATE_AREA 1 52#define __HAVE_ARCH_GATE_AREA 1
41 53
@@ -158,6 +170,24 @@ extern phys_addr_t kernstart_addr;
158#define is_kernel_addr(x) ((x) >= PAGE_OFFSET) 170#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
159#endif 171#endif
160 172
173/*
174 * Use the top bit of the higher-level page table entries to indicate whether
175 * the entries we point to contain hugepages. This works because we know that
176 * the page tables live in kernel space. If we ever decide to support having
177 * page tables at arbitrary addresses, this breaks and will have to change.
178 */
179#ifdef CONFIG_PPC64
180#define PD_HUGE 0x8000000000000000
181#else
182#define PD_HUGE 0x80000000
183#endif
184
185/*
186 * Some number of bits at the level of the page table that points to
187 * a hugepte are used to encode the size. This masks those bits.
188 */
189#define HUGEPD_SHIFT_MASK 0x3f
190
161#ifndef __ASSEMBLY__ 191#ifndef __ASSEMBLY__
162 192
163#undef STRICT_MM_TYPECHECKS 193#undef STRICT_MM_TYPECHECKS
@@ -243,7 +273,6 @@ typedef unsigned long pgprot_t;
243#endif 273#endif
244 274
245typedef struct { signed long pd; } hugepd_t; 275typedef struct { signed long pd; } hugepd_t;
246#define HUGEPD_SHIFT_MASK 0x3f
247 276
248#ifdef CONFIG_HUGETLB_PAGE 277#ifdef CONFIG_HUGETLB_PAGE
249static inline int hugepd_ok(hugepd_t hpd) 278static inline int hugepd_ok(hugepd_t hpd)
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 9356262fd3cc..fb40ede6bc0d 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -64,17 +64,6 @@ extern void copy_page(void *to, void *from);
64/* Log 2 of page table size */ 64/* Log 2 of page table size */
65extern u64 ppc64_pft_size; 65extern u64 ppc64_pft_size;
66 66
67/* Large pages size */
68#ifdef CONFIG_HUGETLB_PAGE
69extern unsigned int HPAGE_SHIFT;
70#else
71#define HPAGE_SHIFT PAGE_SHIFT
72#endif
73#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
74#define HPAGE_MASK (~(HPAGE_SIZE - 1))
75#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
76#define HUGE_MAX_HSTATE (MMU_PAGE_COUNT-1)
77
78#endif /* __ASSEMBLY__ */ 67#endif /* __ASSEMBLY__ */
79 68
80#ifdef CONFIG_PPC_MM_SLICES 69#ifdef CONFIG_PPC_MM_SLICES
diff --git a/arch/powerpc/include/asm/pte-book3e.h b/arch/powerpc/include/asm/pte-book3e.h
index 082d515930a2..0156702ba24e 100644
--- a/arch/powerpc/include/asm/pte-book3e.h
+++ b/arch/powerpc/include/asm/pte-book3e.h
@@ -72,6 +72,9 @@
72#define PTE_RPN_SHIFT (24) 72#define PTE_RPN_SHIFT (24)
73#endif 73#endif
74 74
75#define PTE_WIMGE_SHIFT (19)
76#define PTE_BAP_SHIFT (2)
77
75/* On 32-bit, we never clear the top part of the PTE */ 78/* On 32-bit, we never clear the top part of the PTE */
76#ifdef CONFIG_PPC32 79#ifdef CONFIG_PPC32
77#define _PTE_NONE_MASK 0xffffffff00000000ULL 80#define _PTE_NONE_MASK 0xffffffff00000000ULL
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 0947b36e534c..5e0b6d511e14 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -196,7 +196,7 @@ static inline int qe_alive_during_sleep(void)
196 196
197/* Structure that defines QE firmware binary files. 197/* Structure that defines QE firmware binary files.
198 * 198 *
199 * See Documentation/powerpc/qe-firmware.txt for a description of these 199 * See Documentation/powerpc/qe_firmware.txt for a description of these
200 * fields. 200 * fields.
201 */ 201 */
202struct qe_firmware { 202struct qe_firmware {
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 9ec0b39f9ddc..03c48e819c8e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -31,7 +31,7 @@
31 31
32#define MSR_ MSR_ME | MSR_CE 32#define MSR_ MSR_ME | MSR_CE
33#define MSR_KERNEL MSR_ | MSR_64BIT 33#define MSR_KERNEL MSR_ | MSR_64BIT
34#define MSR_USER32 MSR_ | MSR_PR | MSR_EE | MSR_DE 34#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
35#define MSR_USER64 MSR_USER32 | MSR_64BIT 35#define MSR_USER64 MSR_USER32 | MSR_64BIT
36#elif defined (CONFIG_40x) 36#elif defined (CONFIG_40x)
37#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) 37#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
@@ -548,6 +548,9 @@
548#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 548#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
549#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 549#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
550 550
551/* Bit definitions for L1CSR2. */
552#define L1CSR2_DCWS 0x40000000 /* Data Cache write shadow */
553
551/* Bit definitions for L2CSR0. */ 554/* Bit definitions for L2CSR0. */
552#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 555#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
553#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ 556#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 58625d1e7802..41f69ae79d4e 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -249,10 +249,12 @@ extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
249#define ERR_FLAG_ALREADY_LOGGED 0x0 249#define ERR_FLAG_ALREADY_LOGGED 0x0
250#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */ 250#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
251#define ERR_TYPE_RTAS_LOG 0x2 /* from rtas event-scan */ 251#define ERR_TYPE_RTAS_LOG 0x2 /* from rtas event-scan */
252#define ERR_TYPE_KERNEL_PANIC 0x4 /* from panic() */ 252#define ERR_TYPE_KERNEL_PANIC 0x4 /* from die()/panic() */
253#define ERR_TYPE_KERNEL_PANIC_GZ 0x8 /* ditto, compressed */
253 254
254/* All the types and not flags */ 255/* All the types and not flags */
255#define ERR_TYPE_MASK (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC) 256#define ERR_TYPE_MASK \
257 (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC | ERR_TYPE_KERNEL_PANIC_GZ)
256 258
257#define RTAS_DEBUG KERN_DEBUG "RTAS: " 259#define RTAS_DEBUG KERN_DEBUG "RTAS: "
258 260
diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h
index 6fbce725c710..a0f358d4a00c 100644
--- a/arch/powerpc/include/asm/sections.h
+++ b/arch/powerpc/include/asm/sections.h
@@ -8,7 +8,7 @@
8 8
9#ifdef __powerpc64__ 9#ifdef __powerpc64__
10 10
11extern char _end[]; 11extern char __end_interrupts[];
12 12
13static inline int in_kernel_text(unsigned long addr) 13static inline int in_kernel_text(unsigned long addr)
14{ 14{
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 15a70b7f638b..adba970ce918 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -65,6 +65,7 @@ int generic_cpu_disable(void);
65void generic_cpu_die(unsigned int cpu); 65void generic_cpu_die(unsigned int cpu);
66void generic_mach_cpu_die(void); 66void generic_mach_cpu_die(void);
67void generic_set_cpu_dead(unsigned int cpu); 67void generic_set_cpu_dead(unsigned int cpu);
68int generic_check_cpu_restart(unsigned int cpu);
68#endif 69#endif
69 70
70#ifdef CONFIG_PPC64 71#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
index 54a47ea2c3aa..0c5fa3145615 100644
--- a/arch/powerpc/include/asm/sparsemem.h
+++ b/arch/powerpc/include/asm/sparsemem.h
@@ -16,7 +16,7 @@
16#endif /* CONFIG_SPARSEMEM */ 16#endif /* CONFIG_SPARSEMEM */
17 17
18#ifdef CONFIG_MEMORY_HOTPLUG 18#ifdef CONFIG_MEMORY_HOTPLUG
19extern void create_section_mapping(unsigned long start, unsigned long end); 19extern int create_section_mapping(unsigned long start, unsigned long end);
20extern int remove_section_mapping(unsigned long start, unsigned long end); 20extern int remove_section_mapping(unsigned long start, unsigned long end);
21#ifdef CONFIG_NUMA 21#ifdef CONFIG_NUMA
22extern int hot_add_scn_to_nid(unsigned long scn_addr); 22extern int hot_add_scn_to_nid(unsigned long scn_addr);
diff --git a/arch/powerpc/include/asm/spu.h b/arch/powerpc/include/asm/spu.h
index 0c8b35d75232..4e360bd4a35a 100644
--- a/arch/powerpc/include/asm/spu.h
+++ b/arch/powerpc/include/asm/spu.h
@@ -26,6 +26,7 @@
26 26
27#include <linux/workqueue.h> 27#include <linux/workqueue.h>
28#include <linux/sysdev.h> 28#include <linux/sysdev.h>
29#include <linux/mutex.h>
29 30
30#define LS_SIZE (256 * 1024) 31#define LS_SIZE (256 * 1024)
31#define LS_ADDR_MASK (LS_SIZE - 1) 32#define LS_ADDR_MASK (LS_SIZE - 1)
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index d7cab44643c5..e682a7143edb 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -13,6 +13,7 @@
13extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup; 13extern unsigned int __start___lwsync_fixup, __stop___lwsync_fixup;
14extern void do_lwsync_fixups(unsigned long value, void *fixup_start, 14extern void do_lwsync_fixups(unsigned long value, void *fixup_start,
15 void *fixup_end); 15 void *fixup_end);
16extern void do_final_fixups(void);
16 17
17static inline void eieio(void) 18static inline void eieio(void)
18{ 19{
@@ -41,11 +42,15 @@ static inline void isync(void)
41 START_LWSYNC_SECTION(97); \ 42 START_LWSYNC_SECTION(97); \
42 isync; \ 43 isync; \
43 MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup); 44 MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
44#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER) 45#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
45#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n" 46#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
47#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n"
48#define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n"
46#else 49#else
47#define PPC_ACQUIRE_BARRIER 50#define PPC_ACQUIRE_BARRIER
48#define PPC_RELEASE_BARRIER 51#define PPC_RELEASE_BARRIER
52#define PPC_ATOMIC_ENTRY_BARRIER
53#define PPC_ATOMIC_EXIT_BARRIER
49#endif 54#endif
50 55
51#endif /* __KERNEL__ */ 56#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index f6736b7da463..559ae1ee6706 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -171,7 +171,7 @@ SYSCALL_SPU(setresuid)
171SYSCALL_SPU(getresuid) 171SYSCALL_SPU(getresuid)
172SYSCALL(ni_syscall) 172SYSCALL(ni_syscall)
173SYSCALL_SPU(poll) 173SYSCALL_SPU(poll)
174COMPAT_SYS(nfsservctl) 174SYSCALL(ni_syscall)
175SYSCALL_SPU(setresgid) 175SYSCALL_SPU(setresgid)
176SYSCALL_SPU(getresgid) 176SYSCALL_SPU(getresgid)
177COMPAT_SYS_SPU(prctl) 177COMPAT_SYS_SPU(prctl)
@@ -354,3 +354,5 @@ COMPAT_SYS_SPU(clock_adjtime)
354SYSCALL_SPU(syncfs) 354SYSCALL_SPU(syncfs)
355COMPAT_SYS_SPU(sendmmsg) 355COMPAT_SYS_SPU(sendmmsg)
356SYSCALL_SPU(setns) 356SYSCALL_SPU(setns)
357COMPAT_SYS(process_vm_readv)
358COMPAT_SYS(process_vm_writev)
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 7ef0d90defc8..1e104af08483 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -19,14 +19,10 @@ struct device_node;
19#define RECLAIM_DISTANCE 10 19#define RECLAIM_DISTANCE 10
20 20
21/* 21/*
22 * Before going off node we want the VM to try and reclaim from the local 22 * Avoid creating an extra level of balancing (SD_ALLNODES) on the largest
23 * node. It does this if the remote distance is larger than RECLAIM_DISTANCE. 23 * POWER7 boxes which have a maximum of 32 nodes.
24 * With the default REMOTE_DISTANCE of 20 and the default RECLAIM_DISTANCE of
25 * 20, we never reclaim and go off node straight away.
26 *
27 * To fix this we choose a smaller value of RECLAIM_DISTANCE.
28 */ 24 */
29#define RECLAIM_DISTANCE 10 25#define SD_NODES_PER_DOMAIN 32
30 26
31#include <asm/mmzone.h> 27#include <asm/mmzone.h>
32 28
@@ -69,11 +65,11 @@ static inline int pcibus_to_node(struct pci_bus *bus)
69 .forkexec_idx = 0, \ 65 .forkexec_idx = 0, \
70 \ 66 \
71 .flags = 1*SD_LOAD_BALANCE \ 67 .flags = 1*SD_LOAD_BALANCE \
72 | 1*SD_BALANCE_NEWIDLE \ 68 | 0*SD_BALANCE_NEWIDLE \
73 | 1*SD_BALANCE_EXEC \ 69 | 1*SD_BALANCE_EXEC \
74 | 1*SD_BALANCE_FORK \ 70 | 1*SD_BALANCE_FORK \
75 | 0*SD_BALANCE_WAKE \ 71 | 0*SD_BALANCE_WAKE \
76 | 0*SD_WAKE_AFFINE \ 72 | 1*SD_WAKE_AFFINE \
77 | 0*SD_PREFER_LOCAL \ 73 | 0*SD_PREFER_LOCAL \
78 | 0*SD_SHARE_CPUPOWER \ 74 | 0*SD_SHARE_CPUPOWER \
79 | 0*SD_POWERSAVINGS_BALANCE \ 75 | 0*SD_POWERSAVINGS_BALANCE \
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 93e05d1b34b2..8338aef5a4d3 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -54,6 +54,10 @@ extern void __init udbg_init_40x_realmode(void);
54extern void __init udbg_init_cpm(void); 54extern void __init udbg_init_cpm(void);
55extern void __init udbg_init_usbgecko(void); 55extern void __init udbg_init_usbgecko(void);
56extern void __init udbg_init_wsp(void); 56extern void __init udbg_init_wsp(void);
57extern void __init udbg_init_ehv_bc(void);
58extern void __init udbg_init_ps3gelic(void);
59extern void __init udbg_init_debug_opal_raw(void);
60extern void __init udbg_init_debug_opal_hvsi(void);
57 61
58#endif /* __KERNEL__ */ 62#endif /* __KERNEL__ */
59#endif /* _ASM_POWERPC_UDBG_H */ 63#endif /* _ASM_POWERPC_UDBG_H */
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index b8b3f599362b..d3d1b5efd7eb 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -373,10 +373,12 @@
373#define __NR_syncfs 348 373#define __NR_syncfs 348
374#define __NR_sendmmsg 349 374#define __NR_sendmmsg 349
375#define __NR_setns 350 375#define __NR_setns 350
376#define __NR_process_vm_readv 351
377#define __NR_process_vm_writev 352
376 378
377#ifdef __KERNEL__ 379#ifdef __KERNEL__
378 380
379#define __NR_syscalls 351 381#define __NR_syscalls 353
380 382
381#define __NR__exit __NR_exit 383#define __NR__exit __NR_exit
382#define NR_syscalls __NR_syscalls 384#define NR_syscalls __NR_syscalls
diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
index b183a4062011..c48de98ba94e 100644
--- a/arch/powerpc/include/asm/xics.h
+++ b/arch/powerpc/include/asm/xics.h
@@ -15,8 +15,8 @@
15#define DEFAULT_PRIORITY 5 15#define DEFAULT_PRIORITY 5
16 16
17/* 17/*
18 * Mark IPIs as higher priority so we can take them inside interrupts that 18 * Mark IPIs as higher priority so we can take them inside interrupts
19 * arent marked IRQF_DISABLED 19 * FIXME: still true now?
20 */ 20 */
21#define IPI_PRIORITY 4 21#define IPI_PRIORITY 4
22 22
@@ -27,10 +27,18 @@
27#define MAX_NUM_PRIORITIES 3 27#define MAX_NUM_PRIORITIES 3
28 28
29/* Native ICP */ 29/* Native ICP */
30#ifdef CONFIG_PPC_ICP_NATIVE
30extern int icp_native_init(void); 31extern int icp_native_init(void);
32#else
33static inline int icp_native_init(void) { return -ENODEV; }
34#endif
31 35
32/* PAPR ICP */ 36/* PAPR ICP */
37#ifdef CONFIG_PPC_ICP_HV
33extern int icp_hv_init(void); 38extern int icp_hv_init(void);
39#else
40static inline int icp_hv_init(void) { return -ENODEV; }
41#endif
34 42
35/* ICP ops */ 43/* ICP ops */
36struct icp_ops { 44struct icp_ops {
@@ -51,7 +59,18 @@ extern const struct icp_ops *icp_ops;
51extern int ics_native_init(void); 59extern int ics_native_init(void);
52 60
53/* RTAS ICS */ 61/* RTAS ICS */
62#ifdef CONFIG_PPC_ICS_RTAS
54extern int ics_rtas_init(void); 63extern int ics_rtas_init(void);
64#else
65static inline int ics_rtas_init(void) { return -ENODEV; }
66#endif
67
68/* HAL ICS */
69#ifdef CONFIG_PPC_POWERNV
70extern int ics_opal_init(void);
71#else
72static inline int ics_opal_init(void) { return -ENODEV; }
73#endif
55 74
56/* ICS instance, hooked up to chip_data of an irq */ 75/* ICS instance, hooked up to chip_data of an irq */
57struct ics { 76struct ics {
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 17:59:20 -0500