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-rw-r--r--arch/powerpc/boot/dts/fsl/t4240rdb.dts213
1 files changed, 213 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t4240rdb.dts b/arch/powerpc/boot/dts/fsl/t4240rdb.dts
new file mode 100644
index 000000000000..6e820a875621
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+++ b/arch/powerpc/boot/dts/fsl/t4240rdb.dts
@@ -0,0 +1,213 @@
1/*
2 * T4240RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "t4240si-pre.dtsi"
36
37/ {
38 model = "fsl,T4240RDB";
39 compatible = "fsl,T4240RDB";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 ifc: localbus@ffe124000 {
45 reg = <0xf 0xfe124000 0 0x2000>;
46 ranges = <0 0 0xf 0xe8000000 0x08000000
47 2 0 0xf 0xff800000 0x00010000
48 3 0 0xf 0xffdf0000 0x00008000>;
49
50 nor@0,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "cfi-flash";
54 reg = <0x0 0x0 0x8000000>;
55
56 bank-width = <2>;
57 device-width = <1>;
58 };
59
60 nand@2,0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,ifc-nand";
64 reg = <0x2 0x0 0x10000>;
65 };
66 };
67
68 memory {
69 device_type = "memory";
70 };
71
72 reserved-memory {
73 #address-cells = <2>;
74 #size-cells = <2>;
75 ranges;
76
77 bman_fbpr: bman-fbpr {
78 size = <0 0x1000000>;
79 alignment = <0 0x1000000>;
80 };
81 qman_fqd: qman-fqd {
82 size = <0 0x400000>;
83 alignment = <0 0x400000>;
84 };
85 qman_pfdr: qman-pfdr {
86 size = <0 0x2000000>;
87 alignment = <0 0x2000000>;
88 };
89 };
90
91 dcsr: dcsr@f00000000 {
92 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
93 };
94
95 bportals: bman-portals@ff4000000 {
96 ranges = <0x0 0xf 0xf4000000 0x2000000>;
97 };
98
99 qportals: qman-portals@ff6000000 {
100 ranges = <0x0 0xf 0xf6000000 0x2000000>;
101 };
102
103 soc: soc@ffe000000 {
104 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
105 reg = <0xf 0xfe000000 0 0x00001000>;
106 spi@110000 {
107 flash@0 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "sst,sst25wf040";
111 reg = <0>;
112 spi-max-frequency = <40000000>; /* input clock */
113 };
114 };
115
116 i2c@118000 {
117 eeprom@52 {
118 compatible = "at24,24c256";
119 reg = <0x52>;
120 };
121 eeprom@54 {
122 compatible = "at24,24c256";
123 reg = <0x54>;
124 };
125 eeprom@56 {
126 compatible = "at24,24c256";
127 reg = <0x56>;
128 };
129 rtc@68 {
130 compatible = "dallas,ds1374";
131 reg = <0x68>;
132 interrupts = <0x1 0x1 0 0>;
133 };
134 };
135
136 sdhc@114000 {
137 voltage-ranges = <1800 1800 3300 3300>;
138 };
139 };
140
141 pci0: pcie@ffe240000 {
142 reg = <0xf 0xfe240000 0 0x10000>;
143 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
144 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
145 pcie@0 {
146 ranges = <0x02000000 0 0xe0000000
147 0x02000000 0 0xe0000000
148 0 0x20000000
149
150 0x01000000 0 0x00000000
151 0x01000000 0 0x00000000
152 0 0x00010000>;
153 };
154 };
155
156 pci1: pcie@ffe250000 {
157 reg = <0xf 0xfe250000 0 0x10000>;
158 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
159 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
160 pcie@0 {
161 ranges = <0x02000000 0 0xe0000000
162 0x02000000 0 0xe0000000
163 0 0x20000000
164
165 0x01000000 0 0x00000000
166 0x01000000 0 0x00000000
167 0 0x00010000>;
168 };
169 };
170
171 pci2: pcie@ffe260000 {
172 reg = <0xf 0xfe260000 0 0x1000>;
173 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
174 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
175 pcie@0 {
176 ranges = <0x02000000 0 0xe0000000
177 0x02000000 0 0xe0000000
178 0 0x20000000
179
180 0x01000000 0 0x00000000
181 0x01000000 0 0x00000000
182 0 0x00010000>;
183 };
184 };
185
186 pci3: pcie@ffe270000 {
187 reg = <0xf 0xfe270000 0 0x10000>;
188 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
189 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
190 pcie@0 {
191 ranges = <0x02000000 0 0xe0000000
192 0x02000000 0 0xe0000000
193 0 0x20000000
194
195 0x01000000 0 0x00000000
196 0x01000000 0 0x00000000
197 0 0x00010000>;
198 };
199 };
200
201 rio: rapidio@ffe0c0000 {
202 reg = <0xf 0xfe0c0000 0 0x11000>;
203
204 port1 {
205 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
206 };
207 port2 {
208 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
209 };
210 };
211};
212
213/include/ "t4240si-post.dtsi"
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