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-rw-r--r--arch/mips/netlogic/xlr/irq.c305
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diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
deleted file mode 100644
index fc822c8f0817..000000000000
--- a/arch/mips/netlogic/xlr/irq.c
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1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/init.h>
37#include <linux/linkage.h>
38#include <linux/interrupt.h>
39#include <linux/spinlock.h>
40#include <linux/mm.h>
41#include <linux/msi.h>
42#include <linux/irq.h>
43#include <linux/irqdesc.h>
44#include <linux/pci.h>
45
46#include <asm/mipsregs.h>
47
48#include <asm/netlogic/xlr/msidef.h>
49#include <asm/netlogic/xlr/iomap.h>
50#include <asm/netlogic/xlr/pic.h>
51#include <asm/netlogic/xlr/xlr.h>
52
53#include <asm/netlogic/interrupt.h>
54#include <asm/netlogic/mips-extns.h>
55
56static u64 nlm_irq_mask;
57static DEFINE_SPINLOCK(nlm_pic_lock);
58
59static void xlr_pic_enable(struct irq_data *d)
60{
61 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
62 unsigned long flags;
63 nlm_reg_t reg;
64 int irq = d->irq;
65
66 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
67
68 spin_lock_irqsave(&nlm_pic_lock, flags);
69 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
70 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
71 reg | (1 << 6) | (1 << 30) | (1 << 31));
72 spin_unlock_irqrestore(&nlm_pic_lock, flags);
73}
74
75static void xlr_pic_mask(struct irq_data *d)
76{
77 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
78 unsigned long flags;
79 nlm_reg_t reg;
80 int irq = d->irq;
81
82 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
83
84 spin_lock_irqsave(&nlm_pic_lock, flags);
85 reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
86 netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
87 reg | (1 << 6) | (1 << 30) | (0 << 31));
88 spin_unlock_irqrestore(&nlm_pic_lock, flags);
89}
90
91#ifdef CONFIG_PCI
92/* Extra ACK needed for XLR on chip PCI controller */
93static void xlr_pci_ack(struct irq_data *d)
94{
95 nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
96
97 netlogic_read_reg(pci_mmio, (0x140 >> 2));
98}
99
100/* Extra ACK needed for XLS on chip PCIe controller */
101static void xls_pcie_ack(struct irq_data *d)
102{
103 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
104
105 switch (d->irq) {
106 case PIC_PCIE_LINK0_IRQ:
107 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
108 break;
109 case PIC_PCIE_LINK1_IRQ:
110 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
111 break;
112 case PIC_PCIE_LINK2_IRQ:
113 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
114 break;
115 case PIC_PCIE_LINK3_IRQ:
116 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
117 break;
118 }
119}
120
121/* For XLS B silicon, the 3,4 PCI interrupts are different */
122static void xls_pcie_ack_b(struct irq_data *d)
123{
124 nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
125
126 switch (d->irq) {
127 case PIC_PCIE_LINK0_IRQ:
128 netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
129 break;
130 case PIC_PCIE_LINK1_IRQ:
131 netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
132 break;
133 case PIC_PCIE_XLSB0_LINK2_IRQ:
134 netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
135 break;
136 case PIC_PCIE_XLSB0_LINK3_IRQ:
137 netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
138 break;
139 }
140}
141#endif
142
143static void xlr_pic_ack(struct irq_data *d)
144{
145 unsigned long flags;
146 nlm_reg_t *mmio;
147 int irq = d->irq;
148 void *hd = irq_data_get_irq_handler_data(d);
149
150 WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
151
152 if (hd) {
153 void (*extra_ack)(void *) = hd;
154 extra_ack(d);
155 }
156 mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
157 spin_lock_irqsave(&nlm_pic_lock, flags);
158 netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
159 spin_unlock_irqrestore(&nlm_pic_lock, flags);
160}
161
162/*
163 * This chip definition handles interrupts routed thru the XLR
164 * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
165 * 0-31 wired the XLR PIC
166 */
167static struct irq_chip xlr_pic = {
168 .name = "XLR-PIC",
169 .irq_enable = xlr_pic_enable,
170 .irq_mask = xlr_pic_mask,
171 .irq_ack = xlr_pic_ack,
172};
173
174static void rsvd_irq_handler(struct irq_data *d)
175{
176 WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
177}
178
179/*
180 * Chip definition for CPU originated interrupts(timer, msg) and
181 * IPIs
182 */
183struct irq_chip nlm_cpu_intr = {
184 .name = "XLR-CPU-INTR",
185 .irq_enable = rsvd_irq_handler,
186 .irq_mask = rsvd_irq_handler,
187 .irq_ack = rsvd_irq_handler,
188};
189
190void __init init_xlr_irqs(void)
191{
192 nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
193 uint32_t thread_mask = 1;
194 int level, i;
195
196 pr_info("Interrupt thread mask [%x]\n", thread_mask);
197 for (i = 0; i < PIC_NUM_IRTS; i++) {
198 level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
199
200 /* Bind all PIC irqs to boot cpu */
201 netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
202
203 /*
204 * Use local scheduling and high polarity for all IRTs
205 * Invalidate all IRTs, by default
206 */
207 netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
208 (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
209 }
210
211 /* Make all IRQs as level triggered by default */
212 for (i = 0; i < NR_IRQS; i++) {
213 if (PIC_IRQ_IS_IRT(i))
214 irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
215 else
216 irq_set_chip_and_handler(i, &nlm_cpu_intr,
217 handle_percpu_irq);
218 }
219#ifdef CONFIG_SMP
220 irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
221 nlm_smp_function_ipi_handler);
222 irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
223 nlm_smp_resched_ipi_handler);
224 nlm_irq_mask |=
225 ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
226#endif
227
228#ifdef CONFIG_PCI
229 /*
230 * For PCI interrupts, we need to ack the PIC controller too, overload
231 * irq handler data to do this
232 */
233 if (nlm_chip_is_xls()) {
234 if (nlm_chip_is_xls_b()) {
235 irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
236 xls_pcie_ack_b);
237 irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
238 xls_pcie_ack_b);
239 irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
240 xls_pcie_ack_b);
241 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
242 xls_pcie_ack_b);
243 } else {
244 irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
245 irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
246 irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
247 irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
248 }
249 } else {
250 /* XLR PCI controller ACK */
251 irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
252 }
253#endif
254 /* unmask all PIC related interrupts. If no handler is installed by the
255 * drivers, it'll just ack the interrupt and return
256 */
257 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
258 nlm_irq_mask |= (1ULL << i);
259
260 nlm_irq_mask |= (1ULL << IRQ_TIMER);
261}
262
263void __init arch_init_irq(void)
264{
265 /* Initialize the irq descriptors */
266 init_xlr_irqs();
267 write_c0_eimr(nlm_irq_mask);
268}
269
270void __cpuinit nlm_smp_irq_init(void)
271{
272 /* set interrupt mask for non-zero cpus */
273 write_c0_eimr(nlm_irq_mask);
274}
275
276asmlinkage void plat_irq_dispatch(void)
277{
278 uint64_t eirr;
279 int i;
280
281 eirr = read_c0_eirr() & read_c0_eimr();
282 if (!eirr)
283 return;
284
285 /* no need of EIRR here, writing compare clears interrupt */
286 if (eirr & (1 << IRQ_TIMER)) {
287 do_IRQ(IRQ_TIMER);
288 return;
289 }
290
291 /* use dcltz: optimize below code */
292 for (i = 63; i != -1; i--) {
293 if (eirr & (1ULL << i))
294 break;
295 }
296 if (i == -1) {
297 pr_err("no interrupt !!\n");
298 return;
299 }
300
301 /* Ack eirr */
302 write_c0_eirr(1ULL << i);
303
304 do_IRQ(i);
305}
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