1 files changed, 15 insertions, 73 deletions

diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c
index 4c7c1558944a..dbb917403131 100644
--- a/arch/mips/kernel/uprobes.c
+++ b/arch/mips/kernel/uprobes.c
@@ -8,71 +8,12 @@
 #include <asm/branch.h>
 #include <asm/cpu-features.h>
 #include <asm/ptrace.h>
-#include <asm/inst.h>
+
+#include "probes-common.h"
 
 static inline int insn_has_delay_slot(const union mips_instruction insn)
 {
-        switch (insn.i_format.opcode) {
-        /*
-         * jr and jalr are in r_format format.
-         */
-        case spec_op:
-                switch (insn.r_format.func) {
-                case jalr_op:
-                case jr_op:
-                        return 1;
-                }
-                break;
-
-        /*
-         * This group contains:
-         * bltz_op, bgez_op, bltzl_op, bgezl_op,
-         * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
-         */
-        case bcond_op:
-                switch (insn.i_format.rt) {
-                case bltz_op:
-                case bltzl_op:
-                case bgez_op:
-                case bgezl_op:
-                case bltzal_op:
-                case bltzall_op:
-                case bgezal_op:
-                case bgezall_op:
-                case bposge32_op:
-                        return 1;
-                }
-                break;
-
-        /*
-         * These are unconditional and in j_format.
-         */
-        case jal_op:
-        case j_op:
-        case beq_op:
-        case beql_op:
-        case bne_op:
-        case bnel_op:
-        case blez_op: /* not really i_format */
-        case blezl_op:
-        case bgtz_op:
-        case bgtzl_op:
-                return 1;
-
-        /*
-         * And now the FPA/cp1 branch instructions.
-         */
-        case cop1_op:
-#ifdef CONFIG_CPU_CAVIUM_OCTEON
-        case lwc2_op: /* This is bbit0 on Octeon */
-        case ldc2_op: /* This is bbit032 on Octeon */
-        case swc2_op: /* This is bbit1 on Octeon */
-        case sdc2_op: /* This is bbit132 on Octeon */
-#endif
-                return 1;
-        }
-
-        return 0;
+        return __insn_has_delay_slot(insn);
 }
 
 /**
@@ -95,6 +36,12 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *aup,
                 return -EINVAL;
 
         inst.word = aup->insn[0];
+
+        if (__insn_is_compact_branch(inst)) {
+                pr_notice("Uprobes for compact branches are not supported\n");
+                return -EINVAL;
+        }
+
         aup->ixol[0] = aup->insn[insn_has_delay_slot(inst)];
         aup->ixol[1] = UPROBE_BRK_UPROBE_XOL;           /* NOP  */
 
@@ -282,19 +229,14 @@ int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
 void __weak arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
                                   void *src, unsigned long len)
 {
-        void *kaddr;
+        unsigned long kaddr, kstart;
 
         /* Initialize the slot */
-        kaddr = kmap_atomic(page);
-        memcpy(kaddr + (vaddr & ~PAGE_MASK), src, len);
-        kunmap_atomic(kaddr);
-
-        /*
-         * The MIPS version of flush_icache_range will operate safely on
-         * user space addresses and more importantly, it doesn't require a
-         * VMA argument.
-         */
-        flush_icache_range(vaddr, vaddr + len);
+        kaddr = (unsigned long)kmap_atomic(page);
+        kstart = kaddr + (vaddr & ~PAGE_MASK);
+        memcpy((void *)kstart, src, len);
+        flush_icache_range(kstart, kstart + len);
+        kunmap_atomic((void *)kaddr);
 }
 
 /**