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-rw-r--r--arch/mips/include/asm/addrspace.h3
-rw-r--r--arch/mips/include/asm/barrier.h96
-rw-r--r--arch/mips/include/asm/cacheflush.h5
-rw-r--r--arch/mips/include/asm/cpu-type.h3
-rw-r--r--arch/mips/include/asm/cpu.h1
-rw-r--r--arch/mips/include/asm/device.h5
-rw-r--r--arch/mips/include/asm/dma-coherence.h16
-rw-r--r--arch/mips/include/asm/dma-mapping.h10
-rw-r--r--arch/mips/include/asm/i8259.h12
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h14
-rw-r--r--arch/mips/include/asm/mach-generic/floppy.h6
-rw-r--r--arch/mips/include/asm/mach-generic/spaces.h8
-rw-r--r--arch/mips/include/asm/mach-ip27/spaces.h1
-rw-r--r--arch/mips/include/asm/mach-loongson32/irq.h41
-rw-r--r--arch/mips/include/asm/mach-loongson32/loongson1.h5
-rw-r--r--arch/mips/include/asm/mach-loongson32/platform.h1
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-clk.h34
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-mux.h61
-rw-r--r--arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h72
-rw-r--r--arch/mips/include/asm/mach-sead3/irq.h9
-rw-r--r--arch/mips/include/asm/mach-sead3/kernel-entry-init.h21
-rw-r--r--arch/mips/include/asm/mach-sead3/war.h24
-rw-r--r--arch/mips/include/asm/machine.h63
-rw-r--r--arch/mips/include/asm/mips-boards/sead3int.h32
-rw-r--r--arch/mips/include/asm/mips-cm.h1
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-board.h30
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mdio.h506
-rw-r--r--arch/mips/include/asm/pci.h60
-rw-r--r--arch/mips/include/asm/pgalloc.h6
-rw-r--r--arch/mips/include/asm/pm-cps.h6
-rw-r--r--arch/mips/include/asm/ptrace.h2
-rw-r--r--arch/mips/include/asm/smp.h14
-rw-r--r--arch/mips/include/asm/uaccess.h18
33 files changed, 449 insertions, 737 deletions
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index c5b04e752e97..4856adc8906e 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -126,8 +126,7 @@
126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) 126#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) 127#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) 128#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
129#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ 129#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
130 (_CONST64_(cm) << 59) | (a))
131 130
132/* 131/*
133 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting 132 * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index d296633d890e..a5eb1bb199a7 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -10,6 +10,102 @@
10 10
11#include <asm/addrspace.h> 11#include <asm/addrspace.h>
12 12
13/*
14 * Sync types defined by the MIPS architecture (document MD00087 table 6.5)
15 * These values are used with the sync instruction to perform memory barriers.
16 * Types of ordering guarantees available through the SYNC instruction:
17 * - Completion Barriers
18 * - Ordering Barriers
19 * As compared to the completion barrier, the ordering barrier is a
20 * lighter-weight operation as it does not require the specified instructions
21 * before the SYNC to be already completed. Instead it only requires that those
22 * specified instructions which are subsequent to the SYNC in the instruction
23 * stream are never re-ordered for processing ahead of the specified
24 * instructions which are before the SYNC in the instruction stream.
25 * This potentially reduces how many cycles the barrier instruction must stall
26 * before it completes.
27 * Implementations that do not use any of the non-zero values of stype to define
28 * different barriers, such as ordering barriers, must make those stype values
29 * act the same as stype zero.
30 */
31
32/*
33 * Completion barriers:
34 * - Every synchronizable specified memory instruction (loads or stores or both)
35 * that occurs in the instruction stream before the SYNC instruction must be
36 * already globally performed before any synchronizable specified memory
37 * instructions that occur after the SYNC are allowed to be performed, with
38 * respect to any other processor or coherent I/O module.
39 *
40 * - The barrier does not guarantee the order in which instruction fetches are
41 * performed.
42 *
43 * - A stype value of zero will always be defined such that it performs the most
44 * complete set of synchronization operations that are defined.This means
45 * stype zero always does a completion barrier that affects both loads and
46 * stores preceding the SYNC instruction and both loads and stores that are
47 * subsequent to the SYNC instruction. Non-zero values of stype may be defined
48 * by the architecture or specific implementations to perform synchronization
49 * behaviors that are less complete than that of stype zero. If an
50 * implementation does not use one of these non-zero values to define a
51 * different synchronization behavior, then that non-zero value of stype must
52 * act the same as stype zero completion barrier. This allows software written
53 * for an implementation with a lighter-weight barrier to work on another
54 * implementation which only implements the stype zero completion barrier.
55 *
56 * - A completion barrier is required, potentially in conjunction with SSNOP (in
57 * Release 1 of the Architecture) or EHB (in Release 2 of the Architecture),
58 * to guarantee that memory reference results are visible across operating
59 * mode changes. For example, a completion barrier is required on some
60 * implementations on entry to and exit from Debug Mode to guarantee that
61 * memory effects are handled correctly.
62 */
63
64/*
65 * stype 0 - A completion barrier that affects preceding loads and stores and
66 * subsequent loads and stores.
67 * Older instructions which must reach the load/store ordering point before the
68 * SYNC instruction completes: Loads, Stores
69 * Younger instructions which must reach the load/store ordering point only
70 * after the SYNC instruction completes: Loads, Stores
71 * Older instructions which must be globally performed when the SYNC instruction
72 * completes: Loads, Stores
73 */
74#define STYPE_SYNC 0x0
75
76/*
77 * Ordering barriers:
78 * - Every synchronizable specified memory instruction (loads or stores or both)
79 * that occurs in the instruction stream before the SYNC instruction must
80 * reach a stage in the load/store datapath after which no instruction
81 * re-ordering is possible before any synchronizable specified memory
82 * instruction which occurs after the SYNC instruction in the instruction
83 * stream reaches the same stage in the load/store datapath.
84 *
85 * - If any memory instruction before the SYNC instruction in program order,
86 * generates a memory request to the external memory and any memory
87 * instruction after the SYNC instruction in program order also generates a
88 * memory request to external memory, the memory request belonging to the
89 * older instruction must be globally performed before the time the memory
90 * request belonging to the younger instruction is globally performed.
91 *
92 * - The barrier does not guarantee the order in which instruction fetches are
93 * performed.
94 */
95
96/*
97 * stype 0x10 - An ordering barrier that affects preceding loads and stores and
98 * subsequent loads and stores.
99 * Older instructions which must reach the load/store ordering point before the
100 * SYNC instruction completes: Loads, Stores
101 * Younger instructions which must reach the load/store ordering point only
102 * after the SYNC instruction completes: Loads, Stores
103 * Older instructions which must be globally performed when the SYNC instruction
104 * completes: N/A
105 */
106#define STYPE_SYNC_MB 0x10
107
108
13#ifdef CONFIG_CPU_HAS_SYNC 109#ifdef CONFIG_CPU_HAS_SYNC
14#define __sync() \ 110#define __sync() \
15 __asm__ __volatile__( \ 111 __asm__ __volatile__( \
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 34ed22ec6c33..4812d1fed0c2 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -28,6 +28,7 @@
28 * - flush_cache_sigtramp() flush signal trampoline 28 * - flush_cache_sigtramp() flush signal trampoline
29 * - flush_icache_all() flush the entire instruction cache 29 * - flush_icache_all() flush the entire instruction cache
30 * - flush_data_cache_page() flushes a page from the data cache 30 * - flush_data_cache_page() flushes a page from the data cache
31 * - __flush_icache_user_range(start, end) flushes range of user instructions
31 */ 32 */
32 33
33 /* 34 /*
@@ -80,6 +81,10 @@ static inline void flush_icache_page(struct vm_area_struct *vma,
80 81
81extern void (*flush_icache_range)(unsigned long start, unsigned long end); 82extern void (*flush_icache_range)(unsigned long start, unsigned long end);
82extern void (*local_flush_icache_range)(unsigned long start, unsigned long end); 83extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
84extern void (*__flush_icache_user_range)(unsigned long start,
85 unsigned long end);
86extern void (*__local_flush_icache_user_range)(unsigned long start,
87 unsigned long end);
83 88
84extern void (*__flush_cache_vmap)(void); 89extern void (*__flush_cache_vmap)(void);
85 90
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index fbe1881f28fc..bdd6dc18e65c 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -24,7 +24,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
24 case CPU_LOONGSON3: 24 case CPU_LOONGSON3:
25#endif 25#endif
26 26
27#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B 27#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
28 defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
28 case CPU_LOONGSON1: 29 case CPU_LOONGSON1:
29#endif 30#endif
30 31
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f672df8b26d0..9a8372484edc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -240,6 +240,7 @@
240#define PRID_REV_VR4130 0x0080 240#define PRID_REV_VR4130 0x0080
241#define PRID_REV_34K_V1_0_2 0x0022 241#define PRID_REV_34K_V1_0_2 0x0022
242#define PRID_REV_LOONGSON1B 0x0020 242#define PRID_REV_LOONGSON1B 0x0020
243#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
243#define PRID_REV_LOONGSON2E 0x0002 244#define PRID_REV_LOONGSON2E 0x0002
244#define PRID_REV_LOONGSON2F 0x0003 245#define PRID_REV_LOONGSON2F 0x0003
245#define PRID_REV_LOONGSON3A_R1 0x0005 246#define PRID_REV_LOONGSON3A_R1 0x0005
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index c94fafba9e62..21c2082a0dfb 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -11,6 +11,11 @@ struct dma_map_ops;
11struct dev_archdata { 11struct dev_archdata {
12 /* DMA operations on that device */ 12 /* DMA operations on that device */
13 struct dma_map_ops *dma_ops; 13 struct dma_map_ops *dma_ops;
14
15#ifdef CONFIG_DMA_PERDEV_COHERENT
16 /* Non-zero if DMA is coherent with CPU caches */
17 bool dma_coherent;
18#endif
14}; 19};
15 20
16struct pdev_archdata { 21struct pdev_archdata {
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index bc5e85d579e6..72d0eab02afc 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,14 +9,22 @@
9#ifndef __ASM_DMA_COHERENCE_H 9#ifndef __ASM_DMA_COHERENCE_H
10#define __ASM_DMA_COHERENCE_H 10#define __ASM_DMA_COHERENCE_H
11 11
12#ifdef CONFIG_DMA_MAYBE_COHERENT 12enum coherent_io_user_state {
13extern int coherentio; 13 IO_COHERENCE_DEFAULT,
14 IO_COHERENCE_ENABLED,
15 IO_COHERENCE_DISABLED,
16};
17
18#if defined(CONFIG_DMA_PERDEV_COHERENT)
19/* Don't provide (hw_)coherentio to avoid misuse */
20#elif defined(CONFIG_DMA_MAYBE_COHERENT)
21extern enum coherent_io_user_state coherentio;
14extern int hw_coherentio; 22extern int hw_coherentio;
15#else 23#else
16#ifdef CONFIG_DMA_COHERENT 24#ifdef CONFIG_DMA_COHERENT
17#define coherentio 1 25#define coherentio IO_COHERENCE_ENABLED
18#else 26#else
19#define coherentio 0 27#define coherentio IO_COHERENCE_DISABLED
20#endif 28#endif
21#define hw_coherentio 0 29#define hw_coherentio 0
22#endif /* CONFIG_DMA_MAYBE_COHERENT */ 30#endif /* CONFIG_DMA_MAYBE_COHERENT */
diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 12fa79e2f1b4..7aa71b9b0258 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -32,4 +32,14 @@ static inline void dma_mark_clean(void *addr, size_t size) {}
32extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, 32extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
33 enum dma_data_direction direction); 33 enum dma_data_direction direction);
34 34
35#define arch_setup_dma_ops arch_setup_dma_ops
36static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
37 u64 size, const struct iommu_ops *iommu,
38 bool coherent)
39{
40#ifdef CONFIG_DMA_PERDEV_COHERENT
41 dev->archdata.dma_coherent = coherent;
42#endif
43}
44
35#endif /* _ASM_DMA_MAPPING_H */ 45#endif /* _ASM_DMA_MAPPING_H */
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index a7fbcd6ed13c..32229c77906a 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -37,12 +37,22 @@
37 37
38extern raw_spinlock_t i8259A_lock; 38extern raw_spinlock_t i8259A_lock;
39 39
40extern int i8259A_irq_pending(unsigned int irq);
41extern void make_8259A_irq(unsigned int irq); 40extern void make_8259A_irq(unsigned int irq);
42 41
43extern void init_i8259_irqs(void); 42extern void init_i8259_irqs(void);
44extern int i8259_of_init(struct device_node *node, struct device_node *parent); 43extern int i8259_of_init(struct device_node *node, struct device_node *parent);
45 44
45/**
46 * i8159_set_poll() - Override the i8259 polling function
47 * @poll: pointer to platform-specific polling function
48 *
49 * Call this to override the generic i8259 polling function, which directly
50 * accesses i8259 registers, with a platform specific one which may be faster
51 * in cases where hardware provides a more optimal means of polling for an
52 * interrupt.
53 */
54extern void i8259_set_poll(int (*poll)(void));
55
46/* 56/*
47 * Do the traditional i8259 interrupt polling thing. This is for the few 57 * Do the traditional i8259 interrupt polling thing. This is for the few
48 * cases where no better interrupt acknowledge method is available and we 58 * cases where no better interrupt acknowledge method is available and we
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 0f8a354fd468..61addb1677e9 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -49,7 +49,19 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
49 49
50static inline int plat_device_is_coherent(struct device *dev) 50static inline int plat_device_is_coherent(struct device *dev)
51{ 51{
52 return coherentio; 52#ifdef CONFIG_DMA_PERDEV_COHERENT
53 return dev->archdata.dma_coherent;
54#else
55 switch (coherentio) {
56 default:
57 case IO_COHERENCE_DEFAULT:
58 return hw_coherentio;
59 case IO_COHERENCE_ENABLED:
60 return 1;
61 case IO_COHERENCE_DISABLED:
62 return 0;
63 }
64#endif
53} 65}
54 66
55#ifndef plat_post_dma_flush 67#ifndef plat_post_dma_flush
diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index e2561d99a3fe..9ec2f6a5200b 100644
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -115,11 +115,7 @@ static inline unsigned long fd_getfdaddr1(void)
115 115
116static inline unsigned long fd_dma_mem_alloc(unsigned long size) 116static inline unsigned long fd_dma_mem_alloc(unsigned long size)
117{ 117{
118 unsigned long mem; 118 return __get_dma_pages(GFP_KERNEL, get_order(size));
119
120 mem = __get_dma_pages(GFP_KERNEL, get_order(size));
121
122 return mem;
123} 119}
124 120
125static inline void fd_dma_mem_free(unsigned long addr, unsigned long size) 121static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index afc96ecb9004..952b0fdfda0e 100644
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -12,6 +12,8 @@
12 12
13#include <linux/const.h> 13#include <linux/const.h>
14 14
15#include <asm/mipsregs.h>
16
15/* 17/*
16 * This gives the physical RAM offset. 18 * This gives the physical RAM offset.
17 */ 19 */
@@ -52,11 +54,7 @@
52#ifdef CONFIG_64BIT 54#ifdef CONFIG_64BIT
53 55
54#ifndef CAC_BASE 56#ifndef CAC_BASE
55#ifdef CONFIG_DMA_NONCOHERENT 57#define CAC_BASE PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0)
56#define CAC_BASE _AC(0x9800000000000000, UL)
57#else
58#define CAC_BASE _AC(0xa800000000000000, UL)
59#endif
60#endif 58#endif
61 59
62#ifndef IO_BASE 60#ifndef IO_BASE
diff --git a/arch/mips/include/asm/mach-ip27/spaces.h b/arch/mips/include/asm/mach-ip27/spaces.h
index b18802a0b17e..4775a1136a5b 100644
--- a/arch/mips/include/asm/mach-ip27/spaces.h
+++ b/arch/mips/include/asm/mach-ip27/spaces.h
@@ -19,6 +19,7 @@
19#define IO_BASE 0x9200000000000000 19#define IO_BASE 0x9200000000000000
20#define MSPEC_BASE 0x9400000000000000 20#define MSPEC_BASE 0x9400000000000000
21#define UNCAC_BASE 0x9600000000000000 21#define UNCAC_BASE 0x9600000000000000
22#define CAC_BASE 0xa800000000000000
22 23
23#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) 24#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
24#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) 25#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK))
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index c1c744197de4..8c01b304b7ec 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -36,9 +36,14 @@
36#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) 36#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
37 37
38#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) 38#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
39#if defined(CONFIG_LOONGSON1_LS1B)
39#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) 40#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
40#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) 41#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
41#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) 42#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
43#elif defined(CONFIG_LOONGSON1_LS1C)
44#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
45#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
46#endif
42#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) 47#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
43#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) 48#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
44#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) 49#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
@@ -47,6 +52,9 @@
47#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) 52#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
48#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) 53#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
49#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) 54#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
55#if defined(CONFIG_LOONGSON1_LS1C)
56#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
57#endif
50#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) 58#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
51#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) 59#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
52#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) 60#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
@@ -54,18 +62,49 @@
54#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) 62#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
55#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) 63#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
56#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) 64#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
65#if defined(CONFIG_LOONGSON1_LS1B)
57#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) 66#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
58#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) 67#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
59#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) 68#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
60#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) 69#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
61#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) 70#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
71#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
72#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
73#elif defined(CONFIG_LOONGSON1_LS1C)
74#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
75#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
76#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
77#endif
62 78
63#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) 79#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
64#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) 80#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
81#if defined(CONFIG_LOONGSON1_LS1B)
65#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) 82#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
66#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) 83#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
84#elif defined(CONFIG_LOONGSON1_LS1C)
85#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
86#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
87#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
88#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
89#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
90#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
91#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
92#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
93#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
94#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
95#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
96#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
97#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
98#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
99#endif
67 100
68#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) 101#if defined(CONFIG_LOONGSON1_LS1B)
102#define INTN 4
103#elif defined(CONFIG_LOONGSON1_LS1C)
104#define INTN 5
105#endif
106
107#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
69 108
70#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) 109#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
71 110
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 978f6df8970a..3584c40caf79 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -12,7 +12,11 @@
12#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H 12#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
13#define __ASM_MACH_LOONGSON32_LOONGSON1_H 13#define __ASM_MACH_LOONGSON32_LOONGSON1_H
14 14
15#if defined(CONFIG_LOONGSON1_LS1B)
15#define DEFAULT_MEMSIZE 256 /* If no memsize provided */ 16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17#elif defined(CONFIG_LOONGSON1_LS1C)
18#define DEFAULT_MEMSIZE 32
19#endif
16 20
17/* Loongson 1 Register Bases */ 21/* Loongson 1 Register Bases */
18#define LS1X_MUX_BASE 0x1fd00420 22#define LS1X_MUX_BASE 0x1fd00420
@@ -20,6 +24,7 @@
20#define LS1X_GPIO0_BASE 0x1fd010c0 24#define LS1X_GPIO0_BASE 0x1fd010c0
21#define LS1X_GPIO1_BASE 0x1fd010c4 25#define LS1X_GPIO1_BASE 0x1fd010c4
22#define LS1X_DMAC_BASE 0x1fd01160 26#define LS1X_DMAC_BASE 0x1fd01160
27#define LS1X_CBUS_BASE 0x1fd011c0
23#define LS1X_EHCI_BASE 0x1fe00000 28#define LS1X_EHCI_BASE 0x1fe00000
24#define LS1X_OHCI_BASE 0x1fe08000 29#define LS1X_OHCI_BASE 0x1fe08000
25#define LS1X_GMAC0_BASE 0x1fe10000 30#define LS1X_GMAC0_BASE 0x1fe10000
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index 672531aa9bef..7adc31364939 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -30,5 +30,6 @@ void __init ls1x_clk_init(void);
30void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata); 30void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
31void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata); 31void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata);
32void __init ls1x_serial_set_uartclk(struct platform_device *pdev); 32void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
33void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
33 34
34#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */ 35#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h
index 4d56fc38f0c4..e5e8f118f34b 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h
@@ -18,6 +18,7 @@
18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) 18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) 19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20 20
21#if defined(CONFIG_LOONGSON1_LS1B)
21/* Clock PLL Divisor Register Bits */ 22/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN BIT(31) 23#define DIV_DC_EN BIT(31)
23#define DIV_DC_RST BIT(30) 24#define DIV_DC_RST BIT(30)
@@ -48,4 +49,37 @@
48#define BYPASS_DDR_WIDTH 1 49#define BYPASS_DDR_WIDTH 1
49#define BYPASS_CPU_WIDTH 1 50#define BYPASS_CPU_WIDTH 1
50 51
52#elif defined(CONFIG_LOONGSON1_LS1C)
53/* PLL/SDRAM Frequency configuration register Bits */
54#define PLL_VALID BIT(31)
55#define FRAC_N GENMASK(23, 16)
56#define RST_TIME GENMASK(3, 2)
57#define SDRAM_DIV GENMASK(1, 0)
58
59/* CPU/CAMERA/DC Frequency configuration register Bits */
60#define DIV_DC_EN BIT(31)
61#define DIV_DC GENMASK(30, 24)
62#define DIV_CAM_EN BIT(23)
63#define DIV_CAM GENMASK(22, 16)
64#define DIV_CPU_EN BIT(15)
65#define DIV_CPU GENMASK(14, 8)
66#define DIV_DC_SEL_EN BIT(5)
67#define DIV_DC_SEL BIT(4)
68#define DIV_CAM_SEL_EN BIT(3)
69#define DIV_CAM_SEL BIT(2)
70#define DIV_CPU_SEL_EN BIT(1)
71#define DIV_CPU_SEL BIT(0)
72
73#define DIV_DC_SHIFT 24
74#define DIV_CAM_SHIFT 16
75#define DIV_CPU_SHIFT 8
76#define DIV_DDR_SHIFT 0
77
78#define DIV_DC_WIDTH 7
79#define DIV_CAM_WIDTH 7
80#define DIV_CPU_WIDTH 7
81#define DIV_DDR_WIDTH 2
82
83#endif
84
51#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */ 85#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
index 7c394f93cb9e..4a0bdeb0eb9b 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-mux.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -18,6 +18,7 @@
18#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) 18#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) 19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
20 20
21#if defined(CONFIG_LOONGSON1_LS1B)
21/* MUX CTRL0 Register Bits */ 22/* MUX CTRL0 Register Bits */
22#define UART0_USE_PWM23 BIT(28) 23#define UART0_USE_PWM23 BIT(28)
23#define UART0_USE_PWM01 BIT(27) 24#define UART0_USE_PWM01 BIT(27)
@@ -64,4 +65,64 @@
64#define GMAC1_USE_PWM23 BIT(1) 65#define GMAC1_USE_PWM23 BIT(1)
65#define GMAC0_USE_PWM01 BIT(0) 66#define GMAC0_USE_PWM01 BIT(0)
66 67
68#elif defined(CONFIG_LOONGSON1_LS1C)
69
70/* SHUT_CTRL Register Bits */
71#define UART_SPLIT GENMASK(31, 30)
72#define OUTPUT_CLK GENMASK(29, 26)
73#define ADC_SHUT BIT(25)
74#define SDIO_SHUT BIT(24)
75#define DMA2_SHUT BIT(23)
76#define DMA1_SHUT BIT(22)
77#define DMA0_SHUT BIT(21)
78#define SPI1_SHUT BIT(20)
79#define SPI0_SHUT BIT(19)
80#define I2C2_SHUT BIT(18)
81#define I2C1_SHUT BIT(17)
82#define I2C0_SHUT BIT(16)
83#define AC97_SHUT BIT(15)
84#define I2S_SHUT BIT(14)
85#define UART3_SHUT BIT(13)
86#define UART2_SHUT BIT(12)
87#define UART1_SHUT BIT(11)
88#define UART0_SHUT BIT(10)
89#define CAN1_SHUT BIT(9)
90#define CAN0_SHUT BIT(8)
91#define ECC_SHUT BIT(7)
92#define GMAC_SHUT BIT(6)
93#define USBHOST_SHUT BIT(5)
94#define USBOTG_SHUT BIT(4)
95#define SDRAM_SHUT BIT(3)
96#define SRAM_SHUT BIT(2)
97#define CAM_SHUT BIT(1)
98#define LCD_SHUT BIT(0)
99
100#define UART_SPLIT_SHIFT 30
101#define OUTPUT_CLK_SHIFT 26
102
103/* MISC_CTRL Register Bits */
104#define USBHOST_RSTN BIT(31)
105#define PHY_INTF_SELI GENMASK(30, 28)
106#define AC97_EN BIT(25)
107#define SDIO_DMA_EN GENMASK(24, 23)
108#define ADC_DMA_EN BIT(22)
109#define SDIO_USE_SPI1 BIT(17)
110#define SDIO_USE_SPI0 BIT(16)
111#define SRAM_CTRL GENMASK(15, 0)
112
113#define PHY_INTF_SELI_SHIFT 28
114#define SDIO_DMA_EN_SHIFT 23
115#define SRAM_CTRL_SHIFT 0
116
117#define LS1X_CBUS_REG(n, x) \
118 ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
119
120#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
121#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
122#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
123#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
124#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
125
126#endif
127
67#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ 128#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
deleted file mode 100644
index bfbd7035d4c5..000000000000
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Chris Dearman
7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
8 */
9#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
11
12
13/*
14 * CPU feature overrides for MIPS boards
15 */
16#ifdef CONFIG_CPU_MIPS32
17#define cpu_has_tlb 1
18#define cpu_has_4kex 1
19#define cpu_has_4k_cache 1
20/* #define cpu_has_fpu ? */
21/* #define cpu_has_32fpr ? */
22#define cpu_has_counter 1
23/* #define cpu_has_watch ? */
24#define cpu_has_divec 1
25#define cpu_has_vce 0
26/* #define cpu_has_cache_cdex_p ? */
27/* #define cpu_has_cache_cdex_s ? */
28/* #define cpu_has_prefetch ? */
29#define cpu_has_mcheck 1
30/* #define cpu_has_ejtag ? */
31#ifdef CONFIG_CPU_MICROMIPS
32#define cpu_has_llsc 0
33#else
34#define cpu_has_llsc 1
35#endif
36/* #define cpu_has_vtag_icache ? */
37/* #define cpu_has_dc_aliases ? */
38/* #define cpu_has_ic_fills_f_dc ? */
39#define cpu_has_nofpuex 0
40/* #define cpu_has_64bits ? */
41/* #define cpu_has_64bit_zero_reg ? */
42/* #define cpu_has_inclusive_pcaches ? */
43#define cpu_icache_snoops_remote_store 1
44#endif
45
46#ifdef CONFIG_CPU_MIPS64
47#define cpu_has_tlb 1
48#define cpu_has_4kex 1
49#define cpu_has_4k_cache 1
50/* #define cpu_has_fpu ? */
51/* #define cpu_has_32fpr ? */
52#define cpu_has_counter 1
53/* #define cpu_has_watch ? */
54#define cpu_has_divec 1
55#define cpu_has_vce 0
56/* #define cpu_has_cache_cdex_p ? */
57/* #define cpu_has_cache_cdex_s ? */
58/* #define cpu_has_prefetch ? */
59#define cpu_has_mcheck 1
60/* #define cpu_has_ejtag ? */
61#define cpu_has_llsc 1
62/* #define cpu_has_vtag_icache ? */
63/* #define cpu_has_dc_aliases ? */
64/* #define cpu_has_ic_fills_f_dc ? */
65#define cpu_has_nofpuex 0
66/* #define cpu_has_64bits ? */
67/* #define cpu_has_64bit_zero_reg ? */
68/* #define cpu_has_inclusive_pcaches ? */
69#define cpu_icache_snoops_remote_store 1
70#endif
71
72#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
deleted file mode 100644
index 5d154cfbcf4c..000000000000
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_MACH_MIPS_IRQ_H
2#define __ASM_MACH_MIPS_IRQ_H
3
4#define NR_IRQS 256
5
6
7#include_next <irq.h>
8
9#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h b/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
deleted file mode 100644
index 6cccd4d558d7..000000000000
--- a/arch/mips/include/asm/mach-sead3/kernel-entry-init.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Chris Dearman (chris@mips.com)
7 * Copyright (C) 2007 Mips Technologies, Inc.
8 */
9#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
10#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
11
12 .macro kernel_entry_setup
13 .endm
14
15/*
16 * Do SMP slave processor setup necessary before we can safely execute C code.
17 */
18 .macro smp_slave_setup
19 .endm
20
21#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-sead3/war.h b/arch/mips/include/asm/mach-sead3/war.h
deleted file mode 100644
index d068fc411f47..000000000000
--- a/arch/mips/include/asm/mach-sead3/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
9#define __ASM_MIPS_MACH_MIPS_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 1
18#define MIPS_CACHE_SYNC_WAR 1
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 1
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/arch/mips/include/asm/machine.h b/arch/mips/include/asm/machine.h
new file mode 100644
index 000000000000..6b444cd9526f
--- /dev/null
+++ b/arch/mips/include/asm/machine.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright (C) 2016 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __MIPS_ASM_MACHINE_H__
12#define __MIPS_ASM_MACHINE_H__
13
14#include <linux/libfdt.h>
15#include <linux/of.h>
16
17struct mips_machine {
18 const struct of_device_id *matches;
19 const void *fdt;
20 bool (*detect)(void);
21 const void *(*fixup_fdt)(const void *fdt, const void *match_data);
22 unsigned int (*measure_hpt_freq)(void);
23};
24
25extern long __mips_machines_start;
26extern long __mips_machines_end;
27
28#define MIPS_MACHINE(name) \
29 static const struct mips_machine __mips_mach_##name \
30 __used __section(.mips.machines.init)
31
32#define for_each_mips_machine(mach) \
33 for ((mach) = (struct mips_machine *)&__mips_machines_start; \
34 (mach) < (struct mips_machine *)&__mips_machines_end; \
35 (mach)++)
36
37/**
38 * mips_machine_is_compatible() - check if a machine is compatible with an FDT
39 * @mach: the machine struct to check
40 * @fdt: the FDT to check for compatibility with
41 *
42 * Check whether the given machine @mach is compatible with the given flattened
43 * device tree @fdt, based upon the compatibility property of the root node.
44 *
45 * Return: the device id matched if any, else NULL
46 */
47static inline const struct of_device_id *
48mips_machine_is_compatible(const struct mips_machine *mach, const void *fdt)
49{
50 const struct of_device_id *match;
51
52 if (!mach->matches)
53 return NULL;
54
55 for (match = mach->matches; match->compatible; match++) {
56 if (fdt_node_check_compatible(fdt, 0, match->compatible) == 0)
57 return match;
58 }
59
60 return NULL;
61}
62
63#endif /* __MIPS_ASM_MACHINE_H__ */
diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
deleted file mode 100644
index 8932c7de0419..000000000000
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Douglas Leung <douglas@mips.com>
8 * Steven J. Hill <sjhill@mips.com>
9 */
10#ifndef _MIPS_SEAD3INT_H
11#define _MIPS_SEAD3INT_H
12
13#include <linux/irqchip/mips-gic.h>
14
15/* SEAD-3 GIC address space definitions. */
16#define GIC_BASE_ADDR 0x1b1c0000
17#define GIC_ADDRSPACE_SZ (128 * 1024)
18
19/* CPU interrupt offsets */
20#define CPU_INT_GIC 2
21#define CPU_INT_EHCI 2
22#define CPU_INT_UART0 4
23#define CPU_INT_UART1 4
24#define CPU_INT_NET 6
25
26/* GIC interrupt offsets */
27#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
28#define GIC_INT_UART1 GIC_SHARED_TO_HWIRQ(2)
29#define GIC_INT_UART0 GIC_SHARED_TO_HWIRQ(3)
30#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
31
32#endif /* !(_MIPS_SEAD3INT_H) */
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 4fafeefe65c2..2e4180797b21 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -359,6 +359,7 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
359/* GCR_Cx_COHERENCE register fields */ 359/* GCR_Cx_COHERENCE register fields */
360#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0 360#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF 0
361#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0) 361#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK (_ULCAST_(0xff) << 0)
362#define CM3_GCR_Cx_COHERENCE_COHEN_MSK (_ULCAST_(0x1) << 0)
362 363
363/* GCR_Cx_CONFIG register fields */ 364/* GCR_Cx_CONFIG register fields */
364#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10 365#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF 10
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index cda93aee712c..b4d19c21b62c 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -58,16 +58,6 @@ typedef enum {
58#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10 58#define CVMX_HELPER_BOARD_MGMT_IPD_PORT -10
59 59
60/** 60/**
61 * cvmx_override_board_link_get(int ipd_port) is a function
62 * pointer. It is meant to allow customization of the process of
63 * talking to a PHY to determine link speed. It is called every
64 * time a PHY must be polled for link status. Users should set
65 * this pointer to a function before calling any cvmx-helper
66 * operations.
67 */
68extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
69
70/**
71 * Return the MII PHY address associated with the given IPD 61 * Return the MII PHY address associated with the given IPD
72 * port. A result of -1 means there isn't a MII capable PHY 62 * port. A result of -1 means there isn't a MII capable PHY
73 * connected to this port. On chips supporting multiple MII 63 * connected to this port. On chips supporting multiple MII
@@ -86,26 +76,6 @@ extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
86extern int cvmx_helper_board_get_mii_address(int ipd_port); 76extern int cvmx_helper_board_get_mii_address(int ipd_port);
87 77
88/** 78/**
89 * This function as a board specific method of changing the PHY
90 * speed, duplex, and autonegotiation. This programs the PHY and
91 * not Octeon. This can be used to force Octeon's links to
92 * specific settings.
93 *
94 * @phy_addr: The address of the PHY to program
95 * @link_flags:
96 * Flags to control autonegotiation. Bit 0 is autonegotiation
97 * enable/disable to maintain backward compatibility.
98 * @link_info: Link speed to program. If the speed is zero and autonegotiation
99 * is enabled, all possible negotiation speeds are advertised.
100 *
101 * Returns Zero on success, negative on failure
102 */
103int cvmx_helper_board_link_set_phy(int phy_addr,
104 cvmx_helper_board_set_phy_link_flags_types_t
105 link_flags,
106 cvmx_helper_link_info_t link_info);
107
108/**
109 * This function is the board specific method of determining an 79 * This function is the board specific method of determining an
110 * ethernet ports link speed. Most Octeon boards have Marvell PHYs 80 * ethernet ports link speed. Most Octeon boards have Marvell PHYs
111 * and are handled by the fall through case. This function must be 81 * and are handled by the fall through case. This function must be
diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
deleted file mode 100644
index 9f6a4f32a83c..000000000000
--- a/arch/mips/include/asm/octeon/cvmx-mdio.h
+++ /dev/null
@@ -1,506 +0,0 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
31 * clause 22 and clause 45 operations.
32 *
33 */
34
35#ifndef __CVMX_MIO_H__
36#define __CVMX_MIO_H__
37
38#include <asm/octeon/cvmx-smix-defs.h>
39
40/**
41 * PHY register 0 from the 802.3 spec
42 */
43#define CVMX_MDIO_PHY_REG_CONTROL 0
44typedef union {
45 uint16_t u16;
46 struct {
47 uint16_t reset:1;
48 uint16_t loopback:1;
49 uint16_t speed_lsb:1;
50 uint16_t autoneg_enable:1;
51 uint16_t power_down:1;
52 uint16_t isolate:1;
53 uint16_t restart_autoneg:1;
54 uint16_t duplex:1;
55 uint16_t collision_test:1;
56 uint16_t speed_msb:1;
57 uint16_t unidirectional_enable:1;
58 uint16_t reserved_0_4:5;
59 } s;
60} cvmx_mdio_phy_reg_control_t;
61
62/**
63 * PHY register 1 from the 802.3 spec
64 */
65#define CVMX_MDIO_PHY_REG_STATUS 1
66typedef union {
67 uint16_t u16;
68 struct {
69 uint16_t capable_100base_t4:1;
70 uint16_t capable_100base_x_full:1;
71 uint16_t capable_100base_x_half:1;
72 uint16_t capable_10_full:1;
73 uint16_t capable_10_half:1;
74 uint16_t capable_100base_t2_full:1;
75 uint16_t capable_100base_t2_half:1;
76 uint16_t capable_extended_status:1;
77 uint16_t capable_unidirectional:1;
78 uint16_t capable_mf_preamble_suppression:1;
79 uint16_t autoneg_complete:1;
80 uint16_t remote_fault:1;
81 uint16_t capable_autoneg:1;
82 uint16_t link_status:1;
83 uint16_t jabber_detect:1;
84 uint16_t capable_extended_registers:1;
85
86 } s;
87} cvmx_mdio_phy_reg_status_t;
88
89/**
90 * PHY register 2 from the 802.3 spec
91 */
92#define CVMX_MDIO_PHY_REG_ID1 2
93typedef union {
94 uint16_t u16;
95 struct {
96 uint16_t oui_bits_3_18;
97 } s;
98} cvmx_mdio_phy_reg_id1_t;
99
100/**
101 * PHY register 3 from the 802.3 spec
102 */
103#define CVMX_MDIO_PHY_REG_ID2 3
104typedef union {
105 uint16_t u16;
106 struct {
107 uint16_t oui_bits_19_24:6;
108 uint16_t model:6;
109 uint16_t revision:4;
110 } s;
111} cvmx_mdio_phy_reg_id2_t;
112
113/**
114 * PHY register 4 from the 802.3 spec
115 */
116#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
117typedef union {
118 uint16_t u16;
119 struct {
120 uint16_t next_page:1;
121 uint16_t reserved_14:1;
122 uint16_t remote_fault:1;
123 uint16_t reserved_12:1;
124 uint16_t asymmetric_pause:1;
125 uint16_t pause:1;
126 uint16_t advert_100base_t4:1;
127 uint16_t advert_100base_tx_full:1;
128 uint16_t advert_100base_tx_half:1;
129 uint16_t advert_10base_tx_full:1;
130 uint16_t advert_10base_tx_half:1;
131 uint16_t selector:5;
132 } s;
133} cvmx_mdio_phy_reg_autoneg_adver_t;
134
135/**
136 * PHY register 5 from the 802.3 spec
137 */
138#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
139typedef union {
140 uint16_t u16;
141 struct {
142 uint16_t next_page:1;
143 uint16_t ack:1;
144 uint16_t remote_fault:1;
145 uint16_t reserved_12:1;
146 uint16_t asymmetric_pause:1;
147 uint16_t pause:1;
148 uint16_t advert_100base_t4:1;
149 uint16_t advert_100base_tx_full:1;
150 uint16_t advert_100base_tx_half:1;
151 uint16_t advert_10base_tx_full:1;
152 uint16_t advert_10base_tx_half:1;
153 uint16_t selector:5;
154 } s;
155} cvmx_mdio_phy_reg_link_partner_ability_t;
156
157/**
158 * PHY register 6 from the 802.3 spec
159 */
160#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
161typedef union {
162 uint16_t u16;
163 struct {
164 uint16_t reserved_5_15:11;
165 uint16_t parallel_detection_fault:1;
166 uint16_t link_partner_next_page_capable:1;
167 uint16_t local_next_page_capable:1;
168 uint16_t page_received:1;
169 uint16_t link_partner_autoneg_capable:1;
170
171 } s;
172} cvmx_mdio_phy_reg_autoneg_expansion_t;
173
174/**
175 * PHY register 9 from the 802.3 spec
176 */
177#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
178typedef union {
179 uint16_t u16;
180 struct {
181 uint16_t test_mode:3;
182 uint16_t manual_master_slave:1;
183 uint16_t master:1;
184 uint16_t port_type:1;
185 uint16_t advert_1000base_t_full:1;
186 uint16_t advert_1000base_t_half:1;
187 uint16_t reserved_0_7:8;
188 } s;
189} cvmx_mdio_phy_reg_control_1000_t;
190
191/**
192 * PHY register 10 from the 802.3 spec
193 */
194#define CVMX_MDIO_PHY_REG_STATUS_1000 10
195typedef union {
196 uint16_t u16;
197 struct {
198 uint16_t master_slave_fault:1;
199 uint16_t is_master:1;
200 uint16_t local_receiver_ok:1;
201 uint16_t remote_receiver_ok:1;
202 uint16_t remote_capable_1000base_t_full:1;
203 uint16_t remote_capable_1000base_t_half:1;
204 uint16_t reserved_8_9:2;
205 uint16_t idle_error_count:8;
206 } s;
207} cvmx_mdio_phy_reg_status_1000_t;
208
209/**
210 * PHY register 15 from the 802.3 spec
211 */
212#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
213typedef union {
214 uint16_t u16;
215 struct {
216 uint16_t capable_1000base_x_full:1;
217 uint16_t capable_1000base_x_half:1;
218 uint16_t capable_1000base_t_full:1;
219 uint16_t capable_1000base_t_half:1;
220 uint16_t reserved_0_11:12;
221 } s;
222} cvmx_mdio_phy_reg_extended_status_t;
223
224/**
225 * PHY register 13 from the 802.3 spec
226 */
227#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
228typedef union {
229 uint16_t u16;
230 struct {
231 uint16_t function:2;
232 uint16_t reserved_5_13:9;
233 uint16_t devad:5;
234 } s;
235} cvmx_mdio_phy_reg_mmd_control_t;
236
237/**
238 * PHY register 14 from the 802.3 spec
239 */
240#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
241typedef union {
242 uint16_t u16;
243 struct {
244 uint16_t address_data:16;
245 } s;
246} cvmx_mdio_phy_reg_mmd_address_data_t;
247
248/* Operating request encodings. */
249#define MDIO_CLAUSE_22_WRITE 0
250#define MDIO_CLAUSE_22_READ 1
251
252#define MDIO_CLAUSE_45_ADDRESS 0
253#define MDIO_CLAUSE_45_WRITE 1
254#define MDIO_CLAUSE_45_READ_INC 2
255#define MDIO_CLAUSE_45_READ 3
256
257/* MMD identifiers, mostly for accessing devices within XENPAK modules. */
258#define CVMX_MMD_DEVICE_PMA_PMD 1
259#define CVMX_MMD_DEVICE_WIS 2
260#define CVMX_MMD_DEVICE_PCS 3
261#define CVMX_MMD_DEVICE_PHY_XS 4
262#define CVMX_MMD_DEVICE_DTS_XS 5
263#define CVMX_MMD_DEVICE_TC 6
264#define CVMX_MMD_DEVICE_CL22_EXT 29
265#define CVMX_MMD_DEVICE_VENDOR_1 30
266#define CVMX_MMD_DEVICE_VENDOR_2 31
267
268/* Helper function to put MDIO interface into clause 45 mode */
269static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
270{
271 union cvmx_smix_clk smi_clk;
272 /* Put bus into clause 45 mode */
273 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
274 smi_clk.s.mode = 1;
275 smi_clk.s.preamble = 1;
276 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
277}
278
279/* Helper function to put MDIO interface into clause 22 mode */
280static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
281{
282 union cvmx_smix_clk smi_clk;
283 /* Put bus into clause 22 mode */
284 smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
285 smi_clk.s.mode = 0;
286 cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
287}
288
289/**
290 * Perform an MII read. This function is used to read PHY
291 * registers controlling auto negotiation.
292 *
293 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
294 * support multiple busses.
295 * @phy_id: The MII phy id
296 * @location: Register location to read
297 *
298 * Returns Result from the read or -1 on failure
299 */
300static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
301{
302 union cvmx_smix_cmd smi_cmd;
303 union cvmx_smix_rd_dat smi_rd;
304 int timeout = 1000;
305
306 if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
307 __cvmx_mdio_set_clause22_mode(bus_id);
308
309 smi_cmd.u64 = 0;
310 smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
311 smi_cmd.s.phy_adr = phy_id;
312 smi_cmd.s.reg_adr = location;
313 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
314
315 do {
316 cvmx_wait(1000);
317 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
318 } while (smi_rd.s.pending && timeout--);
319
320 if (smi_rd.s.val)
321 return smi_rd.s.dat;
322 else
323 return -1;
324}
325
326/**
327 * Perform an MII write. This function is used to write PHY
328 * registers controlling auto negotiation.
329 *
330 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
331 * support multiple busses.
332 * @phy_id: The MII phy id
333 * @location: Register location to write
334 * @val: Value to write
335 *
336 * Returns -1 on error
337 * 0 on success
338 */
339static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
340{
341 union cvmx_smix_cmd smi_cmd;
342 union cvmx_smix_wr_dat smi_wr;
343 int timeout = 1000;
344
345 if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
346 __cvmx_mdio_set_clause22_mode(bus_id);
347
348 smi_wr.u64 = 0;
349 smi_wr.s.dat = val;
350 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
351
352 smi_cmd.u64 = 0;
353 smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
354 smi_cmd.s.phy_adr = phy_id;
355 smi_cmd.s.reg_adr = location;
356 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
357
358 do {
359 cvmx_wait(1000);
360 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
361 } while (smi_wr.s.pending && --timeout);
362 if (timeout <= 0)
363 return -1;
364
365 return 0;
366}
367
368/**
369 * Perform an IEEE 802.3 clause 45 MII read. This function is used to
370 * read PHY registers controlling auto negotiation.
371 *
372 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
373 * support multiple busses.
374 * @phy_id: The MII phy id
375 * @device: MDIO Managable Device (MMD) id
376 * @location: Register location to read
377 *
378 * Returns Result from the read or -1 on failure
379 */
380
381static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
382 int location)
383{
384 union cvmx_smix_cmd smi_cmd;
385 union cvmx_smix_rd_dat smi_rd;
386 union cvmx_smix_wr_dat smi_wr;
387 int timeout = 1000;
388
389 if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
390 return -1;
391
392 __cvmx_mdio_set_clause45_mode(bus_id);
393
394 smi_wr.u64 = 0;
395 smi_wr.s.dat = location;
396 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
397
398 smi_cmd.u64 = 0;
399 smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
400 smi_cmd.s.phy_adr = phy_id;
401 smi_cmd.s.reg_adr = device;
402 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
403
404 do {
405 cvmx_wait(1000);
406 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
407 } while (smi_wr.s.pending && --timeout);
408 if (timeout <= 0) {
409 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
410 "device %2d register %2d TIME OUT(address)\n",
411 bus_id, phy_id, device, location);
412 return -1;
413 }
414
415 smi_cmd.u64 = 0;
416 smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
417 smi_cmd.s.phy_adr = phy_id;
418 smi_cmd.s.reg_adr = device;
419 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
420
421 do {
422 cvmx_wait(1000);
423 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
424 } while (smi_rd.s.pending && --timeout);
425
426 if (timeout <= 0) {
427 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
428 "device %2d register %2d TIME OUT(data)\n",
429 bus_id, phy_id, device, location);
430 return -1;
431 }
432
433 if (smi_rd.s.val)
434 return smi_rd.s.dat;
435 else {
436 cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
437 "device %2d register %2d INVALID READ\n",
438 bus_id, phy_id, device, location);
439 return -1;
440 }
441}
442
443/**
444 * Perform an IEEE 802.3 clause 45 MII write. This function is used to
445 * write PHY registers controlling auto negotiation.
446 *
447 * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
448 * support multiple busses.
449 * @phy_id: The MII phy id
450 * @device: MDIO Managable Device (MMD) id
451 * @location: Register location to write
452 * @val: Value to write
453 *
454 * Returns -1 on error
455 * 0 on success
456 */
457static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
458 int location, int val)
459{
460 union cvmx_smix_cmd smi_cmd;
461 union cvmx_smix_wr_dat smi_wr;
462 int timeout = 1000;
463
464 if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
465 return -1;
466
467 __cvmx_mdio_set_clause45_mode(bus_id);
468
469 smi_wr.u64 = 0;
470 smi_wr.s.dat = location;
471 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
472
473 smi_cmd.u64 = 0;
474 smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
475 smi_cmd.s.phy_adr = phy_id;
476 smi_cmd.s.reg_adr = device;
477 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
478
479 do {
480 cvmx_wait(1000);
481 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
482 } while (smi_wr.s.pending && --timeout);
483 if (timeout <= 0)
484 return -1;
485
486 smi_wr.u64 = 0;
487 smi_wr.s.dat = val;
488 cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
489
490 smi_cmd.u64 = 0;
491 smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
492 smi_cmd.s.phy_adr = phy_id;
493 smi_cmd.s.reg_adr = device;
494 cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
495
496 do {
497 cvmx_wait(1000);
498 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
499 } while (smi_wr.s.pending && --timeout);
500 if (timeout <= 0)
501 return -1;
502
503 return 0;
504}
505
506#endif
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 9b63cd41213d..30d1129d8624 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -17,15 +17,18 @@
17 */ 17 */
18 18
19#include <linux/ioport.h> 19#include <linux/ioport.h>
20#include <linux/list.h>
20#include <linux/of.h> 21#include <linux/of.h>
21 22
23#ifdef CONFIG_PCI_DRIVERS_LEGACY
24
22/* 25/*
23 * Each pci channel is a top-level PCI bus seem by CPU. A machine with 26 * Each pci channel is a top-level PCI bus seem by CPU. A machine with
24 * multiple PCI channels may have multiple PCI host controllers or a 27 * multiple PCI channels may have multiple PCI host controllers or a
25 * single controller supporting multiple channels. 28 * single controller supporting multiple channels.
26 */ 29 */
27struct pci_controller { 30struct pci_controller {
28 struct pci_controller *next; 31 struct list_head list;
29 struct pci_bus *bus; 32 struct pci_bus *bus;
30 struct device_node *of_node; 33 struct device_node *of_node;
31 34
@@ -38,10 +41,12 @@ struct pci_controller {
38 struct resource *busn_resource; 41 struct resource *busn_resource;
39 unsigned long busn_offset; 42 unsigned long busn_offset;
40 43
44#ifndef CONFIG_PCI_DOMAINS_GENERIC
41 unsigned int index; 45 unsigned int index;
42 /* For compatibility with current (as of July 2003) pciutils 46 /* For compatibility with current (as of July 2003) pciutils
43 and XFree86. Eventually will be removed. */ 47 and XFree86. Eventually will be removed. */
44 unsigned int need_domain_info; 48 unsigned int need_domain_info;
49#endif
45 50
46 /* Optional access methods for reading/writing the bus number 51 /* Optional access methods for reading/writing the bus number
47 of the PCI controller */ 52 of the PCI controller */
@@ -59,12 +64,43 @@ extern void register_pci_controller(struct pci_controller *hose);
59 */ 64 */
60extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); 65extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
61 66
67/* Do platform specific device initialization at pci_enable_device() time */
68extern int pcibios_plat_dev_init(struct pci_dev *dev);
69
70extern char * (*pcibios_plat_setup)(char *str);
71
72#ifdef CONFIG_OF
73/* this function parses memory ranges from a device node */
74extern void pci_load_of_ranges(struct pci_controller *hose,
75 struct device_node *node);
76#else
77static inline void pci_load_of_ranges(struct pci_controller *hose,
78 struct device_node *node) {}
79#endif
80
81#ifdef CONFIG_PCI_DOMAINS_GENERIC
82static inline void set_pci_need_domain_info(struct pci_controller *hose,
83 int need_domain_info)
84{
85 /* nothing to do */
86}
87#elif defined(CONFIG_PCI_DOMAINS)
88static inline void set_pci_need_domain_info(struct pci_controller *hose,
89 int need_domain_info)
90{
91 hose->need_domain_info = need_domain_info;
92}
93#endif /* CONFIG_PCI_DOMAINS */
94
95#endif
62 96
63/* Can be used to override the logic in pci_scan_bus for skipping 97/* Can be used to override the logic in pci_scan_bus for skipping
64 already-configured bus numbers - to be used for buggy BIOSes 98 already-configured bus numbers - to be used for buggy BIOSes
65 or architectures with incomplete PCI setup by the loader */ 99 or architectures with incomplete PCI setup by the loader */
66 100static inline unsigned int pcibios_assign_all_busses(void)
67extern unsigned int pcibios_assign_all_busses(void); 101{
102 return 1;
103}
68 104
69extern unsigned long PCIBIOS_MIN_IO; 105extern unsigned long PCIBIOS_MIN_IO;
70extern unsigned long PCIBIOS_MIN_MEM; 106extern unsigned long PCIBIOS_MIN_MEM;
@@ -100,7 +136,12 @@ struct pci_dev;
100 */ 136 */
101#define PCI_DMA_BUS_IS_PHYS (1) 137#define PCI_DMA_BUS_IS_PHYS (1)
102 138
103#ifdef CONFIG_PCI_DOMAINS 139#ifdef CONFIG_PCI_DOMAINS_GENERIC
140static inline int pci_proc_domain(struct pci_bus *bus)
141{
142 return pci_domain_nr(bus);
143}
144#elif defined(CONFIG_PCI_DOMAINS)
104#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index 145#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
105 146
106static inline int pci_proc_domain(struct pci_bus *bus) 147static inline int pci_proc_domain(struct pci_bus *bus)
@@ -121,15 +162,4 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
121 return channel ? 15 : 14; 162 return channel ? 15 : 14;
122} 163}
123 164
124extern char * (*pcibios_plat_setup)(char *str);
125
126#ifdef CONFIG_OF
127/* this function parses memory ranges from a device node */
128extern void pci_load_of_ranges(struct pci_controller *hose,
129 struct device_node *node);
130#else
131static inline void pci_load_of_ranges(struct pci_controller *hose,
132 struct device_node *node) {}
133#endif
134
135#endif /* _ASM_PCI_H */ 165#endif /* _ASM_PCI_H */
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 93c079a1cfc8..a03e86969f78 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -67,11 +67,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
67static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 67static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
68 unsigned long address) 68 unsigned long address)
69{ 69{
70 pte_t *pte; 70 return (pte_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, PTE_ORDER);
71
72 pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_ZERO, PTE_ORDER);
73
74 return pte;
75} 71}
76 72
77static inline struct page *pte_alloc_one(struct mm_struct *mm, 73static inline struct page *pte_alloc_one(struct mm_struct *mm,
diff --git a/arch/mips/include/asm/pm-cps.h b/arch/mips/include/asm/pm-cps.h
index 625eda53d571..89d58d80b77b 100644
--- a/arch/mips/include/asm/pm-cps.h
+++ b/arch/mips/include/asm/pm-cps.h
@@ -13,10 +13,12 @@
13 13
14/* 14/*
15 * The CM & CPC can only handle coherence & power control on a per-core basis, 15 * The CM & CPC can only handle coherence & power control on a per-core basis,
16 * thus in an MT system the VPEs within each core are coupled and can only 16 * thus in an MT system the VP(E)s within each core are coupled and can only
17 * enter or exit states requiring CM or CPC assistance in unison. 17 * enter or exit states requiring CM or CPC assistance in unison.
18 */ 18 */
19#ifdef CONFIG_MIPS_MT 19#if defined(CONFIG_CPU_MIPSR6)
20# define coupled_coherence cpu_has_vp
21#elif defined(CONFIG_MIPS_MT)
20# define coupled_coherence cpu_has_mipsmt 22# define coupled_coherence cpu_has_mipsmt
21#else 23#else
22# define coupled_coherence 0 24# define coupled_coherence 0
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index f6fc6aac5496..b6578611dddb 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -152,7 +152,7 @@ static inline int is_syscall_success(struct pt_regs *regs)
152 152
153static inline long regs_return_value(struct pt_regs *regs) 153static inline long regs_return_value(struct pt_regs *regs)
154{ 154{
155 if (is_syscall_success(regs)) 155 if (is_syscall_success(regs) || !user_mode(regs))
156 return regs->regs[2]; 156 return regs->regs[2];
157 else 157 else
158 return -regs->regs[2]; 158 return -regs->regs[2];
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 8bc6c70a4030..060f23ff1817 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -85,6 +85,20 @@ static inline void __cpu_die(unsigned int cpu)
85extern void play_dead(void); 85extern void play_dead(void);
86#endif 86#endif
87 87
88/*
89 * This function will set up the necessary IPIs for Linux to communicate
90 * with the CPUs in mask.
91 * Return 0 on success.
92 */
93int mips_smp_ipi_allocate(const struct cpumask *mask);
94
95/*
96 * This function will free up IPIs allocated with mips_smp_ipi_allocate to the
97 * CPUs in mask, which must be a subset of the IPIs that have been configured.
98 * Return 0 on success.
99 */
100int mips_smp_ipi_free(const struct cpumask *mask);
101
88static inline void arch_send_call_function_single_ipi(int cpu) 102static inline void arch_send_call_function_single_ipi(int cpu)
89{ 103{
90 extern struct plat_smp_ops *mp_ops; /* private */ 104 extern struct plat_smp_ops *mp_ops; /* private */
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 4daf839cd8a8..89fa5c0b1579 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -859,7 +859,10 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
859 __cu_to = (to); \ 859 __cu_to = (to); \
860 __cu_from = (from); \ 860 __cu_from = (from); \
861 __cu_len = (n); \ 861 __cu_len = (n); \
862 \
863 check_object_size(__cu_from, __cu_len, true); \
862 might_fault(); \ 864 might_fault(); \
865 \
863 if (eva_kernel_access()) \ 866 if (eva_kernel_access()) \
864 __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from, \ 867 __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from, \
865 __cu_len); \ 868 __cu_len); \
@@ -880,6 +883,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
880 __cu_to = (to); \ 883 __cu_to = (to); \
881 __cu_from = (from); \ 884 __cu_from = (from); \
882 __cu_len = (n); \ 885 __cu_len = (n); \
886 \
887 check_object_size(__cu_from, __cu_len, true); \
888 \
883 if (eva_kernel_access()) \ 889 if (eva_kernel_access()) \
884 __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from, \ 890 __cu_len = __invoke_copy_to_kernel(__cu_to, __cu_from, \
885 __cu_len); \ 891 __cu_len); \
@@ -898,6 +904,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
898 __cu_to = (to); \ 904 __cu_to = (to); \
899 __cu_from = (from); \ 905 __cu_from = (from); \
900 __cu_len = (n); \ 906 __cu_len = (n); \
907 \
908 check_object_size(__cu_to, __cu_len, false); \
909 \
901 if (eva_kernel_access()) \ 910 if (eva_kernel_access()) \
902 __cu_len = __invoke_copy_from_kernel_inatomic(__cu_to, \ 911 __cu_len = __invoke_copy_from_kernel_inatomic(__cu_to, \
903 __cu_from,\ 912 __cu_from,\
@@ -932,6 +941,9 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
932 __cu_to = (to); \ 941 __cu_to = (to); \
933 __cu_from = (from); \ 942 __cu_from = (from); \
934 __cu_len = (n); \ 943 __cu_len = (n); \
944 \
945 check_object_size(__cu_from, __cu_len, true); \
946 \
935 if (eva_kernel_access()) { \ 947 if (eva_kernel_access()) { \
936 __cu_len = __invoke_copy_to_kernel(__cu_to, \ 948 __cu_len = __invoke_copy_to_kernel(__cu_to, \
937 __cu_from, \ 949 __cu_from, \
@@ -1124,6 +1136,9 @@ extern size_t __copy_in_user_eva(void *__to, const void *__from, size_t __n);
1124 __cu_to = (to); \ 1136 __cu_to = (to); \
1125 __cu_from = (from); \ 1137 __cu_from = (from); \
1126 __cu_len = (n); \ 1138 __cu_len = (n); \
1139 \
1140 check_object_size(__cu_to, __cu_len, false); \
1141 \
1127 if (eva_kernel_access()) { \ 1142 if (eva_kernel_access()) { \
1128 __cu_len = __invoke_copy_from_kernel(__cu_to, \ 1143 __cu_len = __invoke_copy_from_kernel(__cu_to, \
1129 __cu_from, \ 1144 __cu_from, \
@@ -1162,6 +1177,9 @@ extern size_t __copy_in_user_eva(void *__to, const void *__from, size_t __n);
1162 __cu_to = (to); \ 1177 __cu_to = (to); \
1163 __cu_from = (from); \ 1178 __cu_from = (from); \
1164 __cu_len = (n); \ 1179 __cu_len = (n); \
1180 \
1181 check_object_size(__cu_to, __cu_len, false); \
1182 \
1165 if (eva_kernel_access()) { \ 1183 if (eva_kernel_access()) { \
1166 __cu_len = __invoke_copy_from_kernel(__cu_to, \ 1184 __cu_len = __invoke_copy_from_kernel(__cu_to, \
1167 __cu_from, \ 1185 __cu_from, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 08:45:01 -0500