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-rw-r--r--arch/mips/include/asm/compat.h7
-rw-r--r--arch/mips/include/asm/cpu.h3
-rw-r--r--arch/mips/include/asm/ftrace.h1
-rw-r--r--arch/mips/include/asm/hazards.h5
-rw-r--r--arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h49
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h70
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/gpio.h20
-rw-r--r--arch/mips/include/asm/mach-ip27/topology.h1
-rw-r--r--arch/mips/include/asm/mips-boards/generic.h2
-rw-r--r--arch/mips/include/asm/mipsregs.h22
-rw-r--r--arch/mips/include/asm/prefetch.h2
-rw-r--r--arch/mips/include/asm/seccomp.h4
-rw-r--r--arch/mips/include/asm/smp-ops.h2
-rw-r--r--arch/mips/include/asm/socket.h3
-rw-r--r--arch/mips/include/asm/spinlock.h10
-rw-r--r--arch/mips/include/asm/thread_info.h6
-rw-r--r--arch/mips/include/asm/types.h8
-rw-r--r--arch/mips/include/asm/unistd.h18
18 files changed, 138 insertions, 95 deletions
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index ac5d541368e9..6c5b40905dd6 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -3,6 +3,8 @@
3/* 3/*
4 * Architecture specific compatibility types 4 * Architecture specific compatibility types
5 */ 5 */
6#include <linux/seccomp.h>
7#include <linux/thread_info.h>
6#include <linux/types.h> 8#include <linux/types.h>
7#include <asm/page.h> 9#include <asm/page.h>
8#include <asm/ptrace.h> 10#include <asm/ptrace.h>
@@ -218,4 +220,9 @@ struct compat_shmid64_ds {
218 compat_ulong_t __unused2; 220 compat_ulong_t __unused2;
219}; 221};
220 222
223static inline int is_compat_task(void)
224{
225 return test_thread_flag(TIF_32BIT);
226}
227
221#endif /* _ASM_COMPAT_H */ 228#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index c018727c7ddc..3bdc0e3d89cc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -209,8 +209,7 @@ enum cpu_type_enum {
209 * MIPS32 class processors 209 * MIPS32 class processors
210 */ 210 */
211 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 211 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
212 CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, 212 CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
213 CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
214 213
215 /* 214 /*
216 * MIPS64 class processors 215 * MIPS64 class processors
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/mips/include/asm/ftrace.h
@@ -0,0 +1 @@
/* empty */
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 43baed16a109..a12d971db4f9 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do { \
87 : "=r" (tmp)); \ 87 : "=r" (tmp)); \
88} while (0) 88} while (0)
89 89
90#elif defined(CONFIG_CPU_MIPSR1) 90#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
91 91
92/* 92/*
93 * These are slightly complicated by the fact that we guarantee R1 kernels to 93 * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,8 @@ do { \
138 __instruction_hazard(); \ 138 __instruction_hazard(); \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) 141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
142 defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
142 143
143/* 144/*
144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 145 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
new file mode 100644
index 000000000000..d5df0cab9b87
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -0,0 +1,49 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6
7#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
8#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
9
10#define cpu_has_tlb 1
11#define cpu_has_4kex 1
12#define cpu_has_3k_cache 0
13#define cpu_has_4k_cache 1
14#define cpu_has_tx39_cache 0
15#define cpu_has_fpu 0
16#define cpu_has_counter 1
17#define cpu_has_watch 1
18#define cpu_has_divec 1
19#define cpu_has_vce 0
20#define cpu_has_cache_cdex_p 0
21#define cpu_has_cache_cdex_s 0
22#define cpu_has_mcheck 1
23#define cpu_has_ejtag 1
24#define cpu_has_llsc 1
25#define cpu_has_mips16 0
26#define cpu_has_mdmx 0
27#define cpu_has_mips3d 0
28#define cpu_has_smartmips 0
29#define cpu_has_vtag_icache 0
30#define cpu_has_dc_aliases 0
31#define cpu_has_ic_fills_f_dc 1
32#define cpu_has_mips32r1 1
33#define cpu_has_mips32r2 0
34#define cpu_has_mips64r1 0
35#define cpu_has_mips64r2 0
36#define cpu_has_dsp 0
37#define cpu_has_mipsmt 0
38#define cpu_has_userlocal 0
39#define cpu_has_nofpuex 0
40#define cpu_has_64bits 0
41#define cpu_has_64bit_zero_reg 0
42#define cpu_has_vint 0
43#define cpu_has_veic 0
44#define cpu_has_inclusive_pcaches 0
45
46#define cpu_dcache_line_size() 32
47#define cpu_icache_line_size() 32
48
49#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 2dc61e009a08..34d9b7279024 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -5,65 +5,29 @@
5 5
6#define AU1XXX_GPIO_BASE 200 6#define AU1XXX_GPIO_BASE 200
7 7
8struct au1x00_gpio2 { 8/* GPIO bank 1 offsets */
9 u32 dir; 9#define AU1000_GPIO1_TRI_OUT 0x0100
10 u32 reserved; 10#define AU1000_GPIO1_OUT 0x0108
11 u32 output; 11#define AU1000_GPIO1_ST 0x0110
12 u32 pinstate; 12#define AU1000_GPIO1_CLR 0x010C
13 u32 inten;
14 u32 enable;
15};
16 13
17extern int au1xxx_gpio_get_value(unsigned gpio); 14/* GPIO bank 2 offsets */
18extern void au1xxx_gpio_set_value(unsigned gpio, int value); 15#define AU1000_GPIO2_DIR 0x00
19extern int au1xxx_gpio_direction_input(unsigned gpio); 16#define AU1000_GPIO2_RSVD 0x04
20extern int au1xxx_gpio_direction_output(unsigned gpio, int value); 17#define AU1000_GPIO2_OUT 0x08
18#define AU1000_GPIO2_ST 0x0C
19#define AU1000_GPIO2_INT 0x10
20#define AU1000_GPIO2_EN 0x14
21 21
22#define GPIO2_OUT_EN_MASK 0x00010000
22 23
23/* Wrappers for the arch-neutral GPIO API */ 24#define gpio_to_irq(gpio) NULL
24 25
25static inline int gpio_request(unsigned gpio, const char *label) 26#define gpio_get_value __gpio_get_value
26{ 27#define gpio_set_value __gpio_set_value
27 /* Not yet implemented */
28 return 0;
29}
30 28
31static inline void gpio_free(unsigned gpio) 29#define gpio_cansleep __gpio_cansleep
32{
33 /* Not yet implemented */
34}
35 30
36static inline int gpio_direction_input(unsigned gpio)
37{
38 return au1xxx_gpio_direction_input(gpio);
39}
40
41static inline int gpio_direction_output(unsigned gpio, int value)
42{
43 return au1xxx_gpio_direction_output(gpio, value);
44}
45
46static inline int gpio_get_value(unsigned gpio)
47{
48 return au1xxx_gpio_get_value(gpio);
49}
50
51static inline void gpio_set_value(unsigned gpio, int value)
52{
53 au1xxx_gpio_set_value(gpio, value);
54}
55
56static inline int gpio_to_irq(unsigned gpio)
57{
58 return gpio;
59}
60
61static inline int irq_to_gpio(unsigned irq)
62{
63 return irq;
64}
65
66/* For cansleep */
67#include <asm-generic/gpio.h> 31#include <asm-generic/gpio.h>
68 32
69#endif /* _AU1XXX_GPIO_H_ */ 33#endif /* _AU1XXX_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index d8ff4cd89ab5..1784fde2e28f 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -31,24 +31,28 @@ static inline void gpio_set_value(unsigned gpio, int value)
31 31
32static inline int gpio_direction_input(unsigned gpio) 32static inline int gpio_direction_input(unsigned gpio)
33{ 33{
34 return ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0); 34 ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0);
35 return 0;
35} 36}
36 37
37static inline int gpio_direction_output(unsigned gpio, int value) 38static inline int gpio_direction_output(unsigned gpio, int value)
38{ 39{
39 return ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio); 40 ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
41 return 0;
40} 42}
41 43
42static int gpio_intmask(unsigned gpio, int value) 44static inline int gpio_intmask(unsigned gpio, int value)
43{ 45{
44 return ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio, 46 ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio,
45 value ? 1 << gpio : 0); 47 value ? 1 << gpio : 0);
48 return 0;
46} 49}
47 50
48static int gpio_polarity(unsigned gpio, int value) 51static inline int gpio_polarity(unsigned gpio, int value)
49{ 52{
50 return ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio, 53 ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio,
51 value ? 1 << gpio : 0); 54 value ? 1 << gpio : 0);
55 return 0;
52} 56}
53 57
54 58
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 55d481569a1f..07547231e078 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -26,7 +26,6 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
26#define parent_node(node) (node) 26#define parent_node(node) (node)
27#define node_to_cpumask(node) (hub_data(node)->h_cpus) 27#define node_to_cpumask(node) (hub_data(node)->h_cpus)
28#define cpumask_of_node(node) (&hub_data(node)->h_cpus) 28#define cpumask_of_node(node) (&hub_data(node)->h_cpus)
29#define node_to_first_cpu(node) (cpumask_first(cpumask_of_node(node)))
30struct pci_bus; 29struct pci_bus;
31extern int pcibus_to_node(struct pci_bus *); 30extern int pcibus_to_node(struct pci_bus *);
32 31
diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index 7f0b034dd9a5..c0da1a881e3d 100644
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -71,8 +71,6 @@
71 71
72#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 72#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
73 73
74extern int mips_revision_corid;
75
76#define MIPS_REVISION_SCON_OTHER 0 74#define MIPS_REVISION_SCON_OTHER 0
77#define MIPS_REVISION_SCON_SOCITSC 1 75#define MIPS_REVISION_SCON_SOCITSC 1
78#define MIPS_REVISION_SCON_SOCITSCP 2 76#define MIPS_REVISION_SCON_SOCITSCP 2
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0417516503f6..526f327475ce 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1391,11 +1391,11 @@ static inline void tlb_write_random(void)
1391static inline unsigned int \ 1391static inline unsigned int \
1392set_c0_##name(unsigned int set) \ 1392set_c0_##name(unsigned int set) \
1393{ \ 1393{ \
1394 unsigned int res; \ 1394 unsigned int res, new; \
1395 \ 1395 \
1396 res = read_c0_##name(); \ 1396 res = read_c0_##name(); \
1397 res |= set; \ 1397 new = res | set; \
1398 write_c0_##name(res); \ 1398 write_c0_##name(new); \
1399 \ 1399 \
1400 return res; \ 1400 return res; \
1401} \ 1401} \
@@ -1403,24 +1403,24 @@ set_c0_##name(unsigned int set) \
1403static inline unsigned int \ 1403static inline unsigned int \
1404clear_c0_##name(unsigned int clear) \ 1404clear_c0_##name(unsigned int clear) \
1405{ \ 1405{ \
1406 unsigned int res; \ 1406 unsigned int res, new; \
1407 \ 1407 \
1408 res = read_c0_##name(); \ 1408 res = read_c0_##name(); \
1409 res &= ~clear; \ 1409 new = res & ~clear; \
1410 write_c0_##name(res); \ 1410 write_c0_##name(new); \
1411 \ 1411 \
1412 return res; \ 1412 return res; \
1413} \ 1413} \
1414 \ 1414 \
1415static inline unsigned int \ 1415static inline unsigned int \
1416change_c0_##name(unsigned int change, unsigned int new) \ 1416change_c0_##name(unsigned int change, unsigned int val) \
1417{ \ 1417{ \
1418 unsigned int res; \ 1418 unsigned int res, new; \
1419 \ 1419 \
1420 res = read_c0_##name(); \ 1420 res = read_c0_##name(); \
1421 res &= ~change; \ 1421 new = res & ~change; \
1422 res |= (new & change); \ 1422 new |= (val & change); \
1423 write_c0_##name(res); \ 1423 write_c0_##name(new); \
1424 \ 1424 \
1425 return res; \ 1425 return res; \
1426} 1426}
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h
index 17850834ccb0..a56594f360ee 100644
--- a/arch/mips/include/asm/prefetch.h
+++ b/arch/mips/include/asm/prefetch.h
@@ -26,7 +26,7 @@
26 * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in 26 * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
27 * current versions due to erratum G105. 27 * current versions due to erratum G105.
28 * 28 *
29 * VR7701 only implements the Load prefetch. 29 * VR5500 (including VR5701 and VR7701) only implement load prefetch.
30 * 30 *
31 * Finally MIPS32 and MIPS64 implement all of the following hints. 31 * Finally MIPS32 and MIPS64 implement all of the following hints.
32 */ 32 */
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
index a6772e9507f5..ae6306ebdcad 100644
--- a/arch/mips/include/asm/seccomp.h
+++ b/arch/mips/include/asm/seccomp.h
@@ -15,8 +15,6 @@
15 */ 15 */
16#ifdef CONFIG_MIPS32_O32 16#ifdef CONFIG_MIPS32_O32
17 17
18#define TIF_32BIT TIF_32BIT_REGS
19
20#define __NR_seccomp_read_32 4003 18#define __NR_seccomp_read_32 4003
21#define __NR_seccomp_write_32 4004 19#define __NR_seccomp_write_32 4004
22#define __NR_seccomp_exit_32 4001 20#define __NR_seccomp_exit_32 4001
@@ -24,8 +22,6 @@
24 22
25#elif defined(CONFIG_MIPS32_N32) 23#elif defined(CONFIG_MIPS32_N32)
26 24
27#define TIF_32BIT _TIF_32BIT_ADDR
28
29#define __NR_seccomp_read_32 6000 25#define __NR_seccomp_read_32 6000
30#define __NR_seccomp_write_32 6001 26#define __NR_seccomp_write_32 6001
31#define __NR_seccomp_exit_32 6058 27#define __NR_seccomp_exit_32 6058
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 43c207e72a63..64ffc0290b84 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -15,6 +15,8 @@
15 15
16#include <linux/cpumask.h> 16#include <linux/cpumask.h>
17 17
18struct task_struct;
19
18struct plat_smp_ops { 20struct plat_smp_ops {
19 void (*send_ipi_single)(int cpu, unsigned int action); 21 void (*send_ipi_single)(int cpu, unsigned int action);
20 void (*send_ipi_mask)(cpumask_t mask, unsigned int action); 22 void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
index facc2d7a87ca..2abca1780169 100644
--- a/arch/mips/include/asm/socket.h
+++ b/arch/mips/include/asm/socket.h
@@ -75,6 +75,9 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */
75 75
76#define SO_MARK 36 76#define SO_MARK 36
77 77
78#define SO_TIMESTAMPING 37
79#define SCM_TIMESTAMPING SO_TIMESTAMPING
80
78#ifdef __KERNEL__ 81#ifdef __KERNEL__
79 82
80/** sock_type - Socket types 83/** sock_type - Socket types
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 0884947ebe27..5b60a09a0f08 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -76,7 +76,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
76 "2: \n" 76 "2: \n"
77 " .subsection 2 \n" 77 " .subsection 2 \n"
78 "4: andi %[ticket], %[ticket], 0x1fff \n" 78 "4: andi %[ticket], %[ticket], 0x1fff \n"
79 "5: sll %[ticket], 5 \n" 79 " sll %[ticket], 5 \n"
80 " \n" 80 " \n"
81 "6: bnez %[ticket], 6b \n" 81 "6: bnez %[ticket], 6b \n"
82 " subu %[ticket], 1 \n" 82 " subu %[ticket], 1 \n"
@@ -85,7 +85,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
85 " andi %[ticket], %[ticket], 0x1fff \n" 85 " andi %[ticket], %[ticket], 0x1fff \n"
86 " beq %[ticket], %[my_ticket], 2b \n" 86 " beq %[ticket], %[my_ticket], 2b \n"
87 " subu %[ticket], %[my_ticket], %[ticket] \n" 87 " subu %[ticket], %[my_ticket], %[ticket] \n"
88 " b 5b \n" 88 " b 4b \n"
89 " subu %[ticket], %[ticket], 1 \n" 89 " subu %[ticket], %[ticket], 1 \n"
90 " .previous \n" 90 " .previous \n"
91 " .set pop \n" 91 " .set pop \n"
@@ -113,7 +113,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
113 " ll %[ticket], %[ticket_ptr] \n" 113 " ll %[ticket], %[ticket_ptr] \n"
114 " \n" 114 " \n"
115 "4: andi %[ticket], %[ticket], 0x1fff \n" 115 "4: andi %[ticket], %[ticket], 0x1fff \n"
116 "5: sll %[ticket], 5 \n" 116 " sll %[ticket], 5 \n"
117 " \n" 117 " \n"
118 "6: bnez %[ticket], 6b \n" 118 "6: bnez %[ticket], 6b \n"
119 " subu %[ticket], 1 \n" 119 " subu %[ticket], 1 \n"
@@ -122,7 +122,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
122 " andi %[ticket], %[ticket], 0x1fff \n" 122 " andi %[ticket], %[ticket], 0x1fff \n"
123 " beq %[ticket], %[my_ticket], 2b \n" 123 " beq %[ticket], %[my_ticket], 2b \n"
124 " subu %[ticket], %[my_ticket], %[ticket] \n" 124 " subu %[ticket], %[my_ticket], %[ticket] \n"
125 " b 5b \n" 125 " b 4b \n"
126 " subu %[ticket], %[ticket], 1 \n" 126 " subu %[ticket], %[ticket], 1 \n"
127 " .previous \n" 127 " .previous \n"
128 " .set pop \n" 128 " .set pop \n"
@@ -480,6 +480,8 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
480 return ret; 480 return ret;
481} 481}
482 482
483#define __raw_read_lock_flags(lock, flags) __raw_read_lock(lock)
484#define __raw_write_lock_flags(lock, flags) __raw_write_lock(lock)
483 485
484#define _raw_spin_relax(lock) cpu_relax() 486#define _raw_spin_relax(lock) cpu_relax()
485#define _raw_read_relax(lock) cpu_relax() 487#define _raw_read_relax(lock) cpu_relax()
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 3f76de73c943..676aa2ae1913 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -127,6 +127,12 @@ register struct thread_info *__current_thread_info __asm__("$28");
127#define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 127#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
128#define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 128#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
129 129
130#ifdef CONFIG_MIPS32_O32
131#define TIF_32BIT TIF_32BIT_REGS
132#elif defined(CONFIG_MIPS32_N32)
133#define TIF_32BIT _TIF_32BIT_ADDR
134#endif /* CONFIG_MIPS32_O32 */
135
130#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 136#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
131#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 137#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
132#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 138#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index bcbb8d675af5..7956e69a3bd5 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -4,12 +4,18 @@
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle 6 * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
7 * Copyright (C) 2008 Wind River Systems,
8 * written by Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 Silicon Graphics, Inc.
8 */ 10 */
9#ifndef _ASM_TYPES_H 11#ifndef _ASM_TYPES_H
10#define _ASM_TYPES_H 12#define _ASM_TYPES_H
11 13
12#if _MIPS_SZLONG == 64 14/*
15 * We don't use int-l64.h for the kernel anymore but still use it for
16 * userspace to avoid code changes.
17 */
18#if (_MIPS_SZLONG == 64) && !defined(__KERNEL__)
13# include <asm-generic/int-l64.h> 19# include <asm-generic/int-l64.h>
14#else 20#else
15# include <asm-generic/int-ll64.h> 21# include <asm-generic/int-ll64.h>
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index a73e1531e151..40005010827c 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -350,16 +350,18 @@
350#define __NR_dup3 (__NR_Linux + 327) 350#define __NR_dup3 (__NR_Linux + 327)
351#define __NR_pipe2 (__NR_Linux + 328) 351#define __NR_pipe2 (__NR_Linux + 328)
352#define __NR_inotify_init1 (__NR_Linux + 329) 352#define __NR_inotify_init1 (__NR_Linux + 329)
353#define __NR_preadv (__NR_Linux + 330)
354#define __NR_pwritev (__NR_Linux + 331)
353 355
354/* 356/*
355 * Offset of the last Linux o32 flavoured syscall 357 * Offset of the last Linux o32 flavoured syscall
356 */ 358 */
357#define __NR_Linux_syscalls 329 359#define __NR_Linux_syscalls 331
358 360
359#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 361#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
360 362
361#define __NR_O32_Linux 4000 363#define __NR_O32_Linux 4000
362#define __NR_O32_Linux_syscalls 329 364#define __NR_O32_Linux_syscalls 331
363 365
364#if _MIPS_SIM == _MIPS_SIM_ABI64 366#if _MIPS_SIM == _MIPS_SIM_ABI64
365 367
@@ -656,16 +658,18 @@
656#define __NR_dup3 (__NR_Linux + 286) 658#define __NR_dup3 (__NR_Linux + 286)
657#define __NR_pipe2 (__NR_Linux + 287) 659#define __NR_pipe2 (__NR_Linux + 287)
658#define __NR_inotify_init1 (__NR_Linux + 288) 660#define __NR_inotify_init1 (__NR_Linux + 288)
661#define __NR_preadv (__NR_Linux + 289)
662#define __NR_pwritev (__NR_Linux + 290)
659 663
660/* 664/*
661 * Offset of the last Linux 64-bit flavoured syscall 665 * Offset of the last Linux 64-bit flavoured syscall
662 */ 666 */
663#define __NR_Linux_syscalls 288 667#define __NR_Linux_syscalls 290
664 668
665#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */ 669#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
666 670
667#define __NR_64_Linux 5000 671#define __NR_64_Linux 5000
668#define __NR_64_Linux_syscalls 288 672#define __NR_64_Linux_syscalls 290
669 673
670#if _MIPS_SIM == _MIPS_SIM_NABI32 674#if _MIPS_SIM == _MIPS_SIM_NABI32
671 675
@@ -966,16 +970,18 @@
966#define __NR_dup3 (__NR_Linux + 290) 970#define __NR_dup3 (__NR_Linux + 290)
967#define __NR_pipe2 (__NR_Linux + 291) 971#define __NR_pipe2 (__NR_Linux + 291)
968#define __NR_inotify_init1 (__NR_Linux + 292) 972#define __NR_inotify_init1 (__NR_Linux + 292)
973#define __NR_preadv (__NR_Linux + 293)
974#define __NR_pwritev (__NR_Linux + 294)
969 975
970/* 976/*
971 * Offset of the last N32 flavoured syscall 977 * Offset of the last N32 flavoured syscall
972 */ 978 */
973#define __NR_Linux_syscalls 292 979#define __NR_Linux_syscalls 294
974 980
975#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ 981#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
976 982
977#define __NR_N32_Linux 6000 983#define __NR_N32_Linux 6000
978#define __NR_N32_Linux_syscalls 292 984#define __NR_N32_Linux_syscalls 294
979 985
980#ifdef __KERNEL__ 986#ifdef __KERNEL__
981 987
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-27 07:38:00 -0400