23 files changed, 426 insertions, 121 deletions

diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
index 37f84078e78a..940760844e2f 100644
--- a/arch/mips/include/asm/abi.h
+++ b/arch/mips/include/asm/abi.h
@@ -11,19 +11,20 @@
 
 #include <asm/signal.h>
 #include <asm/siginfo.h>
+#include <asm/vdso.h>
 
 struct mips_abi {
         int (* const setup_frame)(void *sig_return, struct ksignal *ksig,
                                   struct pt_regs *regs, sigset_t *set);
-        const unsigned long     signal_return_offset;
         int (* const setup_rt_frame)(void *sig_return, struct ksignal *ksig,
                                      struct pt_regs *regs, sigset_t *set);
-        const unsigned long     rt_signal_return_offset;
         const unsigned long     restart;
 
         unsigned        off_sc_fpregs;
         unsigned        off_sc_fpc_csr;
         unsigned        off_sc_used_math;
+
+        struct mips_vdso_image *vdso;
 };
 
 #endif /* _ASM_ABI_H */
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index f82d3af07931..835b402e4574 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -507,7 +507,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
  * @u: ...unless v is equal to u.
  *
  * Atomically adds @a to @v, so long as it was not @u.
- * Returns the old value of @v.
+ * Returns true iff @v was not @u.
  */
 static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
 {
diff --git a/arch/mips/include/asm/bcache.h b/arch/mips/include/asm/bcache.h
index 8c34484cea82..a00857b135c3 100644
--- a/arch/mips/include/asm/bcache.h
+++ b/arch/mips/include/asm/bcache.h
@@ -9,6 +9,7 @@
 #ifndef _ASM_BCACHE_H
 #define _ASM_BCACHE_H
 
+#include <linux/types.h>
 
 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
    chipset implemented caches.  On machines with other CPUs the CPU does the
@@ -18,6 +19,9 @@ struct bcache_ops {
         void (*bc_disable)(void);
         void (*bc_wback_inv)(unsigned long page, unsigned long size);
         void (*bc_inv)(unsigned long page, unsigned long size);
+        void (*bc_prefetch_enable)(void);
+        void (*bc_prefetch_disable)(void);
+        bool (*bc_prefetch_is_enabled)(void);
 };
 
 extern void indy_sc_init(void);
@@ -46,6 +50,26 @@ static inline void bc_inv(unsigned long page, unsigned long size)
         bcops->bc_inv(page, size);
 }
 
+static inline void bc_prefetch_enable(void)
+{
+        if (bcops->bc_prefetch_enable)
+                bcops->bc_prefetch_enable();
+}
+
+static inline void bc_prefetch_disable(void)
+{
+        if (bcops->bc_prefetch_disable)
+                bcops->bc_prefetch_disable();
+}
+
+static inline bool bc_prefetch_is_enabled(void)
+{
+        if (bcops->bc_prefetch_is_enabled)
+                return bcops->bc_prefetch_is_enabled();
+
+        return false;
+}
+
 #else /* !defined(CONFIG_BOARD_SCACHE) */
 
 /* Not R4000 / R4400 / R4600 / R5000.  */
@@ -54,6 +78,9 @@ static inline void bc_inv(unsigned long page, unsigned long size)
 #define bc_disable() do { } while (0)
 #define bc_wback_inv(page, size) do { } while (0)
 #define bc_inv(page, size) do { } while (0)
+#define bc_prefetch_enable() do { } while (0)
+#define bc_prefetch_disable() do { } while (0)
+#define bc_prefetch_is_enabled() 0
 
 #endif /* !defined(CONFIG_BOARD_SCACHE) */
 
diff --git a/arch/mips/include/asm/cdmm.h b/arch/mips/include/asm/cdmm.h
index bece2064cc8c..c06dbf8ba937 100644
--- a/arch/mips/include/asm/cdmm.h
+++ b/arch/mips/include/asm/cdmm.h
@@ -84,6 +84,17 @@ void mips_cdmm_driver_unregister(struct mips_cdmm_driver *);
         module_driver(__mips_cdmm_driver, mips_cdmm_driver_register, \
                         mips_cdmm_driver_unregister)
 
+/*
+ * builtin_mips_cdmm_driver() - Helper macro for drivers that don't do anything
+ * special in init and have no exit. This eliminates some boilerplate. Each
+ * driver may only use this macro once, and calling it replaces device_initcall
+ * (or in some cases, the legacy __initcall). This is meant to be a direct
+ * parallel of module_mips_cdmm_driver() above but without the __exit stuff that
+ * is not used for builtin cases.
+ */
+#define builtin_mips_cdmm_driver(__mips_cdmm_driver) \
+        builtin_driver(__mips_cdmm_driver, mips_cdmm_driver_register)
+
 /* drivers/tty/mips_ejtag_fdc.c */
 
 #ifdef CONFIG_MIPS_EJTAG_FDC_EARLYCON
diff --git a/arch/mips/include/asm/clocksource.h b/arch/mips/include/asm/clocksource.h
new file mode 100644
index 000000000000..3deb1d0c1a94
--- /dev/null
+++ b/arch/mips/include/asm/clocksource.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_CLOCKSOURCE_H
+#define __ASM_CLOCKSOURCE_H
+
+#include <linux/types.h>
+
+/* VDSO clocksources. */
+#define VDSO_CLOCK_NONE         0       /* No suitable clocksource. */
+#define VDSO_CLOCK_R4K          1       /* Use the coprocessor 0 count. */
+#define VDSO_CLOCK_GIC          2       /* Use the GIC. */
+
+/**
+ * struct arch_clocksource_data - Architecture-specific clocksource information.
+ * @vdso_clock_mode: Method the VDSO should use to access the clocksource.
+ */
+struct arch_clocksource_data {
+        u8 vdso_clock_mode;
+};
+
+#endif /* __ASM_CLOCKSOURCE_H */
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index c4bd54a7f5ce..a9580097cba8 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -130,6 +130,8 @@ typedef union compat_sigval {
         compat_uptr_t   sival_ptr;
 } compat_sigval_t;
 
+/* Can't use the generic version because si_code and si_errno are swapped */
+
 #define SI_PAD_SIZE32   (128/sizeof(int) - 3)
 
 typedef struct compat_siginfo {
@@ -138,57 +140,61 @@ typedef struct compat_siginfo {
         int si_errno;
 
         union {
-                int _pad[SI_PAD_SIZE32];
+                int _pad[128 / sizeof(int) - 3];
 
                 /* kill() */
                 struct {
                         compat_pid_t _pid;      /* sender's pid */
-                        __compat_uid_t _uid;    /* sender's uid */
+                        __compat_uid32_t _uid;  /* sender's uid */
                 } _kill;
 
+                /* POSIX.1b timers */
+                struct {
+                        compat_timer_t _tid;    /* timer id */
+                        int _overrun;           /* overrun count */
+                        compat_sigval_t _sigval;        /* same as below */
+                } _timer;
+
+                /* POSIX.1b signals */
+                struct {
+                        compat_pid_t _pid;      /* sender's pid */
+                        __compat_uid32_t _uid;  /* sender's uid */
+                        compat_sigval_t _sigval;
+                } _rt;
+
                 /* SIGCHLD */
                 struct {
                         compat_pid_t _pid;      /* which child */
-                        __compat_uid_t _uid;    /* sender's uid */
+                        __compat_uid32_t _uid;  /* sender's uid */
                         int _status;            /* exit code */
                         compat_clock_t _utime;
                         compat_clock_t _stime;
                 } _sigchld;
 
-                /* IRIX SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        compat_clock_t _utime;
-                        int _status;            /* exit code */
-                        compat_clock_t _stime;
-                } _irix_sigchld;
-
                 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
                 struct {
-                        s32 _addr; /* faulting insn/memory ref. */
+                        compat_uptr_t _addr;    /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+                        int _trapno;    /* TRAP # which caused the signal */
+#endif
+                        short _addr_lsb; /* LSB of the reported address */
+                        struct {
+                                compat_uptr_t _lower;
+                                compat_uptr_t _upper;
+                        } _addr_bnd;
                 } _sigfault;
 
-                /* SIGPOLL, SIGXFSZ (To do ...)  */
+                /* SIGPOLL */
                 struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
+                        compat_long_t _band; /* POLL_IN, POLL_OUT, POLL_MSG */
                         int _fd;
                 } _sigpoll;
 
-                /* POSIX.1b timers */
-                struct {
-                        timer_t _tid;           /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;/* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
                 struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        __compat_uid_t _uid;    /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
+                        compat_uptr_t _call_addr; /* calling insn */
+                        int _syscall;   /* triggering system call number */
+                        compat_uint_t _arch;    /* AUDIT_ARCH_* of syscall */
+                } _sigsys;
         } _sifields;
 } compat_siginfo_t;
 
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index fe67f12ac239..d1e04c943f5f 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -131,11 +131,7 @@
 #endif
 
 #ifndef cpu_has_rixi
-# ifdef CONFIG_64BIT
-# define cpu_has_rixi           (cpu_data[0].options & MIPS_CPU_RIXI)
-# else /* CONFIG_32BIT */
-# define cpu_has_rixi           ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
-# endif
+#define cpu_has_rixi            (cpu_data[0].options & MIPS_CPU_RIXI)
 #endif
 
 #ifndef cpu_has_mmips
diff --git a/arch/mips/include/asm/debug.h b/arch/mips/include/asm/debug.h
new file mode 100644
index 000000000000..254f00deb9d5
--- /dev/null
+++ b/arch/mips/include/asm/debug.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MIPS_ASM_DEBUG_H__
+#define __MIPS_ASM_DEBUG_H__
+
+#include <linux/dcache.h>
+
+/*
+ * mips_debugfs_dir corresponds to the "mips" directory at the top level
+ * of the DebugFS hierarchy. MIPS-specific DebugFS entires should be
+ * placed beneath this directory.
+ */
+extern struct dentry *mips_debugfs_dir;
+
+#endif /* __MIPS_ASM_DEBUG_H__ */
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 53b26933b12c..b01a6ff468e0 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -8,6 +8,7 @@
 #ifndef _ASM_ELF_H
 #define _ASM_ELF_H
 
+#include <linux/auxvec.h>
 #include <linux/fs.h>
 #include <uapi/linux/elf.h>
 
@@ -419,6 +420,12 @@ extern const char *__elf_platform;
 #define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
 #endif
 
+#define ARCH_DLINFO                                                     \
+do {                                                                    \
+        NEW_AUX_ENT(AT_SYSINFO_EHDR,                                    \
+                    (unsigned long)current->mm->context.vdso);          \
+} while (0)
+
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
 struct linux_binprm;
 extern int arch_setup_additional_pages(struct linux_binprm *bprm,
diff --git a/arch/mips/include/asm/fw/fw.h b/arch/mips/include/asm/fw/fw.h
index f3e6978aad70..d0ef8b4892bb 100644
--- a/arch/mips/include/asm/fw/fw.h
+++ b/arch/mips/include/asm/fw/fw.h
@@ -10,21 +10,6 @@
 
 #include <asm/bootinfo.h>       /* For cleaner code... */
 
-enum fw_memtypes {
-        fw_dontuse,
-        fw_code,
-        fw_free,
-};
-
-typedef struct {
-        unsigned long base;     /* Within KSEG0 */
-        unsigned int size;      /* bytes */
-        enum fw_memtypes type;  /* fw_memtypes */
-} fw_memblock_t;
-
-/* Maximum number of memory block descriptors. */
-#define FW_MAX_MEMBLOCKS        32
-
 extern int fw_argc;
 extern int *_fw_argv;
 extern int *_fw_envp;
@@ -38,7 +23,6 @@ extern int *_fw_envp;
 
 extern void fw_init_cmdline(void);
 extern char *fw_getcmdline(void);
-extern fw_memblock_t *fw_getmdesc(int);
 extern void fw_meminit(void);
 extern char *fw_getenv(char *name);
 extern unsigned long fw_getenvl(char *name);
diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
index 1461c10c1c4c..71e4096a2145 100644
--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
@@ -48,11 +48,6 @@ extern enum bcm47xx_bus_type bcm47xx_bus_type;
 void bcm47xx_fill_sprom(struct ssb_sprom *sprom, const char *prefix,
                         bool fallback);
 
-#ifdef CONFIG_BCM47XX_SSB
-void bcm47xx_fill_ssb_boardinfo(struct ssb_boardinfo *boardinfo,
-                                const char *prefix);
-#endif
-
 void bcm47xx_set_system_type(u16 chip_id);
 
 #endif /* __ASM_BCM47XX_H */
diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 133336b493b6..dd6005b75e0c 100644
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -35,6 +35,17 @@
 #define SOC_ID_VRX268_2         0x00C /* v1.2 */
 #define SOC_ID_GRX288_2         0x00D /* v1.2 */
 #define SOC_ID_GRX282_2         0x00E /* v1.2 */
+#define SOC_ID_VRX220           0x000
+
+#define SOC_ID_ARX362           0x004
+#define SOC_ID_ARX368           0x005
+#define SOC_ID_ARX382           0x007
+#define SOC_ID_ARX388           0x008
+#define SOC_ID_URX388           0x009
+#define SOC_ID_GRX383           0x010
+#define SOC_ID_GRX369           0x011
+#define SOC_ID_GRX387           0x00F
+#define SOC_ID_GRX389           0x012
 
  /* SoC Types */
 #define SOC_TYPE_DANUBE         0x01
@@ -43,6 +54,9 @@
 #define SOC_TYPE_VR9            0x04 /* v1.1 */
 #define SOC_TYPE_VR9_2          0x05 /* v1.2 */
 #define SOC_TYPE_AMAZON_SE      0x06
+#define SOC_TYPE_AR10           0x07
+#define SOC_TYPE_GRX390         0x08
+#define SOC_TYPE_VRX220         0x09
 
 /* BOOT_SEL - find what boot media we have */
 #define BS_EXT_ROM              0x0
diff --git a/arch/mips/include/asm/mach-malta/malta-dtshim.h b/arch/mips/include/asm/mach-malta/malta-dtshim.h
new file mode 100644
index 000000000000..cfd777663c64
--- /dev/null
+++ b/arch/mips/include/asm/mach-malta/malta-dtshim.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MIPS_MALTA_DTSHIM_H__
+#define __MIPS_MALTA_DTSHIM_H__
+
+#include <linux/init.h>
+
+#ifdef CONFIG_MIPS_MALTA
+
+extern void __init *malta_dt_shim(void *fdt);
+
+#else /* !CONFIG_MIPS_MALTA */
+
+static inline void *malta_dt_shim(void *fdt)
+{
+        return fdt;
+}
+
+#endif /* !CONFIG_MIPS_MALTA */
+
+#endif /* __MIPS_MALTA_DTSHIM_H__ */
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 1976fb815fd1..455d406e8ddf 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -13,17 +13,11 @@
 #ifndef _MT7620_REGS_H_
 #define _MT7620_REGS_H_
 
-enum mt762x_soc_type {
-        MT762X_SOC_UNKNOWN = 0,
-        MT762X_SOC_MT7620A,
-        MT762X_SOC_MT7620N,
-        MT762X_SOC_MT7628AN,
-};
-
 #define MT7620_SYSC_BASE                0x10000000
 
 #define SYSC_REG_CHIP_NAME0             0x00
 #define SYSC_REG_CHIP_NAME1             0x04
+#define SYSC_REG_EFUSE_CFG              0x08
 #define SYSC_REG_CHIP_REV               0x0c
 #define SYSC_REG_SYSTEM_CONFIG0         0x10
 #define SYSC_REG_SYSTEM_CONFIG1         0x14
diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
index bd93014490df..4c9fba68c8b2 100644
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -13,6 +13,23 @@
 #ifndef _RALINK_REGS_H_
 #define _RALINK_REGS_H_
 
+enum ralink_soc_type {
+        RALINK_UNKNOWN = 0,
+        RT2880_SOC,
+        RT3883_SOC,
+        RT305X_SOC_RT3050,
+        RT305X_SOC_RT3052,
+        RT305X_SOC_RT3350,
+        RT305X_SOC_RT3352,
+        RT305X_SOC_RT5350,
+        MT762X_SOC_MT7620A,
+        MT762X_SOC_MT7620N,
+        MT762X_SOC_MT7621AT,
+        MT762X_SOC_MT7628AN,
+        MT762X_SOC_MT7688,
+};
+extern enum ralink_soc_type ralink_soc;
+
 extern __iomem void *rt_sysc_membase;
 extern __iomem void *rt_memc_membase;
 
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
index 96f731bac79a..2eea79331a14 100644
--- a/arch/mips/include/asm/mach-ralink/rt305x.h
+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
@@ -13,25 +13,16 @@
 #ifndef _RT305X_REGS_H_
 #define _RT305X_REGS_H_
 
-enum rt305x_soc_type {
-        RT305X_SOC_UNKNOWN = 0,
-        RT305X_SOC_RT3050,
-        RT305X_SOC_RT3052,
-        RT305X_SOC_RT3350,
-        RT305X_SOC_RT3352,
-        RT305X_SOC_RT5350,
-};
-
-extern enum rt305x_soc_type rt305x_soc;
+extern enum ralink_soc_type ralink_soc;
 
 static inline int soc_is_rt3050(void)
 {
-        return rt305x_soc == RT305X_SOC_RT3050;
+        return ralink_soc == RT305X_SOC_RT3050;
 }
 
 static inline int soc_is_rt3052(void)
 {
-        return rt305x_soc == RT305X_SOC_RT3052;
+        return ralink_soc == RT305X_SOC_RT3052;
 }
 
 static inline int soc_is_rt305x(void)
@@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void)
 
 static inline int soc_is_rt3350(void)
 {
-        return rt305x_soc == RT305X_SOC_RT3350;
+        return ralink_soc == RT305X_SOC_RT3350;
 }
 
 static inline int soc_is_rt3352(void)
 {
-        return rt305x_soc == RT305X_SOC_RT3352;
+        return ralink_soc == RT305X_SOC_RT3352;
 }
 
 static inline int soc_is_rt5350(void)
 {
-        return rt305x_soc == RT305X_SOC_RT5350;
+        return ralink_soc == RT305X_SOC_RT5350;
 }
 
 #define RT305X_SYSC_BASE                0x10000000
diff --git a/arch/mips/include/asm/mach-xilfpga/irq.h b/arch/mips/include/asm/mach-xilfpga/irq.h
new file mode 100644
index 000000000000..0132a5b91f57
--- /dev/null
+++ b/arch/mips/include/asm/mach-xilfpga/irq.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MIPS_ASM_MACH_XILFPGA_IRQ_H__
+#define __MIPS_ASM_MACH_XILFPGA_IRQ_H__
+
+#define NR_IRQS 32
+
+#include_next <irq.h>
+
+#endif /* __MIPS_ASM_MACH_XILFPGA_IRQ_H__ */
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 1f1927ab4269..6516e9da5133 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -11,6 +11,7 @@
 #ifndef __MIPS_ASM_MIPS_CM_H__
 #define __MIPS_ASM_MIPS_CM_H__
 
+#include <linux/bitops.h>
 #include <linux/errno.h>
 #include <linux/io.h>
 #include <linux/types.h>
@@ -36,12 +37,12 @@ extern phys_addr_t __mips_cm_phys_base(void);
 /*
  * mips_cm_is64 - determine CM register width
  *
- * The CM register width is processor and CM specific. A 64-bit processor
- * usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit
- * processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs
- * can be done either using regular 64-bit load/store instructions, or 32-bit
- * load/store instruction on 32-bit register pairs. We opt for using 64-bit
- * accesses on 64-bit CMs and kernels and 32-bit in any other case.
+ * The CM register width is determined by the version of the CM, with CM3
+ * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
+ * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
+ * or vice-versa. This variable indicates the width of the memory accesses
+ * that the kernel will perform to GCRs, which may differ from the actual
+ * width of the GCRs.
  *
  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
  */
@@ -125,7 +126,17 @@ static inline u32 read32_gcr_##name(void)			\
                                                                 \
 static inline u64 read64_gcr_##name(void)                       \
 {                                                               \
-        return __raw_readq(addr_gcr_##name());                  \
+        void __iomem *addr = addr_gcr_##name();                 \
+        u64 ret;                                                \
+                                                                \
+        if (mips_cm_is64) {                                     \
+                ret = __raw_readq(addr);                        \
+        } else {                                                \
+                ret = __raw_readl(addr);                        \
+                ret |= (u64)__raw_readl(addr + 0x4) << 32;      \
+        }                                                       \
+                                                                \
+        return ret;                                             \
 }                                                               \
                                                                 \
 static inline unsigned long read_gcr_##name(void)               \
@@ -195,6 +206,8 @@ BUILD_CM_R_(gic_status,		MIPS_CM_GCB_OFS + 0xd0)
 BUILD_CM_R_(cpc_status,         MIPS_CM_GCB_OFS + 0xf0)
 BUILD_CM_RW(l2_config,          MIPS_CM_GCB_OFS + 0x130)
 BUILD_CM_RW(sys_config2,        MIPS_CM_GCB_OFS + 0x150)
+BUILD_CM_RW(l2_pft_control,     MIPS_CM_GCB_OFS + 0x300)
+BUILD_CM_RW(l2_pft_control_b,   MIPS_CM_GCB_OFS + 0x308)
 
 /* Core Local & Core Other register accessor functions */
 BUILD_CM_Cx_RW(reset_release,   0x00)
@@ -245,11 +258,14 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
                  ((minor) << CM_GCR_REV_MINOR_SHF))
 
 #define CM_REV_CM2                              CM_ENCODE_REV(6, 0)
+#define CM_REV_CM2_5                            CM_ENCODE_REV(7, 0)
 #define CM_REV_CM3                              CM_ENCODE_REV(8, 0)
 
 /* GCR_ERROR_CAUSE register fields */
 #define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF          27
 #define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK          (_ULCAST_(0x1f) << 27)
+#define CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF         58
+#define CM3_GCR_ERROR_CAUSE_ERRTYPE_MSK         GENMASK_ULL(63, 58)
 #define CM_GCR_ERROR_CAUSE_ERRINFO_SHF          0
 #define CM_GCR_ERROR_CAUSE_ERRINGO_MSK          (_ULCAST_(0x7ffffff) << 0)
 
@@ -321,6 +337,20 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
 #define CM_GCR_SYS_CONFIG2_MAXVPW_SHF           0
 #define CM_GCR_SYS_CONFIG2_MAXVPW_MSK           (_ULCAST_(0xf) << 0)
 
+/* GCR_L2_PFT_CONTROL register fields */
+#define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF      12
+#define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK      (_ULCAST_(0xfffff) << 12)
+#define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF         8
+#define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK         (_ULCAST_(0x1) << 8)
+#define CM_GCR_L2_PFT_CONTROL_NPFT_SHF          0
+#define CM_GCR_L2_PFT_CONTROL_NPFT_MSK          (_ULCAST_(0xff) << 0)
+
+/* GCR_L2_PFT_CONTROL_B register fields */
+#define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF         8
+#define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK         (_ULCAST_(0x1) << 8)
+#define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF      0
+#define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK      (_ULCAST_(0xff) << 0)
+
 /* GCR_Cx_COHERENCE register fields */
 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF     0
 #define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK     (_ULCAST_(0xff) << 0)
@@ -329,11 +359,15 @@ BUILD_CM_Cx_R_(tcid_8_priority,	0x80)
 #define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF           10
 #define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK           (_ULCAST_(0x3) << 10)
 #define CM_GCR_Cx_CONFIG_PVPE_SHF               0
-#define CM_GCR_Cx_CONFIG_PVPE_MSK               (_ULCAST_(0x1ff) << 0)
+#define CM_GCR_Cx_CONFIG_PVPE_MSK               (_ULCAST_(0x3ff) << 0)
 
 /* GCR_Cx_OTHER register fields */
 #define CM_GCR_Cx_OTHER_CORENUM_SHF             16
 #define CM_GCR_Cx_OTHER_CORENUM_MSK             (_ULCAST_(0xffff) << 16)
+#define CM3_GCR_Cx_OTHER_CORE_SHF               8
+#define CM3_GCR_Cx_OTHER_CORE_MSK               (_ULCAST_(0x3f) << 8)
+#define CM3_GCR_Cx_OTHER_VP_SHF                 0
+#define CM3_GCR_Cx_OTHER_VP_MSK                 (_ULCAST_(0x7) << 0)
 
 /* GCR_Cx_RESET_BASE register fields */
 #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF     12
@@ -444,4 +478,32 @@ static inline unsigned int mips_cm_vp_id(unsigned int cpu)
         return (core * mips_cm_max_vp_width()) + vp;
 }
 
+#ifdef CONFIG_MIPS_CM
+
+/**
+ * mips_cm_lock_other - lock access to another core
+ * @core: the other core to be accessed
+ * @vp: the VP within the other core to be accessed
+ *
+ * Call before operating upon a core via the 'other' register region in
+ * order to prevent the region being moved during access. Must be followed
+ * by a call to mips_cm_unlock_other.
+ */
+extern void mips_cm_lock_other(unsigned int core, unsigned int vp);
+
+/**
+ * mips_cm_unlock_other - unlock access to another core
+ *
+ * Call after operating upon another core via the 'other' register region.
+ * Must be called after mips_cm_lock_other.
+ */
+extern void mips_cm_unlock_other(void);
+
+#else /* !CONFIG_MIPS_CM */
+
+static inline void mips_cm_lock_other(unsigned int core) { }
+static inline void mips_cm_unlock_other(void) { }
+
+#endif /* !CONFIG_MIPS_CM */
+
 #endif /* __MIPS_ASM_MIPS_CM_H__ */
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
index f386f32702f1..e09035239e53 100644
--- a/arch/mips/include/asm/mips-cpc.h
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -149,7 +149,8 @@ BUILD_CPC_Cx_RW(other,		0x10)
  * core: the other core to be accessed
  *
  * Call before operating upon a core via the 'other' register region in
- * order to prevent the region being moved during access. Must be followed
+ * order to prevent the region being moved during access. Must be called
+ * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
  * by a call to mips_cpc_unlock_other.
  */
 extern void mips_cpc_lock_other(unsigned int core);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c64781cf649f..e43aca183c99 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -50,7 +50,9 @@
 #define CP0_PAGEMASK $5
 #define CP0_WIRED $6
 #define CP0_INFO $7
+#define CP0_HWRENA $7, 0
 #define CP0_BADVADDR $8
+#define CP0_BADINSTR $8, 1
 #define CP0_COUNT $9
 #define CP0_ENTRYHI $10
 #define CP0_COMPARE $11
@@ -58,7 +60,11 @@
 #define CP0_CAUSE $13
 #define CP0_EPC $14
 #define CP0_PRID $15
+#define CP0_EBASE $15, 1
+#define CP0_CMGCRBASE $15, 3
 #define CP0_CONFIG $16
+#define CP0_CONFIG3 $16, 3
+#define CP0_CONFIG5 $16, 5
 #define CP0_LLADDR $17
 #define CP0_WATCHLO $18
 #define CP0_WATCHHI $19
@@ -126,15 +132,9 @@
 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 
 /* MIPS32/64 EntryLo bit definitions */
-#ifdef CONFIG_64BIT
-/* as read by dmfc0 */
-#define MIPS_ENTRYLO_XI         (_ULCAST_(1) << 62)
-#define MIPS_ENTRYLO_RI         (_ULCAST_(1) << 63)
-#else
-/* as read by mfc0 */
-#define MIPS_ENTRYLO_XI         (_ULCAST_(1) << 30)
-#define MIPS_ENTRYLO_RI         (_ULCAST_(1) << 31)
-#endif
+#define MIPS_ENTRYLO_PFN_SHIFT  6
+#define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
+#define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 
 /*
  * Values for PageMask register
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 89dd7fed1a57..ad1fccdb8d13 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -33,7 +33,7 @@
 #define PAGE_SHIFT      16
 #endif
 #define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
+#define PAGE_MASK       (~(PAGE_SIZE - 1))
 
 /*
  * This is used for calculating the real page sizes
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 59ee6dcf6eed..3f832c3dd8f5 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -36,12 +36,6 @@ extern unsigned int vced_count, vcei_count;
  */
 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 
-/*
- * A special page (the vdso) is mapped into all processes at the very
- * top of the virtual memory space.
- */
-#define SPECIAL_PAGES_SIZE PAGE_SIZE
-
 #ifdef CONFIG_32BIT
 #ifdef CONFIG_KVM_GUEST
 /* User space process size is limited to 1GB in KVM Guest Mode */
@@ -80,7 +74,7 @@ extern unsigned int vced_count, vcei_count;
 
 #endif
 
-#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
+#define STACK_TOP       (TASK_SIZE & PAGE_MASK)
 
 /*
  * This decides where the kernel will search for a free chunk of vm
diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h
index cca56aa40ff4..8f4ca5dd992b 100644
--- a/arch/mips/include/asm/vdso.h
+++ b/arch/mips/include/asm/vdso.h
@@ -1,29 +1,136 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Copyright (C) 2015 Imagination Technologies
+ * Author: Alex Smith <alex.smith@imgtec.com>
  *
- * Copyright (C) 2009 Cavium Networks
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
 
 #ifndef __ASM_VDSO_H
 #define __ASM_VDSO_H
 
-#include <linux/types.h>
+#include <linux/mm_types.h>
 
+#include <asm/barrier.h>
 
-#ifdef CONFIG_32BIT
-struct mips_vdso {
-        u32 signal_trampoline[2];
-        u32 rt_signal_trampoline[2];
+/**
+ * struct mips_vdso_image - Details of a VDSO image.
+ * @data: Pointer to VDSO image data (page-aligned).
+ * @size: Size of the VDSO image data (page-aligned).
+ * @off_sigreturn: Offset of the sigreturn() trampoline.
+ * @off_rt_sigreturn: Offset of the rt_sigreturn() trampoline.
+ * @mapping: Special mapping structure.
+ *
+ * This structure contains details of a VDSO image, including the image data
+ * and offsets of certain symbols required by the kernel. It is generated as
+ * part of the VDSO build process, aside from the mapping page array, which is
+ * populated at runtime.
+ */
+struct mips_vdso_image {
+        void *data;
+        unsigned long size;
+
+        unsigned long off_sigreturn;
+        unsigned long off_rt_sigreturn;
+
+        struct vm_special_mapping mapping;
 };
-#else  /* !CONFIG_32BIT */
-struct mips_vdso {
-        u32 o32_signal_trampoline[2];
-        u32 o32_rt_signal_trampoline[2];
-        u32 rt_signal_trampoline[2];
-        u32 n32_rt_signal_trampoline[2];
+
+/*
+ * The following structures are auto-generated as part of the build for each
+ * ABI by genvdso, see arch/mips/vdso/Makefile.
+ */
+
+extern struct mips_vdso_image vdso_image;
+
+#ifdef CONFIG_MIPS32_O32
+extern struct mips_vdso_image vdso_image_o32;
+#endif
+
+#ifdef CONFIG_MIPS32_N32
+extern struct mips_vdso_image vdso_image_n32;
+#endif
+
+/**
+ * union mips_vdso_data - Data provided by the kernel for the VDSO.
+ * @xtime_sec:          Current real time (seconds part).
+ * @xtime_nsec:         Current real time (nanoseconds part, shifted).
+ * @wall_to_mono_sec:   Wall-to-monotonic offset (seconds part).
+ * @wall_to_mono_nsec:  Wall-to-monotonic offset (nanoseconds part).
+ * @seq_count:          Counter to synchronise updates (odd = updating).
+ * @cs_shift:           Clocksource shift value.
+ * @clock_mode:         Clocksource to use for time functions.
+ * @cs_mult:            Clocksource multiplier value.
+ * @cs_cycle_last:      Clock cycle value at last update.
+ * @cs_mask:            Clocksource mask value.
+ * @tz_minuteswest:     Minutes west of Greenwich (from timezone).
+ * @tz_dsttime:         Type of DST correction (from timezone).
+ *
+ * This structure contains data needed by functions within the VDSO. It is
+ * populated by the kernel and mapped read-only into user memory. The time
+ * fields are mirrors of internal data from the timekeeping infrastructure.
+ *
+ * Note: Care should be taken when modifying as the layout must remain the same
+ * for both 64- and 32-bit (for 32-bit userland on 64-bit kernel).
+ */
+union mips_vdso_data {
+        struct {
+                u64 xtime_sec;
+                u64 xtime_nsec;
+                u32 wall_to_mono_sec;
+                u32 wall_to_mono_nsec;
+                u32 seq_count;
+                u32 cs_shift;
+                u8 clock_mode;
+                u32 cs_mult;
+                u64 cs_cycle_last;
+                u64 cs_mask;
+                s32 tz_minuteswest;
+                s32 tz_dsttime;
+        };
+
+        u8 page[PAGE_SIZE];
 };
-#endif /* CONFIG_32BIT */
+
+static inline u32 vdso_data_read_begin(const union mips_vdso_data *data)
+{
+        u32 seq;
+
+        while (true) {
+                seq = ACCESS_ONCE(data->seq_count);
+                if (likely(!(seq & 1))) {
+                        /* Paired with smp_wmb() in vdso_data_write_*(). */
+                        smp_rmb();
+                        return seq;
+                }
+
+                cpu_relax();
+        }
+}
+
+static inline bool vdso_data_read_retry(const union mips_vdso_data *data,
+                                        u32 start_seq)
+{
+        /* Paired with smp_wmb() in vdso_data_write_*(). */
+        smp_rmb();
+        return unlikely(data->seq_count != start_seq);
+}
+
+static inline void vdso_data_write_begin(union mips_vdso_data *data)
+{
+        ++data->seq_count;
+
+        /* Ensure sequence update is written before other data page values. */
+        smp_wmb();
+}
+
+static inline void vdso_data_write_end(union mips_vdso_data *data)
+{
+        /* Ensure data values are written before updating sequence again. */
+        smp_wmb();
+        ++data->seq_count;
+}
 
 #endif /* __ASM_VDSO_H */