diff options
Diffstat (limited to 'arch/mips/include/asm/sibyte/bcm1480_scd.h')
-rw-r--r-- | arch/mips/include/asm/sibyte/bcm1480_scd.h | 276 |
1 files changed, 138 insertions, 138 deletions
diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h index 2af3706b9648..8a1e2b05a626 100644 --- a/arch/mips/include/asm/sibyte/bcm1480_scd.h +++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* ********************************************************************* | 1 | /* ********************************************************************* |
2 | * BCM1280/BCM1400 Board Support Package | 2 | * BCM1280/BCM1400 Board Support Package |
3 | * | 3 | * |
4 | * SCD Constants and Macros File: bcm1480_scd.h | 4 | * SCD Constants and Macros File: bcm1480_scd.h |
5 | * | 5 | * |
6 | * This module contains constants and macros useful for | 6 | * This module contains constants and macros useful for |
7 | * manipulating the System Control and Debug module. | 7 | * manipulating the System Control and Debug module. |
@@ -74,11 +74,11 @@ | |||
74 | * New part definitions | 74 | * New part definitions |
75 | */ | 75 | */ |
76 | 76 | ||
77 | #define K_SYS_PART_BCM1480 0x1406 | 77 | #define K_SYS_PART_BCM1480 0x1406 |
78 | #define K_SYS_PART_BCM1280 0x1206 | 78 | #define K_SYS_PART_BCM1280 0x1206 |
79 | #define K_SYS_PART_BCM1455 0x1407 | 79 | #define K_SYS_PART_BCM1455 0x1407 |
80 | #define K_SYS_PART_BCM1255 0x1257 | 80 | #define K_SYS_PART_BCM1255 0x1257 |
81 | #define K_SYS_PART_BCM1158 0x1156 | 81 | #define K_SYS_PART_BCM1158 0x1156 |
82 | 82 | ||
83 | /* | 83 | /* |
84 | * Manufacturing Information Register (Table 14) | 84 | * Manufacturing Information Register (Table 14) |
@@ -91,73 +91,73 @@ | |||
91 | * Entire register is different from 1250, all new constants below | 91 | * Entire register is different from 1250, all new constants below |
92 | */ | 92 | */ |
93 | 93 | ||
94 | #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) | 94 | #define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) |
95 | #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) | 95 | #define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) |
96 | #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) | 96 | #define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) |
97 | #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) | 97 | #define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) |
98 | #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) | 98 | #define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) |
99 | #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) | 99 | #define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) |
100 | 100 | ||
101 | #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) | 101 | #define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) |
102 | #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) | 102 | #define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) |
103 | #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) | 103 | #define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) |
104 | #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) | 104 | #define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) |
105 | 105 | ||
106 | #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) | 106 | #define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) |
107 | #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) | 107 | #define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) |
108 | #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) | 108 | #define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) |
109 | #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) | 109 | #define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) |
110 | 110 | ||
111 | #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) | 111 | #define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) |
112 | #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) | 112 | #define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) |
113 | 113 | ||
114 | #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) | 114 | #define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) |
115 | #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) | 115 | #define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) |
116 | #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) | 116 | #define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) |
117 | #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) | 117 | #define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) |
118 | #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 | 118 | #define K_BCM1480_SYS_BOOT_MODE_ROM32 0 |
119 | #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 | 119 | #define K_BCM1480_SYS_BOOT_MODE_ROM8 1 |
120 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 | 120 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 |
121 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 | 121 | #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 |
122 | #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) | 122 | #define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) |
123 | 123 | ||
124 | #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) | 124 | #define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) |
125 | #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) | 125 | #define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) |
126 | #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) | 126 | #define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) |
127 | #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) | 127 | #define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) |
128 | #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) | 128 | #define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) |
129 | #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) | 129 | #define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) |
130 | 130 | ||
131 | #define S_BCM1480_SYS_CONFIG 26 | 131 | #define S_BCM1480_SYS_CONFIG 26 |
132 | #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) | 132 | #define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) |
133 | #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) | 133 | #define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) |
134 | #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) | 134 | #define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) |
135 | 135 | ||
136 | #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) | 136 | #define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) |
137 | 137 | ||
138 | #define S_BCM1480_SYS_NODEID 47 | 138 | #define S_BCM1480_SYS_NODEID 47 |
139 | #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) | 139 | #define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) |
140 | #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) | 140 | #define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) |
141 | #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) | 141 | #define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) |
142 | 142 | ||
143 | #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) | 143 | #define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) |
144 | #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) | 144 | #define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) |
145 | #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) | 145 | #define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) |
146 | #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) | 146 | #define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) |
147 | #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) | 147 | #define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) |
148 | #define S_BCM1480_SYS_DISABLECPU0 56 | 148 | #define S_BCM1480_SYS_DISABLECPU0 56 |
149 | #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) | 149 | #define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) |
150 | #define S_BCM1480_SYS_DISABLECPU1 57 | 150 | #define S_BCM1480_SYS_DISABLECPU1 57 |
151 | #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) | 151 | #define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) |
152 | #define S_BCM1480_SYS_DISABLECPU2 58 | 152 | #define S_BCM1480_SYS_DISABLECPU2 58 |
153 | #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) | 153 | #define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) |
154 | #define S_BCM1480_SYS_DISABLECPU3 59 | 154 | #define S_BCM1480_SYS_DISABLECPU3 59 |
155 | #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) | 155 | #define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) |
156 | 156 | ||
157 | #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) | 157 | #define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) |
158 | #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) | 158 | #define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) |
159 | #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) | 159 | #define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) |
160 | #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) | 160 | #define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) |
161 | 161 | ||
162 | /* | 162 | /* |
163 | * Scratch Register (Table 16) | 163 | * Scratch Register (Table 16) |
@@ -193,23 +193,23 @@ | |||
193 | * Registers: SCD_WDOG_CFG_x | 193 | * Registers: SCD_WDOG_CFG_x |
194 | */ | 194 | */ |
195 | 195 | ||
196 | #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) | 196 | #define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) |
197 | 197 | ||
198 | #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 | 198 | #define S_BCM1480_SCD_WDOG_RESET_TYPE 2 |
199 | #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) | 199 | #define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) |
200 | #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) | 200 | #define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) |
201 | #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) | 201 | #define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) |
202 | 202 | ||
203 | #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ | 203 | #define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ |
204 | #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 | 204 | #define K_BCM1480_SCD_WDOG_RESET_SOFT 1 |
205 | #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 | 205 | #define K_BCM1480_SCD_WDOG_RESET_CPU0 3 |
206 | #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 | 206 | #define K_BCM1480_SCD_WDOG_RESET_CPU1 5 |
207 | #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 | 207 | #define K_BCM1480_SCD_WDOG_RESET_CPU2 9 |
208 | #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 | 208 | #define K_BCM1480_SCD_WDOG_RESET_CPU3 17 |
209 | #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 | 209 | #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 |
210 | 210 | ||
211 | 211 | ||
212 | #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) | 212 | #define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) |
213 | 213 | ||
214 | /* | 214 | /* |
215 | * General Timer Initial Count Registers (Table 26) | 215 | * General Timer Initial Count Registers (Table 26) |
@@ -243,32 +243,32 @@ | |||
243 | * The clear/enable bits are in different locations on the 1250 and 1480. | 243 | * The clear/enable bits are in different locations on the 1250 and 1480. |
244 | */ | 244 | */ |
245 | 245 | ||
246 | #define S_SPC_CFG_SRC4 32 | 246 | #define S_SPC_CFG_SRC4 32 |
247 | #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) | 247 | #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) |
248 | #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) | 248 | #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) |
249 | #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) | 249 | #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) |
250 | 250 | ||
251 | #define S_SPC_CFG_SRC5 40 | 251 | #define S_SPC_CFG_SRC5 40 |
252 | #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) | 252 | #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) |
253 | #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) | 253 | #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) |
254 | #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) | 254 | #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) |
255 | 255 | ||
256 | #define S_SPC_CFG_SRC6 48 | 256 | #define S_SPC_CFG_SRC6 48 |
257 | #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) | 257 | #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) |
258 | #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) | 258 | #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) |
259 | #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) | 259 | #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) |
260 | 260 | ||
261 | #define S_SPC_CFG_SRC7 56 | 261 | #define S_SPC_CFG_SRC7 56 |
262 | #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) | 262 | #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) |
263 | #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) | 263 | #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) |
264 | #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) | 264 | #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) |
265 | 265 | ||
266 | /* | 266 | /* |
267 | * System Performance Counter Control Register (Table 32) | 267 | * System Performance Counter Control Register (Table 32) |
268 | * Register: PERF_CNT_CFG_1 | 268 | * Register: PERF_CNT_CFG_1 |
269 | * BCM1480 specific | 269 | * BCM1480 specific |
270 | */ | 270 | */ |
271 | #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) | 271 | #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) |
272 | #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) | 272 | #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) |
273 | #if SIBYTE_HDR_FEATURE_CHIP(1480) | 273 | #if SIBYTE_HDR_FEATURE_CHIP(1480) |
274 | #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR | 274 | #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR |
@@ -280,12 +280,12 @@ | |||
280 | * Registers: PERF_CNT_x | 280 | * Registers: PERF_CNT_x |
281 | */ | 281 | */ |
282 | 282 | ||
283 | #define S_BCM1480_SPC_CNT_COUNT 0 | 283 | #define S_BCM1480_SPC_CNT_COUNT 0 |
284 | #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) | 284 | #define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) |
285 | #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) | 285 | #define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) |
286 | #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) | 286 | #define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) |
287 | 287 | ||
288 | #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) | 288 | #define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) |
289 | 289 | ||
290 | 290 | ||
291 | /* | 291 | /* |
@@ -325,45 +325,45 @@ | |||
325 | #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) | 325 | #define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) |
326 | #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) | 326 | #define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) |
327 | 327 | ||
328 | #define S_BCM1480_ATRAP_CFG_CNT 0 | 328 | #define S_BCM1480_ATRAP_CFG_CNT 0 |
329 | #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) | 329 | #define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) |
330 | #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) | 330 | #define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) |
331 | #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) | 331 | #define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) |
332 | 332 | ||
333 | #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) | 333 | #define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) |
334 | #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) | 334 | #define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) |
335 | #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) | 335 | #define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) |
336 | #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) | 336 | #define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) |
337 | #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) | 337 | #define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) |
338 | 338 | ||
339 | #define S_BCM1480_ATRAP_CFG_AGENTID 8 | 339 | #define S_BCM1480_ATRAP_CFG_AGENTID 8 |
340 | #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) | 340 | #define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) |
341 | #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) | 341 | #define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) |
342 | #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) | 342 | #define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) |
343 | 343 | ||
344 | 344 | ||
345 | #define K_BCM1480_BUS_AGENT_CPU0 0 | 345 | #define K_BCM1480_BUS_AGENT_CPU0 0 |
346 | #define K_BCM1480_BUS_AGENT_CPU1 1 | 346 | #define K_BCM1480_BUS_AGENT_CPU1 1 |
347 | #define K_BCM1480_BUS_AGENT_NC 2 | 347 | #define K_BCM1480_BUS_AGENT_NC 2 |
348 | #define K_BCM1480_BUS_AGENT_IOB 3 | 348 | #define K_BCM1480_BUS_AGENT_IOB 3 |
349 | #define K_BCM1480_BUS_AGENT_SCD 4 | 349 | #define K_BCM1480_BUS_AGENT_SCD 4 |
350 | #define K_BCM1480_BUS_AGENT_L2C 6 | 350 | #define K_BCM1480_BUS_AGENT_L2C 6 |
351 | #define K_BCM1480_BUS_AGENT_MC 7 | 351 | #define K_BCM1480_BUS_AGENT_MC 7 |
352 | #define K_BCM1480_BUS_AGENT_CPU2 8 | 352 | #define K_BCM1480_BUS_AGENT_CPU2 8 |
353 | #define K_BCM1480_BUS_AGENT_CPU3 9 | 353 | #define K_BCM1480_BUS_AGENT_CPU3 9 |
354 | #define K_BCM1480_BUS_AGENT_PM 10 | 354 | #define K_BCM1480_BUS_AGENT_PM 10 |
355 | 355 | ||
356 | #define S_BCM1480_ATRAP_CFG_CATTR 12 | 356 | #define S_BCM1480_ATRAP_CFG_CATTR 12 |
357 | #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) | 357 | #define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) |
358 | #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) | 358 | #define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) |
359 | #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) | 359 | #define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) |
360 | 360 | ||
361 | #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 | 361 | #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 |
362 | #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 | 362 | #define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 |
363 | #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 | 363 | #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 |
364 | #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 | 364 | #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 |
365 | 365 | ||
366 | #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) | 366 | #define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) |
367 | 367 | ||
368 | 368 | ||
369 | /* | 369 | /* |
@@ -381,10 +381,10 @@ | |||
381 | 381 | ||
382 | #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) | 382 | #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) |
383 | 383 | ||
384 | #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 | 384 | #define S_BCM1480_SCD_TRSEQ_SWFUNC 26 |
385 | #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) | 385 | #define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) |
386 | #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) | 386 | #define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) |
387 | #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) | 387 | #define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) |
388 | 388 | ||
389 | /* | 389 | /* |
390 | * Trace Control Register (Table 49) | 390 | * Trace Control Register (Table 49) |
@@ -394,13 +394,13 @@ | |||
394 | * are defined below. | 394 | * are defined below. |
395 | */ | 395 | */ |
396 | 396 | ||
397 | #define S_BCM1480_SCD_TRACE_CFG_MODE 16 | 397 | #define S_BCM1480_SCD_TRACE_CFG_MODE 16 |
398 | #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) | 398 | #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) |
399 | #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) | 399 | #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) |
400 | #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) | 400 | #define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) |
401 | 401 | ||
402 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 | 402 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 |
403 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 | 403 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 |
404 | #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 | 404 | #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 |
405 | 405 | ||
406 | #endif /* _BCM1480_SCD_H */ | 406 | #endif /* _BCM1480_SCD_H */ |