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Diffstat (limited to 'arch/mips/include/asm/r4kcache.h')
-rw-r--r--arch/mips/include/asm/r4kcache.h41
1 files changed, 30 insertions, 11 deletions
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index a0b2650516ac..34d1a1917125 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -15,6 +15,7 @@
15#include <asm/asm.h> 15#include <asm/asm.h>
16#include <asm/cacheops.h> 16#include <asm/cacheops.h>
17#include <asm/cpu-features.h> 17#include <asm/cpu-features.h>
18#include <asm/cpu-type.h>
18#include <asm/mipsmtregs.h> 19#include <asm/mipsmtregs.h>
19 20
20/* 21/*
@@ -162,7 +163,15 @@ static inline void flush_scache_line_indexed(unsigned long addr)
162static inline void flush_icache_line(unsigned long addr) 163static inline void flush_icache_line(unsigned long addr)
163{ 164{
164 __iflush_prologue 165 __iflush_prologue
165 cache_op(Hit_Invalidate_I, addr); 166 switch (boot_cpu_type()) {
167 case CPU_LOONGSON2:
168 cache_op(Hit_Invalidate_I_Loongson23, addr);
169 break;
170
171 default:
172 cache_op(Hit_Invalidate_I, addr);
173 break;
174 }
166 __iflush_epilogue 175 __iflush_epilogue
167} 176}
168 177
@@ -208,7 +217,15 @@ static inline void flush_scache_line(unsigned long addr)
208 */ 217 */
209static inline void protected_flush_icache_line(unsigned long addr) 218static inline void protected_flush_icache_line(unsigned long addr)
210{ 219{
211 protected_cache_op(Hit_Invalidate_I, addr); 220 switch (boot_cpu_type()) {
221 case CPU_LOONGSON2:
222 protected_cache_op(Hit_Invalidate_I_Loongson23, addr);
223 break;
224
225 default:
226 protected_cache_op(Hit_Invalidate_I, addr);
227 break;
228 }
212} 229}
213 230
214/* 231/*
@@ -412,8 +429,8 @@ __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64
412__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) 429__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
413 430
414/* build blast_xxx_range, protected_blast_xxx_range */ 431/* build blast_xxx_range, protected_blast_xxx_range */
415#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ 432#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
416static inline void prot##blast_##pfx##cache##_range(unsigned long start, \ 433static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
417 unsigned long end) \ 434 unsigned long end) \
418{ \ 435{ \
419 unsigned long lsize = cpu_##desc##_line_size(); \ 436 unsigned long lsize = cpu_##desc##_line_size(); \
@@ -432,13 +449,15 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
432 __##pfx##flush_epilogue \ 449 __##pfx##flush_epilogue \
433} 450}
434 451
435__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_) 452__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
436__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_) 453__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
437__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_) 454__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
438__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, ) 455__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson23, \
439__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, ) 456 protected_, loongson23_)
457__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
458__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
440/* blast_inv_dcache_range */ 459/* blast_inv_dcache_range */
441__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, ) 460__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
442__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, ) 461__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
443 462
444#endif /* _ASM_R4KCACHE_H */ 463#endif /* _ASM_R4KCACHE_H */