1 files changed, 18 insertions, 18 deletions
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index dedef7d2b01f..1e7dbb192657 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -16,7 +16,7 @@
 #define CP0_PRID_OCTEON_PASS1 0x000d0000
 #define CP0_PRID_OCTEON_CN30XX 0x000d0200
-.macro  kernel_entry_setup
+.macro  kernel_entry_setup
        # Registers set by bootloader:
        # (only 32 bits set by bootloader, all addresses are physical
        # addresses, and need to have the appropriate memory region set
@@ -28,12 +28,12 @@
        .set push
        .set arch=octeon
        # Read the cavium mem control register
-        dmfc0   v0, CP0_CVMMEMCTL_REG
+        dmfc0   v0, CP0_CVMMEMCTL_REG
        # Clear the lower 6 bits, the CVMSEG size
-        dins    v0, $0, 0, 6
+        dins    v0, $0, 0, 6
-        ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+        ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
-        dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
+        dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
-        dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
+        dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
 #ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
        # Disable unaligned load/store support but leave HW fixup enabled
        or  v0, v0, 0x5001
@@ -69,14 +69,14 @@ skip:
        and     v0, v0, v1
        ori     v0, v0, (6 << 7)
        # Write the cavium control register
-        dmtc0   v0, CP0_CVMCTL_REG
+        dmtc0   v0, CP0_CVMCTL_REG
        sync
        # Flush dcache after config change
-        cache   9, 0($0)
+        cache   9, 0($0)
        # Get my core id
-        rdhwr   v0, $0
+        rdhwr   v0, $0
        # Jump the master to kernel_entry
-        bne     a2, zero, octeon_main_processor
+        bne     a2, zero, octeon_main_processor
        nop
 #ifdef CONFIG_SMP
@@ -87,21 +87,21 @@ skip:
        #
        # This is the variable where the next core to boot os stored
-        PTR_LA  t0, octeon_processor_boot
+        PTR_LA  t0, octeon_processor_boot
 octeon_spin_wait_boot:
        # Get the core id of the next to be booted
-        LONG_L  t1, (t0)
+        LONG_L  t1, (t0)
        # Keep looping if it isn't me
        bne t1, v0, octeon_spin_wait_boot
        nop
        # Get my GP from the global variable
-        PTR_LA  t0, octeon_processor_gp
+        PTR_LA  t0, octeon_processor_gp
-        LONG_L  gp, (t0)
+        LONG_L  gp, (t0)
        # Get my SP from the global variable
-        PTR_LA  t0, octeon_processor_sp
+        PTR_LA  t0, octeon_processor_sp
-        LONG_L  sp, (t0)
+        LONG_L  sp, (t0)
        # Set the SP global variable to zero so the master knows we've started
-        LONG_S  zero, (t0)
+        LONG_S  zero, (t0)
 #ifdef __OCTEON__
        syncw
        syncw
@@ -130,7 +130,7 @@ octeon_main_processor:
 /*
 * Do SMP slave processor setup necessary before we can savely execute C code.
 */
-        .macro  smp_slave_setup
+        .macro  smp_slave_setup
        .endm
 #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */

diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index dedef7d2b01f..1e7dbb192657 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -16,7 +16,7 @@
16	#define CP0_PRID_OCTEON_PASS1 0x000d0000	16	#define CP0_PRID_OCTEON_PASS1 0x000d0000
17	#define CP0_PRID_OCTEON_CN30XX 0x000d0200	17	#define CP0_PRID_OCTEON_CN30XX 0x000d0200
18		18
19	.macro kernel_entry_setup	19	.macro kernel_entry_setup
20	# Registers set by bootloader:	20	# Registers set by bootloader:
21	# (only 32 bits set by bootloader, all addresses are physical	21	# (only 32 bits set by bootloader, all addresses are physical
22	# addresses, and need to have the appropriate memory region set	22	# addresses, and need to have the appropriate memory region set
@@ -28,12 +28,12 @@
28	.set push	28	.set push
29	.set arch=octeon	29	.set arch=octeon
30	# Read the cavium mem control register	30	# Read the cavium mem control register
31	dmfc0 v0, CP0_CVMMEMCTL_REG	31	dmfc0 v0, CP0_CVMMEMCTL_REG
32	# Clear the lower 6 bits, the CVMSEG size	32	# Clear the lower 6 bits, the CVMSEG size
33	dins v0, $0, 0, 6	33	dins v0, $0, 0, 6
34	ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE	34	ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35	dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register	35	dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36	dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register	36	dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37	#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED	37	#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
38	# Disable unaligned load/store support but leave HW fixup enabled	38	# Disable unaligned load/store support but leave HW fixup enabled
39	or v0, v0, 0x5001	39	or v0, v0, 0x5001
@@ -69,14 +69,14 @@ skip:
69	and v0, v0, v1	69	and v0, v0, v1
70	ori v0, v0, (6 << 7)	70	ori v0, v0, (6 << 7)
71	# Write the cavium control register	71	# Write the cavium control register
72	dmtc0 v0, CP0_CVMCTL_REG	72	dmtc0 v0, CP0_CVMCTL_REG
73	sync	73	sync
74	# Flush dcache after config change	74	# Flush dcache after config change
75	cache 9, 0($0)	75	cache 9, 0($0)
76	# Get my core id	76	# Get my core id
77	rdhwr v0, $0	77	rdhwr v0, $0
78	# Jump the master to kernel_entry	78	# Jump the master to kernel_entry
79	bne a2, zero, octeon_main_processor	79	bne a2, zero, octeon_main_processor
80	nop	80	nop
81		81
82	#ifdef CONFIG_SMP	82	#ifdef CONFIG_SMP
@@ -87,21 +87,21 @@ skip:
87	#	87	#
88		88
89	# This is the variable where the next core to boot os stored	89	# This is the variable where the next core to boot os stored
90	PTR_LA t0, octeon_processor_boot	90	PTR_LA t0, octeon_processor_boot
91	octeon_spin_wait_boot:	91	octeon_spin_wait_boot:
92	# Get the core id of the next to be booted	92	# Get the core id of the next to be booted
93	LONG_L t1, (t0)	93	LONG_L t1, (t0)
94	# Keep looping if it isn't me	94	# Keep looping if it isn't me
95	bne t1, v0, octeon_spin_wait_boot	95	bne t1, v0, octeon_spin_wait_boot
96	nop	96	nop
97	# Get my GP from the global variable	97	# Get my GP from the global variable
98	PTR_LA t0, octeon_processor_gp	98	PTR_LA t0, octeon_processor_gp
99	LONG_L gp, (t0)	99	LONG_L gp, (t0)
100	# Get my SP from the global variable	100	# Get my SP from the global variable
101	PTR_LA t0, octeon_processor_sp	101	PTR_LA t0, octeon_processor_sp
102	LONG_L sp, (t0)	102	LONG_L sp, (t0)
103	# Set the SP global variable to zero so the master knows we've started	103	# Set the SP global variable to zero so the master knows we've started
104	LONG_S zero, (t0)	104	LONG_S zero, (t0)
105	#ifdef __OCTEON__	105	#ifdef __OCTEON__
106	syncw	106	syncw
107	syncw	107	syncw
@@ -130,7 +130,7 @@ octeon_main_processor:
130	/*	130	/*
131	* Do SMP slave processor setup necessary before we can savely execute C code.	131	* Do SMP slave processor setup necessary before we can savely execute C code.
132	*/	132	*/
133	.macro smp_slave_setup	133	.macro smp_slave_setup
134	.endm	134	.endm
135		135
136	#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */	136	#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */