aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm/mach-ar7/ar7.h
diff options
context:
space:
mode:
Diffstat (limited to 'arch/mips/include/asm/mach-ar7/ar7.h')
-rw-r--r--arch/mips/include/asm/mach-ar7/ar7.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 07d3fadb2443..a47ea0c85248 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -40,9 +40,9 @@
40#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) 40#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
41#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) 41#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
42#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C) 42#define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
43#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) 43#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
44#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) 44#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
45#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) 45#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
46#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) 46#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
47#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) 47#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
48#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) 48#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
@@ -52,7 +52,7 @@
52#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 52#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
53 53
54/* Titan registers */ 54/* Titan registers */
55#define TITAN_REGS_ESWITCH_BASE (0x08640000) 55#define TITAN_REGS_ESWITCH_BASE (0x08640000)
56#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE) 56#define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE)
57#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) 57#define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800)
58#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) 58#define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000)
@@ -72,9 +72,9 @@
72 72
73/* GPIO control registers */ 73/* GPIO control registers */
74#define AR7_GPIO_INPUT 0x0 74#define AR7_GPIO_INPUT 0x0
75#define AR7_GPIO_OUTPUT 0x4 75#define AR7_GPIO_OUTPUT 0x4
76#define AR7_GPIO_DIR 0x8 76#define AR7_GPIO_DIR 0x8
77#define AR7_GPIO_ENABLE 0xc 77#define AR7_GPIO_ENABLE 0xc
78#define TITAN_GPIO_INPUT_0 0x0 78#define TITAN_GPIO_INPUT_0 0x0
79#define TITAN_GPIO_INPUT_1 0x4 79#define TITAN_GPIO_INPUT_1 0x4
80#define TITAN_GPIO_OUTPUT_0 0x8 80#define TITAN_GPIO_OUTPUT_0 0x8
@@ -88,10 +88,10 @@
88#define AR7_CHIP_7200 0x2b 88#define AR7_CHIP_7200 0x2b
89#define AR7_CHIP_7300 0x05 89#define AR7_CHIP_7300 0x05
90#define AR7_CHIP_TITAN 0x07 90#define AR7_CHIP_TITAN 0x07
91#define TITAN_CHIP_1050 0x0f 91#define TITAN_CHIP_1050 0x0f
92#define TITAN_CHIP_1055 0x0e 92#define TITAN_CHIP_1055 0x0e
93#define TITAN_CHIP_1056 0x0d 93#define TITAN_CHIP_1056 0x0d
94#define TITAN_CHIP_1060 0x07 94#define TITAN_CHIP_1060 0x07
95 95
96/* Interrupts */ 96/* Interrupts */
97#define AR7_IRQ_UART0 15 97#define AR7_IRQ_UART0 15