1 files changed, 0 insertions, 25 deletions

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index b4c20e4f87cd..f0324e92d089 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -161,31 +161,6 @@ ASMMACRO(back_to_back_c0_hazard,
         )
 #define instruction_hazard() do { } while (0)
 
-#elif defined(CONFIG_CPU_RM9000)
-
-/*
- * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-
-ASMMACRO(mtc0_tlbw_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(tlbw_use_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(tlb_probe_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(irq_enable_hazard,
-        )
-ASMMACRO(irq_disable_hazard,
-        )
-ASMMACRO(back_to_back_c0_hazard,
-        )
-#define instruction_hazard() do { } while (0)
-
 #elif defined(CONFIG_CPU_SB1)
 
 /*