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-rw-r--r--arch/m68k/include/asm/m5249sim.h269
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diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
deleted file mode 100644
index fdf45e6807c9..000000000000
--- a/arch/m68k/include/asm/m5249sim.h
+++ /dev/null
@@ -1,269 +0,0 @@
1/****************************************************************************/
2
3/*
4 * m5249sim.h -- ColdFire 5249 System Integration Module support.
5 *
6 * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m5249sim_h
11#define m5249sim_h
12/****************************************************************************/
13
14#define CPU_NAME "COLDFIRE(m5249)"
15#define CPU_INSTR_PER_JIFFY 3
16#define MCF_BUSCLK (MCF_CLK / 2)
17
18#include <asm/m52xxacr.h>
19
20/*
21 * The 5249 has a second MBAR region, define its address.
22 */
23#define MCF_MBAR2 0x80000000
24
25/*
26 * Define the 5249 SIM register set addresses.
27 */
28#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
29#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
30#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
31#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
32#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
33#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
34#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
36#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
37#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
38#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
39#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
40#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
41#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
42#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
43#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
44#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
45#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
46#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
47#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
48#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
49#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
50
51#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
57#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
58#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
59#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
60#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
61#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
62#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
63
64#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
65#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
66#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM 0 Mask */
67#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
68#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM 1 Mask */
69
70/*
71 * Timer module.
72 */
73#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */
74#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */
75
76/*
77 * UART module.
78 */
79#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */
80#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */
81
82/*
83 * QSPI module.
84 */
85#define MCFQSPI_BASE (MCF_MBAR + 0x300) /* Base address QSPI */
86#define MCFQSPI_SIZE 0x40 /* Register set size */
87
88#define MCFQSPI_CS0 29
89#define MCFQSPI_CS1 24
90#define MCFQSPI_CS2 21
91#define MCFQSPI_CS3 22
92
93/*
94 * DMA unit base addresses.
95 */
96#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */
97#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */
98#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */
99#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */
100
101/*
102 * Some symbol defines for the above...
103 */
104#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
105#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
106#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
107#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
108#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
109#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
110#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
111#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
112#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
113#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
114
115/*
116 * Define system peripheral IRQ usage.
117 */
118#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
119#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
120#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
121
122#define MCF_IRQ_UART0 73 /* UART0 */
123#define MCF_IRQ_UART1 74 /* UART1 */
124
125/*
126 * General purpose IO registers (in MBAR2).
127 */
128#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
129#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
130#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
131#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
132#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
133#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
134#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
135#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
136
137#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
138#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
139#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
140
141#define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
142#define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
143#define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
144#define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
145#define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
146#define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
147#define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
148#define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
149
150#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
151
152#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
153#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
154
155/*
156 * Define the base interrupt for the second interrupt controller.
157 * We set it to 128, out of the way of the base interrupts, and plenty
158 * of room for its 64 interrupts.
159 */
160#define MCFINTC2_VECBASE 128
161
162#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
163#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
164#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
165#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
166#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
167#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
168#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
169#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
170
171/*
172 * Generic GPIO support
173 */
174#define MCFGPIO_PIN_MAX 64
175#define MCFGPIO_IRQ_MAX -1
176#define MCFGPIO_IRQ_VECBASE -1
177
178/****************************************************************************/
179
180#ifdef __ASSEMBLER__
181
182/*
183 * The M5249C3 board needs a little help getting all its SIM devices
184 * initialized at kernel start time. dBUG doesn't set much up, so
185 * we need to do it manually.
186 */
187.macro m5249c3_setup
188 /*
189 * Set MBAR1 and MBAR2, just incase they are not set.
190 */
191 movel #0x10000001,%a0
192 movec %a0,%MBAR /* map MBAR region */
193 subql #1,%a0 /* get MBAR address in a0 */
194
195 movel #0x80000001,%a1
196 movec %a1,#3086 /* map MBAR2 region */
197 subql #1,%a1 /* get MBAR2 address in a1 */
198
199 /*
200 * Move secondary interrupts to their base (128).
201 */
202 moveb #MCFINTC2_VECBASE,%d0
203 moveb %d0,0x16b(%a1) /* interrupt base register */
204
205 /*
206 * Work around broken CSMR0/DRAM vector problem.
207 */
208 movel #0x001F0021,%d0 /* disable C/I bit */
209 movel %d0,0x84(%a0) /* set CSMR0 */
210
211 /*
212 * Disable the PLL firstly. (Who knows what state it is
213 * in here!).
214 */
215 movel 0x180(%a1),%d0 /* get current PLL value */
216 andl #0xfffffffe,%d0 /* PLL bypass first */
217 movel %d0,0x180(%a1) /* set PLL register */
218 nop
219
220#if CONFIG_CLOCK_FREQ == 140000000
221 /*
222 * Set initial clock frequency. This assumes M5249C3 board
223 * is fitted with 11.2896MHz crystal. It will program the
224 * PLL for 140MHz. Lets go fast :-)
225 */
226 movel #0x125a40f0,%d0 /* set for 140MHz */
227 movel %d0,0x180(%a1) /* set PLL register */
228 orl #0x1,%d0
229 movel %d0,0x180(%a1) /* set PLL register */
230#endif
231
232 /*
233 * Setup CS1 for ethernet controller.
234 * (Setup as per M5249C3 doco).
235 */
236 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */
237 movel %d0,0x8c(%a0)
238 movel #0x001f0021,%d0 /* CS1 size of 1Mb */
239 movel %d0,0x90(%a0)
240 movew #0x0080,%d0 /* CS1 = 16bit port, AA */
241 movew %d0,0x96(%a0)
242
243 /*
244 * Setup CS2 for IDE interface.
245 */
246 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */
247 movel %d0,0x98(%a0)
248 movel #0x001f0001,%d0 /* CS2 size of 1MB */
249 movel %d0,0x9c(%a0)
250 movew #0x0080,%d0 /* CS2 = 16bit, TA */
251 movew %d0,0xa2(%a0)
252
253 movel #0x00107000,%d0 /* IDEconfig1 */
254 movel %d0,0x18c(%a1)
255 movel #0x000c0400,%d0 /* IDEconfig2 */
256 movel %d0,0x190(%a1)
257
258 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */
259 orl %d0,0xc(%a1) /* function GPIO19 */
260 orl %d0,0x8(%a1) /* enable GPIO19 as output */
261 orl %d0,0x4(%a1) /* de-assert IDE reset */
262.endm
263
264#define PLATFORM_SETUP m5249c3_setup
265
266#endif /* __ASSEMBLER__ */
267
268/****************************************************************************/
269#endif /* m5249sim_h */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 22:30:21 -0500