diff options
Diffstat (limited to 'arch/arm')
40 files changed, 220 insertions, 195 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index ecfcdba2d17c..9b31f4311ea2 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -495,6 +495,7 @@ config DEBUG_IMX_UART_PORT | |||
495 | DEBUG_IMX53_UART || \ | 495 | DEBUG_IMX53_UART || \ |
496 | DEBUG_IMX6Q_UART | 496 | DEBUG_IMX6Q_UART |
497 | default 1 | 497 | default 1 |
498 | depends on ARCH_MXC | ||
498 | help | 499 | help |
499 | Choose UART port on which kernel low-level debug messages | 500 | Choose UART port on which kernel low-level debug messages |
500 | should be output. | 501 | should be output. |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 48d00a099ce3..3d3f64d2111a 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -385,7 +385,7 @@ | |||
385 | 385 | ||
386 | spi@7000d800 { | 386 | spi@7000d800 { |
387 | compatible = "nvidia,tegra20-slink"; | 387 | compatible = "nvidia,tegra20-slink"; |
388 | reg = <0x7000d480 0x200>; | 388 | reg = <0x7000d800 0x200>; |
389 | interrupts = <0 83 0x04>; | 389 | interrupts = <0 83 0x04>; |
390 | nvidia,dma-request-selector = <&apbdma 17>; | 390 | nvidia,dma-request-selector = <&apbdma 17>; |
391 | #address-cells = <1>; | 391 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9d87a3ffe998..dbf46c272562 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
@@ -372,7 +372,7 @@ | |||
372 | 372 | ||
373 | spi@7000d800 { | 373 | spi@7000d800 { |
374 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | 374 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; |
375 | reg = <0x7000d480 0x200>; | 375 | reg = <0x7000d800 0x200>; |
376 | interrupts = <0 83 0x04>; | 376 | interrupts = <0 83 0x04>; |
377 | nvidia,dma-request-selector = <&apbdma 17>; | 377 | nvidia,dma-request-selector = <&apbdma 17>; |
378 | #address-cells = <1>; | 378 | #address-cells = <1>; |
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0f82098c9bfe..cd22d821bf74 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
@@ -562,21 +562,21 @@ ENDPROC(__und_usr) | |||
562 | @ Fall-through from Thumb-2 __und_usr | 562 | @ Fall-through from Thumb-2 __und_usr |
563 | @ | 563 | @ |
564 | #ifdef CONFIG_NEON | 564 | #ifdef CONFIG_NEON |
565 | get_thread_info r10 @ get current thread | ||
565 | adr r6, .LCneon_thumb_opcodes | 566 | adr r6, .LCneon_thumb_opcodes |
566 | b 2f | 567 | b 2f |
567 | #endif | 568 | #endif |
568 | call_fpe: | 569 | call_fpe: |
570 | get_thread_info r10 @ get current thread | ||
569 | #ifdef CONFIG_NEON | 571 | #ifdef CONFIG_NEON |
570 | adr r6, .LCneon_arm_opcodes | 572 | adr r6, .LCneon_arm_opcodes |
571 | 2: | 573 | 2: ldr r5, [r6], #4 @ mask value |
572 | ldr r7, [r6], #4 @ mask value | ||
573 | cmp r7, #0 @ end mask? | ||
574 | beq 1f | ||
575 | and r8, r0, r7 | ||
576 | ldr r7, [r6], #4 @ opcode bits matching in mask | 574 | ldr r7, [r6], #4 @ opcode bits matching in mask |
575 | cmp r5, #0 @ end mask? | ||
576 | beq 1f | ||
577 | and r8, r0, r5 | ||
577 | cmp r8, r7 @ NEON instruction? | 578 | cmp r8, r7 @ NEON instruction? |
578 | bne 2b | 579 | bne 2b |
579 | get_thread_info r10 | ||
580 | mov r7, #1 | 580 | mov r7, #1 |
581 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | 581 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used |
582 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | 582 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used |
@@ -586,7 +586,6 @@ call_fpe: | |||
586 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 | 586 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
587 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 | 587 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
588 | moveq pc, lr | 588 | moveq pc, lr |
589 | get_thread_info r10 @ get current thread | ||
590 | and r8, r0, #0x00000f00 @ mask out CP number | 589 | and r8, r0, #0x00000f00 @ mask out CP number |
591 | THUMB( lsr r8, r8, #8 ) | 590 | THUMB( lsr r8, r8, #8 ) |
592 | mov r7, #1 | 591 | mov r7, #1 |
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 047d3e40e470..cbd0f51937cc 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c | |||
@@ -459,15 +459,16 @@ unsigned long arch_randomize_brk(struct mm_struct *mm) | |||
459 | * atomic helpers and the signal restart code. Insert it into the | 459 | * atomic helpers and the signal restart code. Insert it into the |
460 | * gate_vma so that it is visible through ptrace and /proc/<pid>/mem. | 460 | * gate_vma so that it is visible through ptrace and /proc/<pid>/mem. |
461 | */ | 461 | */ |
462 | static struct vm_area_struct gate_vma; | 462 | static struct vm_area_struct gate_vma = { |
463 | .vm_start = 0xffff0000, | ||
464 | .vm_end = 0xffff0000 + PAGE_SIZE, | ||
465 | .vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC, | ||
466 | .vm_mm = &init_mm, | ||
467 | }; | ||
463 | 468 | ||
464 | static int __init gate_vma_init(void) | 469 | static int __init gate_vma_init(void) |
465 | { | 470 | { |
466 | gate_vma.vm_start = 0xffff0000; | 471 | gate_vma.vm_page_prot = PAGE_READONLY_EXEC; |
467 | gate_vma.vm_end = 0xffff0000 + PAGE_SIZE; | ||
468 | gate_vma.vm_page_prot = PAGE_READONLY_EXEC; | ||
469 | gate_vma.vm_flags = VM_READ | VM_EXEC | | ||
470 | VM_MAYREAD | VM_MAYEXEC; | ||
471 | return 0; | 472 | return 0; |
472 | } | 473 | } |
473 | arch_initcall(gate_vma_init); | 474 | arch_initcall(gate_vma_init); |
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index ea961445e0e9..b23c8e4f28e8 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c | |||
@@ -536,16 +536,14 @@ static void __init ap_init_of(void) | |||
536 | 'A' + (ap_sc_id & 0x0f)); | 536 | 'A' + (ap_sc_id & 0x0f)); |
537 | 537 | ||
538 | soc_dev = soc_device_register(soc_dev_attr); | 538 | soc_dev = soc_device_register(soc_dev_attr); |
539 | if (IS_ERR_OR_NULL(soc_dev)) { | 539 | if (IS_ERR(soc_dev)) { |
540 | kfree(soc_dev_attr->revision); | 540 | kfree(soc_dev_attr->revision); |
541 | kfree(soc_dev_attr); | 541 | kfree(soc_dev_attr); |
542 | return; | 542 | return; |
543 | } | 543 | } |
544 | 544 | ||
545 | parent = soc_device_to_device(soc_dev); | 545 | parent = soc_device_to_device(soc_dev); |
546 | 546 | integrator_init_sysfs(parent, ap_sc_id); | |
547 | if (!IS_ERR_OR_NULL(parent)) | ||
548 | integrator_init_sysfs(parent, ap_sc_id); | ||
549 | 547 | ||
550 | of_platform_populate(root, of_default_bus_match_table, | 548 | of_platform_populate(root, of_default_bus_match_table, |
551 | ap_auxdata_lookup, parent); | 549 | ap_auxdata_lookup, parent); |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 2b0db82a5381..da1091be0887 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -360,17 +360,14 @@ static void __init intcp_init_of(void) | |||
360 | 'A' + (intcp_sc_id & 0x0f)); | 360 | 'A' + (intcp_sc_id & 0x0f)); |
361 | 361 | ||
362 | soc_dev = soc_device_register(soc_dev_attr); | 362 | soc_dev = soc_device_register(soc_dev_attr); |
363 | if (IS_ERR_OR_NULL(soc_dev)) { | 363 | if (IS_ERR(soc_dev)) { |
364 | kfree(soc_dev_attr->revision); | 364 | kfree(soc_dev_attr->revision); |
365 | kfree(soc_dev_attr); | 365 | kfree(soc_dev_attr); |
366 | return; | 366 | return; |
367 | } | 367 | } |
368 | 368 | ||
369 | parent = soc_device_to_device(soc_dev); | 369 | parent = soc_device_to_device(soc_dev); |
370 | 370 | integrator_init_sysfs(parent, intcp_sc_id); | |
371 | if (!IS_ERR_OR_NULL(parent)) | ||
372 | integrator_init_sysfs(parent, intcp_sc_id); | ||
373 | |||
374 | of_platform_populate(root, of_default_bus_match_table, | 371 | of_platform_populate(root, of_default_bus_match_table, |
375 | intcp_auxdata_lookup, parent); | 372 | intcp_auxdata_lookup, parent); |
376 | } | 373 | } |
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 3218f1f2c0e0..e7b781d3788f 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
@@ -41,8 +41,6 @@ static struct fb_videomode mx23evk_video_modes[] = { | |||
41 | .lower_margin = 4, | 41 | .lower_margin = 4, |
42 | .hsync_len = 1, | 42 | .hsync_len = 1, |
43 | .vsync_len = 1, | 43 | .vsync_len = 1, |
44 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
45 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
46 | }, | 44 | }, |
47 | }; | 45 | }; |
48 | 46 | ||
@@ -59,8 +57,6 @@ static struct fb_videomode mx28evk_video_modes[] = { | |||
59 | .lower_margin = 10, | 57 | .lower_margin = 10, |
60 | .hsync_len = 10, | 58 | .hsync_len = 10, |
61 | .vsync_len = 10, | 59 | .vsync_len = 10, |
62 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
63 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
64 | }, | 60 | }, |
65 | }; | 61 | }; |
66 | 62 | ||
@@ -77,7 +73,6 @@ static struct fb_videomode m28evk_video_modes[] = { | |||
77 | .lower_margin = 45, | 73 | .lower_margin = 45, |
78 | .hsync_len = 1, | 74 | .hsync_len = 1, |
79 | .vsync_len = 1, | 75 | .vsync_len = 1, |
80 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, | ||
81 | }, | 76 | }, |
82 | }; | 77 | }; |
83 | 78 | ||
@@ -94,9 +89,7 @@ static struct fb_videomode apx4devkit_video_modes[] = { | |||
94 | .lower_margin = 13, | 89 | .lower_margin = 13, |
95 | .hsync_len = 48, | 90 | .hsync_len = 48, |
96 | .vsync_len = 3, | 91 | .vsync_len = 3, |
97 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | | 92 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
98 | FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
99 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
100 | }, | 93 | }, |
101 | }; | 94 | }; |
102 | 95 | ||
@@ -113,9 +106,7 @@ static struct fb_videomode apf28dev_video_modes[] = { | |||
113 | .lower_margin = 0x15, | 106 | .lower_margin = 0x15, |
114 | .hsync_len = 64, | 107 | .hsync_len = 64, |
115 | .vsync_len = 4, | 108 | .vsync_len = 4, |
116 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | | 109 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
117 | FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
118 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
119 | }, | 110 | }, |
120 | }; | 111 | }; |
121 | 112 | ||
@@ -132,7 +123,6 @@ static struct fb_videomode cfa10049_video_modes[] = { | |||
132 | .lower_margin = 2, | 123 | .lower_margin = 2, |
133 | .hsync_len = 15, | 124 | .hsync_len = 15, |
134 | .vsync_len = 15, | 125 | .vsync_len = 15, |
135 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | ||
136 | }, | 126 | }, |
137 | }; | 127 | }; |
138 | 128 | ||
@@ -259,6 +249,8 @@ static void __init imx23_evk_init(void) | |||
259 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); | 249 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); |
260 | mxsfb_pdata.default_bpp = 32; | 250 | mxsfb_pdata.default_bpp = 32; |
261 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 251 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
252 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
253 | MXSFB_SYNC_DOTCLK_FAILING_ACT; | ||
262 | } | 254 | } |
263 | 255 | ||
264 | static inline void enable_clk_enet_out(void) | 256 | static inline void enable_clk_enet_out(void) |
@@ -278,6 +270,8 @@ static void __init imx28_evk_init(void) | |||
278 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); | 270 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); |
279 | mxsfb_pdata.default_bpp = 32; | 271 | mxsfb_pdata.default_bpp = 32; |
280 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 272 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
273 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
274 | MXSFB_SYNC_DOTCLK_FAILING_ACT; | ||
281 | 275 | ||
282 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); | 276 | mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0); |
283 | } | 277 | } |
@@ -297,6 +291,7 @@ static void __init m28evk_init(void) | |||
297 | mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); | 291 | mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); |
298 | mxsfb_pdata.default_bpp = 16; | 292 | mxsfb_pdata.default_bpp = 16; |
299 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; | 293 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; |
294 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; | ||
300 | } | 295 | } |
301 | 296 | ||
302 | static void __init sc_sps1_init(void) | 297 | static void __init sc_sps1_init(void) |
@@ -322,6 +317,8 @@ static void __init apx4devkit_init(void) | |||
322 | mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); | 317 | mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); |
323 | mxsfb_pdata.default_bpp = 32; | 318 | mxsfb_pdata.default_bpp = 32; |
324 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | 319 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; |
320 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
321 | MXSFB_SYNC_DOTCLK_FAILING_ACT; | ||
325 | } | 322 | } |
326 | 323 | ||
327 | #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) | 324 | #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0) |
@@ -407,6 +404,7 @@ static void __init cfa10049_init(void) | |||
407 | mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes); | 404 | mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes); |
408 | mxsfb_pdata.default_bpp = 32; | 405 | mxsfb_pdata.default_bpp = 32; |
409 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; | 406 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; |
407 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT; | ||
410 | } | 408 | } |
411 | 409 | ||
412 | static void __init cfa10037_init(void) | 410 | static void __init cfa10037_init(void) |
@@ -423,6 +421,8 @@ static void __init apf28_init(void) | |||
423 | mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes); | 421 | mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes); |
424 | mxsfb_pdata.default_bpp = 16; | 422 | mxsfb_pdata.default_bpp = 16; |
425 | mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT; | 423 | mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT; |
424 | mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
425 | MXSFB_SYNC_DOTCLK_FAILING_ACT; | ||
426 | } | 426 | } |
427 | 427 | ||
428 | static void __init mxs_machine_init(void) | 428 | static void __init mxs_machine_init(void) |
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 903da8eb886c..cdd05f2e67ee 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig | |||
@@ -55,12 +55,6 @@ config MACH_OMAP_H3 | |||
55 | TI OMAP 1710 H3 board support. Say Y here if you have such | 55 | TI OMAP 1710 H3 board support. Say Y here if you have such |
56 | a board. | 56 | a board. |
57 | 57 | ||
58 | config MACH_OMAP_HTCWIZARD | ||
59 | bool "HTC Wizard" | ||
60 | depends on ARCH_OMAP850 | ||
61 | help | ||
62 | HTC Wizard smartphone support (AKA QTEK 9100, ...) | ||
63 | |||
64 | config MACH_HERALD | 58 | config MACH_HERALD |
65 | bool "HTC Herald" | 59 | bool "HTC Herald" |
66 | depends on ARCH_OMAP850 | 60 | depends on ARCH_OMAP850 |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 8111cd9ff3e5..b9c0ed3f648c 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -408,7 +408,7 @@ config OMAP3_SDRC_AC_TIMING | |||
408 | 408 | ||
409 | config OMAP4_ERRATA_I688 | 409 | config OMAP4_ERRATA_I688 |
410 | bool "OMAP4 errata: Async Bridge Corruption" | 410 | bool "OMAP4 errata: Async Bridge Corruption" |
411 | depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM | 411 | depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM |
412 | select ARCH_HAS_BARRIERS | 412 | select ARCH_HAS_BARRIERS |
413 | help | 413 | help |
414 | If a data is stalled inside asynchronous bridge because of back | 414 | If a data is stalled inside asynchronous bridge because of back |
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index a3e0aaa4886b..cb0596b631cf 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
@@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void) | |||
166 | omap_display_init(&sdp2430_dss_data); | 166 | omap_display_init(&sdp2430_dss_data); |
167 | } | 167 | } |
168 | 168 | ||
169 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) | 169 | #if IS_ENABLED(CONFIG_SMC91X) |
170 | 170 | ||
171 | static struct omap_smc91x_platform_data board_smc91x_data = { | 171 | static struct omap_smc91x_platform_data board_smc91x_data = { |
172 | .cs = 5, | 172 | .cs = 5, |
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c index 6920f6cfc97c..4eb5e6f2f7f5 100644 --- a/arch/arm/mach-omap2/board-cm-t3517.c +++ b/arch/arm/mach-omap2/board-cm-t3517.c | |||
@@ -332,6 +332,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517") | |||
332 | .handle_irq = omap3_intc_handle_irq, | 332 | .handle_irq = omap3_intc_handle_irq, |
333 | .init_machine = cm_t3517_init, | 333 | .init_machine = cm_t3517_init, |
334 | .init_late = am35xx_init_late, | 334 | .init_late = am35xx_init_late, |
335 | .init_time = omap3_gp_gptimer_timer_init, | 335 | .init_time = omap3_gptimer_timer_init, |
336 | .restart = omap3xxx_restart, | 336 | .restart = omap3xxx_restart, |
337 | MACHINE_END | 337 | MACHINE_END |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index e54a48060198..78813b397209 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
@@ -140,7 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") | |||
140 | .init_irq = omap_intc_of_init, | 140 | .init_irq = omap_intc_of_init, |
141 | .handle_irq = omap3_intc_handle_irq, | 141 | .handle_irq = omap3_intc_handle_irq, |
142 | .init_machine = omap_generic_init, | 142 | .init_machine = omap_generic_init, |
143 | .init_time = omap3_am33xx_gptimer_timer_init, | 143 | .init_time = omap3_gptimer_timer_init, |
144 | .dt_compat = am33xx_boards_compat, | 144 | .dt_compat = am33xx_boards_compat, |
145 | .restart = am33xx_restart, | 145 | .restart = am33xx_restart, |
146 | MACHINE_END | 146 | MACHINE_END |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 812c829fa46f..5b4ec51c385f 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
@@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void) | |||
246 | return 0; | 246 | return 0; |
247 | } | 247 | } |
248 | 248 | ||
249 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE) | 249 | #if IS_ENABLED(CONFIG_SMC91X) |
250 | 250 | ||
251 | static struct omap_smc91x_platform_data board_smc91x_data = { | 251 | static struct omap_smc91x_platform_data board_smc91x_data = { |
252 | .cs = 1, | 252 | .cs = 1, |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 5382215a49bc..6955a428f534 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
@@ -489,7 +489,7 @@ static int __init beagle_opp_init(void) | |||
489 | 489 | ||
490 | /* Initialize the omap3 opp table if not already created. */ | 490 | /* Initialize the omap3 opp table if not already created. */ |
491 | r = omap3_opp_init(); | 491 | r = omap3_opp_init(); |
492 | if (IS_ERR_VALUE(r) && (r != -EEXIST)) { | 492 | if (r < 0 && (r != -EEXIST)) { |
493 | pr_err("%s: opp default init failed\n", __func__); | 493 | pr_err("%s: opp default init failed\n", __func__); |
494 | return r; | 494 | return r; |
495 | } | 495 | } |
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index 476b82066cb6..7f091c85384e 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c | |||
@@ -958,6 +958,14 @@ int __init am33xx_clk_init(void) | |||
958 | 958 | ||
959 | clk_set_parent(&timer3_fck, &sys_clkin_ck); | 959 | clk_set_parent(&timer3_fck, &sys_clkin_ck); |
960 | clk_set_parent(&timer6_fck, &sys_clkin_ck); | 960 | clk_set_parent(&timer6_fck, &sys_clkin_ck); |
961 | /* | ||
962 | * The On-Chip 32K RC Osc clock is not an accurate clock-source as per | ||
963 | * the design/spec, so as a result, for example, timer which supposed | ||
964 | * to get expired @60Sec, but will expire somewhere ~@40Sec, which is | ||
965 | * not expected by any use-case, so change WDT1 clock source to PRCM | ||
966 | * 32KHz clock. | ||
967 | */ | ||
968 | clk_set_parent(&wdt1_fck, &clkdiv32k_ick); | ||
961 | 969 | ||
962 | return 0; | 970 | return 0; |
963 | } | 971 | } |
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e4ec3a69ee2e..2191f25ad21b 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -596,7 +596,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) | |||
596 | return -ENOENT; | 596 | return -ENOENT; |
597 | 597 | ||
598 | r = clk_set_rate(mpurate_ck, mpurate); | 598 | r = clk_set_rate(mpurate_ck, mpurate); |
599 | if (IS_ERR_VALUE(r)) { | 599 | if (r < 0) { |
600 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", | 600 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", |
601 | mpurate_ck_name, mpurate, r); | 601 | mpurate_ck_name, mpurate, r); |
602 | clk_put(mpurate_ck); | 602 | clk_put(mpurate_ck); |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 40f4a03d728f..bf70e2b57ff8 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
@@ -82,8 +82,7 @@ extern void omap2_init_common_infrastructure(void); | |||
82 | extern void omap2_sync32k_timer_init(void); | 82 | extern void omap2_sync32k_timer_init(void); |
83 | extern void omap3_sync32k_timer_init(void); | 83 | extern void omap3_sync32k_timer_init(void); |
84 | extern void omap3_secure_sync32k_timer_init(void); | 84 | extern void omap3_secure_sync32k_timer_init(void); |
85 | extern void omap3_gp_gptimer_timer_init(void); | 85 | extern void omap3_gptimer_timer_init(void); |
86 | extern void omap3_am33xx_gptimer_timer_init(void); | ||
87 | extern void omap4_local_timer_init(void); | 86 | extern void omap4_local_timer_init(void); |
88 | extern void omap5_realtime_timer_init(void); | 87 | extern void omap5_realtime_timer_init(void); |
89 | 88 | ||
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 3aed4b0b9563..3a0296cfcace 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
@@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) | |||
307 | _omap3_noncore_dpll_bypass(clk); | 307 | _omap3_noncore_dpll_bypass(clk); |
308 | 308 | ||
309 | /* | 309 | /* |
310 | * Set jitter correction. No jitter correction for OMAP4 and 3630 | 310 | * Set jitter correction. Jitter correction applicable for OMAP343X |
311 | * since freqsel field is no longer present | 311 | * only since freqsel field is no longer present on other devices. |
312 | */ | 312 | */ |
313 | if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) { | 313 | if (cpu_is_omap343x()) { |
314 | v = __raw_readl(dd->control_reg); | 314 | v = __raw_readl(dd->control_reg); |
315 | v &= ~dd->freqsel_mask; | 315 | v &= ~dd->freqsel_mask; |
316 | v |= freqsel << __ffs(dd->freqsel_mask); | 316 | v |= freqsel << __ffs(dd->freqsel_mask); |
@@ -480,29 +480,30 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |||
480 | if (!dd) | 480 | if (!dd) |
481 | return -EINVAL; | 481 | return -EINVAL; |
482 | 482 | ||
483 | __clk_prepare(dd->clk_bypass); | ||
484 | clk_enable(dd->clk_bypass); | ||
485 | __clk_prepare(dd->clk_ref); | ||
486 | clk_enable(dd->clk_ref); | ||
487 | |||
488 | if (__clk_get_rate(dd->clk_bypass) == rate && | 483 | if (__clk_get_rate(dd->clk_bypass) == rate && |
489 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | 484 | (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) { |
490 | pr_debug("%s: %s: set rate: entering bypass.\n", | 485 | pr_debug("%s: %s: set rate: entering bypass.\n", |
491 | __func__, __clk_get_name(hw->clk)); | 486 | __func__, __clk_get_name(hw->clk)); |
492 | 487 | ||
488 | __clk_prepare(dd->clk_bypass); | ||
489 | clk_enable(dd->clk_bypass); | ||
493 | ret = _omap3_noncore_dpll_bypass(clk); | 490 | ret = _omap3_noncore_dpll_bypass(clk); |
494 | if (!ret) | 491 | if (!ret) |
495 | new_parent = dd->clk_bypass; | 492 | new_parent = dd->clk_bypass; |
493 | clk_disable(dd->clk_bypass); | ||
494 | __clk_unprepare(dd->clk_bypass); | ||
496 | } else { | 495 | } else { |
496 | __clk_prepare(dd->clk_ref); | ||
497 | clk_enable(dd->clk_ref); | ||
498 | |||
497 | if (dd->last_rounded_rate != rate) | 499 | if (dd->last_rounded_rate != rate) |
498 | rate = __clk_round_rate(hw->clk, rate); | 500 | rate = __clk_round_rate(hw->clk, rate); |
499 | 501 | ||
500 | if (dd->last_rounded_rate == 0) | 502 | if (dd->last_rounded_rate == 0) |
501 | return -EINVAL; | 503 | return -EINVAL; |
502 | 504 | ||
503 | /* No freqsel on AM335x, OMAP4 and OMAP3630 */ | 505 | /* Freqsel is available only on OMAP343X devices */ |
504 | if (!soc_is_am33xx() && !cpu_is_omap44xx() && | 506 | if (cpu_is_omap343x()) { |
505 | !cpu_is_omap3630()) { | ||
506 | freqsel = _omap3_dpll_compute_freqsel(clk, | 507 | freqsel = _omap3_dpll_compute_freqsel(clk, |
507 | dd->last_rounded_n); | 508 | dd->last_rounded_n); |
508 | WARN_ON(!freqsel); | 509 | WARN_ON(!freqsel); |
@@ -514,6 +515,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |||
514 | ret = omap3_noncore_dpll_program(clk, freqsel); | 515 | ret = omap3_noncore_dpll_program(clk, freqsel); |
515 | if (!ret) | 516 | if (!ret) |
516 | new_parent = dd->clk_ref; | 517 | new_parent = dd->clk_ref; |
518 | clk_disable(dd->clk_ref); | ||
519 | __clk_unprepare(dd->clk_ref); | ||
517 | } | 520 | } |
518 | /* | 521 | /* |
519 | * FIXME - this is all wrong. common code handles reparenting and | 522 | * FIXME - this is all wrong. common code handles reparenting and |
@@ -525,11 +528,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |||
525 | if (!ret) | 528 | if (!ret) |
526 | __clk_reparent(hw->clk, new_parent); | 529 | __clk_reparent(hw->clk, new_parent); |
527 | 530 | ||
528 | clk_disable(dd->clk_ref); | ||
529 | __clk_unprepare(dd->clk_ref); | ||
530 | clk_disable(dd->clk_bypass); | ||
531 | __clk_unprepare(dd->clk_bypass); | ||
532 | |||
533 | return 0; | 531 | return 0; |
534 | } | 532 | } |
535 | 533 | ||
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index b155500e84a8..b8208b4b1bd9 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include "control.h" | 26 | #include "control.h" |
27 | #include "cm2xxx_3xxx.h" | 27 | #include "cm2xxx_3xxx.h" |
28 | #include "prm2xxx_3xxx.h" | 28 | #include "prm2xxx_3xxx.h" |
29 | #ifdef CONFIG_BRIDGE_DVFS | 29 | #ifdef CONFIG_TIDSPBRIDGE_DVFS |
30 | #include "omap-pm.h" | 30 | #include "omap-pm.h" |
31 | #endif | 31 | #endif |
32 | 32 | ||
@@ -35,7 +35,7 @@ | |||
35 | static struct platform_device *omap_dsp_pdev; | 35 | static struct platform_device *omap_dsp_pdev; |
36 | 36 | ||
37 | static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { | 37 | static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { |
38 | #ifdef CONFIG_BRIDGE_DVFS | 38 | #ifdef CONFIG_TIDSPBRIDGE_DVFS |
39 | .dsp_set_min_opp = omap_pm_dsp_set_min_opp, | 39 | .dsp_set_min_opp = omap_pm_dsp_set_min_opp, |
40 | .dsp_get_opp = omap_pm_dsp_get_opp, | 40 | .dsp_get_opp = omap_pm_dsp_get_opp, |
41 | .cpu_set_freq = omap_pm_cpu_set_freq, | 41 | .cpu_set_freq = omap_pm_cpu_set_freq, |
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index fadd87435cd0..0d75889c0a6f 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
@@ -303,7 +303,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base) | |||
303 | t = omap2_onenand_calc_async_timings(); | 303 | t = omap2_onenand_calc_async_timings(); |
304 | 304 | ||
305 | ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); | 305 | ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t); |
306 | if (IS_ERR_VALUE(ret)) | 306 | if (ret < 0) |
307 | return ret; | 307 | return ret; |
308 | 308 | ||
309 | omap2_onenand_set_async_mode(onenand_base); | 309 | omap2_onenand_set_async_mode(onenand_base); |
@@ -325,7 +325,7 @@ static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr) | |||
325 | t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); | 325 | t = omap2_onenand_calc_sync_timings(gpmc_onenand_data, freq); |
326 | 326 | ||
327 | ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); | 327 | ret = gpmc_set_sync_mode(gpmc_onenand_data->cs, &t); |
328 | if (IS_ERR_VALUE(ret)) | 328 | if (ret < 0) |
329 | return ret; | 329 | return ret; |
330 | 330 | ||
331 | set_onenand_cfg(onenand_base); | 331 | set_onenand_cfg(onenand_base); |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 410e1bac7815..6de31739b45c 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -716,7 +716,7 @@ static int gpmc_setup_irq(void) | |||
716 | return -EINVAL; | 716 | return -EINVAL; |
717 | 717 | ||
718 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | 718 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); |
719 | if (IS_ERR_VALUE(gpmc_irq_start)) { | 719 | if (gpmc_irq_start < 0) { |
720 | pr_err("irq_alloc_descs failed\n"); | 720 | pr_err("irq_alloc_descs failed\n"); |
721 | return gpmc_irq_start; | 721 | return gpmc_irq_start; |
722 | } | 722 | } |
@@ -801,7 +801,7 @@ static int gpmc_mem_init(void) | |||
801 | continue; | 801 | continue; |
802 | gpmc_cs_get_memconf(cs, &base, &size); | 802 | gpmc_cs_get_memconf(cs, &base, &size); |
803 | rc = gpmc_cs_insert_mem(cs, base, size); | 803 | rc = gpmc_cs_insert_mem(cs, base, size); |
804 | if (IS_ERR_VALUE(rc)) { | 804 | if (rc < 0) { |
805 | while (--cs >= 0) | 805 | while (--cs >= 0) |
806 | if (gpmc_cs_mem_enabled(cs)) | 806 | if (gpmc_cs_mem_enabled(cs)) |
807 | gpmc_cs_delete_mem(cs); | 807 | gpmc_cs_delete_mem(cs); |
@@ -1370,14 +1370,14 @@ static int gpmc_probe(struct platform_device *pdev) | |||
1370 | GPMC_REVISION_MINOR(l)); | 1370 | GPMC_REVISION_MINOR(l)); |
1371 | 1371 | ||
1372 | rc = gpmc_mem_init(); | 1372 | rc = gpmc_mem_init(); |
1373 | if (IS_ERR_VALUE(rc)) { | 1373 | if (rc < 0) { |
1374 | clk_disable_unprepare(gpmc_l3_clk); | 1374 | clk_disable_unprepare(gpmc_l3_clk); |
1375 | clk_put(gpmc_l3_clk); | 1375 | clk_put(gpmc_l3_clk); |
1376 | dev_err(gpmc_dev, "failed to reserve memory\n"); | 1376 | dev_err(gpmc_dev, "failed to reserve memory\n"); |
1377 | return rc; | 1377 | return rc; |
1378 | } | 1378 | } |
1379 | 1379 | ||
1380 | if (IS_ERR_VALUE(gpmc_setup_irq())) | 1380 | if (gpmc_setup_irq() < 0) |
1381 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); | 1381 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); |
1382 | 1382 | ||
1383 | /* Now the GPMC is initialised, unreserve the chip-selects */ | 1383 | /* Now the GPMC is initialised, unreserve the chip-selects */ |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 8a68f1ec66b9..ff0bc9e51aa7 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
@@ -529,22 +529,28 @@ void __init omap5xxx_check_revision(void) | |||
529 | case 0xb942: | 529 | case 0xb942: |
530 | switch (rev) { | 530 | switch (rev) { |
531 | case 0: | 531 | case 0: |
532 | default: | ||
533 | omap_revision = OMAP5430_REV_ES1_0; | 532 | omap_revision = OMAP5430_REV_ES1_0; |
533 | break; | ||
534 | case 1: | ||
535 | default: | ||
536 | omap_revision = OMAP5430_REV_ES2_0; | ||
534 | } | 537 | } |
535 | break; | 538 | break; |
536 | 539 | ||
537 | case 0xb998: | 540 | case 0xb998: |
538 | switch (rev) { | 541 | switch (rev) { |
539 | case 0: | 542 | case 0: |
540 | default: | ||
541 | omap_revision = OMAP5432_REV_ES1_0; | 543 | omap_revision = OMAP5432_REV_ES1_0; |
544 | break; | ||
545 | case 1: | ||
546 | default: | ||
547 | omap_revision = OMAP5432_REV_ES2_0; | ||
542 | } | 548 | } |
543 | break; | 549 | break; |
544 | 550 | ||
545 | default: | 551 | default: |
546 | /* Unknown default to latest silicon rev as default*/ | 552 | /* Unknown default to latest silicon rev as default*/ |
547 | omap_revision = OMAP5430_REV_ES1_0; | 553 | omap_revision = OMAP5430_REV_ES2_0; |
548 | } | 554 | } |
549 | 555 | ||
550 | pr_info("OMAP%04x ES%d.0\n", | 556 | pr_info("OMAP%04x ES%d.0\n", |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 2c3fdd65387b..2bef5a7e6af8 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -271,6 +271,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = { | |||
271 | .length = L4_PER_54XX_SIZE, | 271 | .length = L4_PER_54XX_SIZE, |
272 | .type = MT_DEVICE, | 272 | .type = MT_DEVICE, |
273 | }, | 273 | }, |
274 | #ifdef CONFIG_OMAP4_ERRATA_I688 | ||
275 | { | ||
276 | .virtual = OMAP4_SRAM_VA, | ||
277 | .pfn = __phys_to_pfn(OMAP4_SRAM_PA), | ||
278 | .length = PAGE_SIZE, | ||
279 | .type = MT_MEMORY_SO, | ||
280 | }, | ||
281 | #endif | ||
274 | }; | 282 | }; |
275 | #endif | 283 | #endif |
276 | 284 | ||
@@ -323,6 +331,7 @@ void __init omap4_map_io(void) | |||
323 | void __init omap5_map_io(void) | 331 | void __init omap5_map_io(void) |
324 | { | 332 | { |
325 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); | 333 | iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); |
334 | omap_barriers_init(); | ||
326 | } | 335 | } |
327 | #endif | 336 | #endif |
328 | /* | 337 | /* |
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 708bb115a27f..2aeb928efdfd 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c | |||
@@ -240,15 +240,21 @@ void __iomem *omap4_get_sar_ram_base(void) | |||
240 | */ | 240 | */ |
241 | static int __init omap4_sar_ram_init(void) | 241 | static int __init omap4_sar_ram_init(void) |
242 | { | 242 | { |
243 | unsigned long sar_base; | ||
244 | |||
243 | /* | 245 | /* |
244 | * To avoid code running on other OMAPs in | 246 | * To avoid code running on other OMAPs in |
245 | * multi-omap builds | 247 | * multi-omap builds |
246 | */ | 248 | */ |
247 | if (!cpu_is_omap44xx()) | 249 | if (cpu_is_omap44xx()) |
250 | sar_base = OMAP44XX_SAR_RAM_BASE; | ||
251 | else if (soc_is_omap54xx()) | ||
252 | sar_base = OMAP54XX_SAR_RAM_BASE; | ||
253 | else | ||
248 | return -ENOMEM; | 254 | return -ENOMEM; |
249 | 255 | ||
250 | /* Static mapping, never released */ | 256 | /* Static mapping, never released */ |
251 | sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); | 257 | sar_ram_base = ioremap(sar_base, SZ_16K); |
252 | if (WARN_ON(!sar_ram_base)) | 258 | if (WARN_ON(!sar_ram_base)) |
253 | return -ENOMEM; | 259 | return -ENOMEM; |
254 | 260 | ||
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h index e170fe803b04..937417523b8e 100644 --- a/arch/arm/mach-omap2/omap4-sar-layout.h +++ b/arch/arm/mach-omap2/omap4-sar-layout.h | |||
@@ -48,13 +48,13 @@ | |||
48 | #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 | 48 | #define SAR_BACKUP_STATUS_WAKEUPGEN 0x10 |
49 | 49 | ||
50 | /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ | 50 | /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */ |
51 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4) | 51 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9dc) |
52 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8) | 52 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x9f0) |
53 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc) | 53 | #define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa04) |
54 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910) | 54 | #define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0xa18) |
55 | #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924) | 55 | #define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0xa2c) |
56 | #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928) | 56 | #define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x930) |
57 | #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c) | 57 | #define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0xa34) |
58 | #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) | 58 | #define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800) |
59 | 59 | ||
60 | #endif | 60 | #endif |
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a2582bb3cab3..a086ba15868b 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h | |||
@@ -28,5 +28,6 @@ | |||
28 | #define OMAP54XX_PRCM_MPU_BASE 0x48243000 | 28 | #define OMAP54XX_PRCM_MPU_BASE 0x48243000 |
29 | #define OMAP54XX_SCM_BASE 0x4a002000 | 29 | #define OMAP54XX_SCM_BASE 0x4a002000 |
30 | #define OMAP54XX_CTRL_BASE 0x4a002800 | 30 | #define OMAP54XX_CTRL_BASE 0x4a002800 |
31 | #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 | ||
31 | 32 | ||
32 | #endif /* __ASM_SOC_OMAP555554XX_H */ | 33 | #endif /* __ASM_SOC_OMAP555554XX_H */ |
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index 381be7ac0c17..eeea4fa28fbc 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c | |||
@@ -131,7 +131,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev) | |||
131 | int oh_cnt, i, ret = 0; | 131 | int oh_cnt, i, ret = 0; |
132 | 132 | ||
133 | oh_cnt = of_property_count_strings(node, "ti,hwmods"); | 133 | oh_cnt = of_property_count_strings(node, "ti,hwmods"); |
134 | if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) { | 134 | if (oh_cnt <= 0) { |
135 | dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n"); | 135 | dev_dbg(&pdev->dev, "No 'hwmods' to build omap_device\n"); |
136 | return -ENODEV; | 136 | return -ENODEV; |
137 | } | 137 | } |
@@ -815,20 +815,17 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name) | |||
815 | } | 815 | } |
816 | 816 | ||
817 | oh = omap_hwmod_lookup(oh_name); | 817 | oh = omap_hwmod_lookup(oh_name); |
818 | if (IS_ERR_OR_NULL(oh)) { | 818 | if (!oh) { |
819 | WARN(1, "%s: no hwmod for %s\n", __func__, | 819 | WARN(1, "%s: no hwmod for %s\n", __func__, |
820 | oh_name); | 820 | oh_name); |
821 | return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV); | 821 | return ERR_PTR(-ENODEV); |
822 | } | 822 | } |
823 | if (IS_ERR_OR_NULL(oh->od)) { | 823 | if (!oh->od) { |
824 | WARN(1, "%s: no omap_device for %s\n", __func__, | 824 | WARN(1, "%s: no omap_device for %s\n", __func__, |
825 | oh_name); | 825 | oh_name); |
826 | return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV); | 826 | return ERR_PTR(-ENODEV); |
827 | } | 827 | } |
828 | 828 | ||
829 | if (IS_ERR_OR_NULL(oh->od->pdev)) | ||
830 | return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV); | ||
831 | |||
832 | return &oh->od->pdev->dev; | 829 | return &oh->od->pdev->dev; |
833 | } | 830 | } |
834 | 831 | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index c2c798c08c2b..2520d46c8508 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -610,8 +610,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) | |||
610 | 610 | ||
611 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 611 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
612 | 612 | ||
613 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | ||
614 | |||
615 | return 0; | 613 | return 0; |
616 | } | 614 | } |
617 | 615 | ||
@@ -645,8 +643,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) | |||
645 | 643 | ||
646 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | 644 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
647 | 645 | ||
648 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | ||
649 | |||
650 | return 0; | 646 | return 0; |
651 | } | 647 | } |
652 | 648 | ||
@@ -1663,7 +1659,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |||
1663 | return -ENOSYS; | 1659 | return -ENOSYS; |
1664 | 1660 | ||
1665 | ret = _lookup_hardreset(oh, name, &ohri); | 1661 | ret = _lookup_hardreset(oh, name, &ohri); |
1666 | if (IS_ERR_VALUE(ret)) | 1662 | if (ret < 0) |
1667 | return ret; | 1663 | return ret; |
1668 | 1664 | ||
1669 | if (oh->clkdm) { | 1665 | if (oh->clkdm) { |
@@ -2413,7 +2409,7 @@ static int __init _init(struct omap_hwmod *oh, void *data) | |||
2413 | _init_mpu_rt_base(oh, NULL); | 2409 | _init_mpu_rt_base(oh, NULL); |
2414 | 2410 | ||
2415 | r = _init_clocks(oh, NULL); | 2411 | r = _init_clocks(oh, NULL); |
2416 | if (IS_ERR_VALUE(r)) { | 2412 | if (r < 0) { |
2417 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | 2413 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); |
2418 | return -EINVAL; | 2414 | return -EINVAL; |
2419 | } | 2415 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index d43d9b608eda..28f4dea0512e 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h | |||
@@ -477,15 +477,13 @@ struct omap_hwmod_omap4_prcm { | |||
477 | * These are for internal use only and are managed by the omap_hwmod code. | 477 | * These are for internal use only and are managed by the omap_hwmod code. |
478 | * | 478 | * |
479 | * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module | 479 | * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module |
480 | * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP | ||
481 | * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached | 480 | * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached |
482 | * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - | 481 | * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) - |
483 | * causes the first call to _enable() to only update the pinmux | 482 | * causes the first call to _enable() to only update the pinmux |
484 | */ | 483 | */ |
485 | #define _HWMOD_NO_MPU_PORT (1 << 0) | 484 | #define _HWMOD_NO_MPU_PORT (1 << 0) |
486 | #define _HWMOD_WAKEUP_ENABLED (1 << 1) | 485 | #define _HWMOD_SYSCONFIG_LOADED (1 << 1) |
487 | #define _HWMOD_SYSCONFIG_LOADED (1 << 2) | 486 | #define _HWMOD_SKIP_ENABLE (1 << 2) |
488 | #define _HWMOD_SKIP_ENABLE (1 << 3) | ||
489 | 487 | ||
490 | /* | 488 | /* |
491 | * omap_hwmod._state definitions | 489 | * omap_hwmod._state definitions |
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 26eee4a556ad..31bea1ce3de1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include "prm-regbits-33xx.h" | 28 | #include "prm-regbits-33xx.h" |
29 | #include "i2c.h" | 29 | #include "i2c.h" |
30 | #include "mmc.h" | 30 | #include "mmc.h" |
31 | #include "wd_timer.h" | ||
31 | 32 | ||
32 | /* | 33 | /* |
33 | * IP blocks | 34 | * IP blocks |
@@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = { | |||
2087 | }; | 2088 | }; |
2088 | 2089 | ||
2089 | /* 'wd_timer' class */ | 2090 | /* 'wd_timer' class */ |
2091 | static struct omap_hwmod_class_sysconfig wdt_sysc = { | ||
2092 | .rev_offs = 0x0, | ||
2093 | .sysc_offs = 0x10, | ||
2094 | .syss_offs = 0x14, | ||
2095 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | | ||
2096 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), | ||
2097 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
2098 | SIDLE_SMART_WKUP), | ||
2099 | .sysc_fields = &omap_hwmod_sysc_type1, | ||
2100 | }; | ||
2101 | |||
2090 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { | 2102 | static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = { |
2091 | .name = "wd_timer", | 2103 | .name = "wd_timer", |
2104 | .sysc = &wdt_sysc, | ||
2105 | .pre_shutdown = &omap2_wd_timer_disable, | ||
2092 | }; | 2106 | }; |
2093 | 2107 | ||
2094 | /* | 2108 | /* |
@@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = { | |||
2099 | .name = "wd_timer2", | 2113 | .name = "wd_timer2", |
2100 | .class = &am33xx_wd_timer_hwmod_class, | 2114 | .class = &am33xx_wd_timer_hwmod_class, |
2101 | .clkdm_name = "l4_wkup_clkdm", | 2115 | .clkdm_name = "l4_wkup_clkdm", |
2116 | .flags = HWMOD_SWSUP_SIDLE, | ||
2102 | .main_clk = "wdt1_fck", | 2117 | .main_clk = "wdt1_fck", |
2103 | .prcm = { | 2118 | .prcm = { |
2104 | .omap4 = { | 2119 | .omap4 = { |
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 1edd000a8143..0b339861d751 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c | |||
@@ -217,7 +217,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir) | |||
217 | return 0; | 217 | return 0; |
218 | 218 | ||
219 | d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir); | 219 | d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir); |
220 | if (!(IS_ERR_OR_NULL(d))) | 220 | if (d) |
221 | (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, | 221 | (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d, |
222 | (void *)pwrdm, &pwrdm_suspend_fops); | 222 | (void *)pwrdm, &pwrdm_suspend_fops); |
223 | 223 | ||
@@ -261,8 +261,8 @@ static int __init pm_dbg_init(void) | |||
261 | return 0; | 261 | return 0; |
262 | 262 | ||
263 | d = debugfs_create_dir("pm_debug", NULL); | 263 | d = debugfs_create_dir("pm_debug", NULL); |
264 | if (IS_ERR_OR_NULL(d)) | 264 | if (!d) |
265 | return PTR_ERR(d); | 265 | return -EINVAL; |
266 | 266 | ||
267 | (void) debugfs_create_file("count", S_IRUGO, | 267 | (void) debugfs_create_file("count", S_IRUGO, |
268 | d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); | 268 | d, (void *)DEBUG_FILE_COUNTERS, &debug_fops); |
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 8e61d80bf6b3..86babd740d41 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c | |||
@@ -52,7 +52,6 @@ enum { | |||
52 | #define ALREADYACTIVE_SWITCH 0 | 52 | #define ALREADYACTIVE_SWITCH 0 |
53 | #define FORCEWAKEUP_SWITCH 1 | 53 | #define FORCEWAKEUP_SWITCH 1 |
54 | #define LOWPOWERSTATE_SWITCH 2 | 54 | #define LOWPOWERSTATE_SWITCH 2 |
55 | #define ERROR_SWITCH 3 | ||
56 | 55 | ||
57 | /* pwrdm_list contains all registered struct powerdomains */ | 56 | /* pwrdm_list contains all registered struct powerdomains */ |
58 | static LIST_HEAD(pwrdm_list); | 57 | static LIST_HEAD(pwrdm_list); |
@@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm, | |||
233 | { | 232 | { |
234 | u8 sleep_switch; | 233 | u8 sleep_switch; |
235 | 234 | ||
236 | if (curr_pwrst < 0) { | 235 | if (curr_pwrst < PWRDM_POWER_ON) { |
237 | WARN_ON(1); | ||
238 | sleep_switch = ERROR_SWITCH; | ||
239 | } else if (curr_pwrst < PWRDM_POWER_ON) { | ||
240 | if (curr_pwrst > pwrst && | 236 | if (curr_pwrst > pwrst && |
241 | pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && | 237 | pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE && |
242 | arch_pwrdm->pwrdm_set_lowpwrstchange) { | 238 | arch_pwrdm->pwrdm_set_lowpwrstchange) { |
@@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm) | |||
1091 | */ | 1087 | */ |
1092 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) | 1088 | int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) |
1093 | { | 1089 | { |
1094 | u8 curr_pwrst, next_pwrst, sleep_switch; | 1090 | u8 next_pwrst, sleep_switch; |
1091 | int curr_pwrst; | ||
1095 | int ret = 0; | 1092 | int ret = 0; |
1096 | bool hwsup = false; | 1093 | bool hwsup = false; |
1097 | 1094 | ||
@@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst) | |||
1107 | pwrdm_lock(pwrdm); | 1104 | pwrdm_lock(pwrdm); |
1108 | 1105 | ||
1109 | curr_pwrst = pwrdm_read_pwrst(pwrdm); | 1106 | curr_pwrst = pwrdm_read_pwrst(pwrdm); |
1107 | if (curr_pwrst < 0) { | ||
1108 | ret = -EINVAL; | ||
1109 | goto osps_out; | ||
1110 | } | ||
1111 | |||
1110 | next_pwrst = pwrdm_read_next_pwrst(pwrdm); | 1112 | next_pwrst = pwrdm_read_next_pwrst(pwrdm); |
1111 | if (curr_pwrst == pwrst && next_pwrst == pwrst) | 1113 | if (curr_pwrst == pwrst && next_pwrst == pwrst) |
1112 | goto osps_out; | 1114 | goto osps_out; |
1113 | 1115 | ||
1114 | sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, | 1116 | sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst, |
1115 | pwrst, &hwsup); | 1117 | pwrst, &hwsup); |
1116 | if (sleep_switch == ERROR_SWITCH) { | ||
1117 | ret = -EINVAL; | ||
1118 | goto osps_out; | ||
1119 | } | ||
1120 | 1118 | ||
1121 | ret = pwrdm_set_next_pwrst(pwrdm, pwrst); | 1119 | ret = pwrdm_set_next_pwrst(pwrdm, pwrst); |
1122 | if (ret) | 1120 | if (ret) |
@@ -1182,7 +1180,7 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm) | |||
1182 | { | 1180 | { |
1183 | int i; | 1181 | int i; |
1184 | 1182 | ||
1185 | if (IS_ERR_OR_NULL(pwrdm)) { | 1183 | if (!pwrdm) { |
1186 | pr_debug("powerdomain: %s: invalid powerdomain pointer\n", | 1184 | pr_debug("powerdomain: %s: invalid powerdomain pointer\n", |
1187 | __func__); | 1185 | __func__); |
1188 | return 1; | 1186 | return 1; |
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index d35f98aabf7a..415c7e0c9393 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c | |||
@@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = { | |||
81 | /* Read a register in a CM/PRM instance in the PRM module */ | 81 | /* Read a register in a CM/PRM instance in the PRM module */ |
82 | u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) | 82 | u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) |
83 | { | 83 | { |
84 | return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); | 84 | return __raw_readl(prm_base + inst + reg); |
85 | } | 85 | } |
86 | 86 | ||
87 | /* Write into a register in a CM/PRM instance in the PRM module */ | 87 | /* Write into a register in a CM/PRM instance in the PRM module */ |
88 | void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) | 88 | void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) |
89 | { | 89 | { |
90 | __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); | 90 | __raw_writel(val, prm_base + inst + reg); |
91 | } | 91 | } |
92 | 92 | ||
93 | /* Read-modify-write a register in a PRM module. Caller must lock */ | 93 | /* Read-modify-write a register in a PRM module. Caller must lock */ |
@@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { | |||
650 | 650 | ||
651 | int __init omap44xx_prm_init(void) | 651 | int __init omap44xx_prm_init(void) |
652 | { | 652 | { |
653 | if (!cpu_is_omap44xx()) | 653 | if (!cpu_is_omap44xx() && !soc_is_omap54xx()) |
654 | return 0; | 654 | return 0; |
655 | 655 | ||
656 | return prm_register(&omap44xx_prm_ll_data); | 656 | return prm_register(&omap44xx_prm_ll_data); |
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index c62116bbc760..18fdeeb3a44a 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h | |||
@@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
413 | 413 | ||
414 | #define OMAP54XX_CLASS 0x54000054 | 414 | #define OMAP54XX_CLASS 0x54000054 |
415 | #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) | 415 | #define OMAP5430_REV_ES1_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8)) |
416 | #define OMAP5430_REV_ES2_0 (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8)) | ||
416 | #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) | 417 | #define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8)) |
418 | #define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8)) | ||
417 | 419 | ||
418 | void omap2xxx_check_revision(void); | 420 | void omap2xxx_check_revision(void); |
419 | void omap3xxx_check_revision(void); | 421 | void omap3xxx_check_revision(void); |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 4fd80257c73e..f12aa6c15da4 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -57,15 +57,6 @@ | |||
57 | #include "common.h" | 57 | #include "common.h" |
58 | #include "powerdomain.h" | 58 | #include "powerdomain.h" |
59 | 59 | ||
60 | /* Parent clocks, eventually these will come from the clock framework */ | ||
61 | |||
62 | #define OMAP2_MPU_SOURCE "sys_ck" | ||
63 | #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE | ||
64 | #define OMAP4_MPU_SOURCE "sys_clkin_ck" | ||
65 | #define OMAP2_32K_SOURCE "func_32k_ck" | ||
66 | #define OMAP3_32K_SOURCE "omap_32k_fck" | ||
67 | #define OMAP4_32K_SOURCE "sys_32k_ck" | ||
68 | |||
69 | #define REALTIME_COUNTER_BASE 0x48243200 | 60 | #define REALTIME_COUNTER_BASE 0x48243200 |
70 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 | 61 | #define INCREMENTER_NUMERATOR_OFFSET 0x10 |
71 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 | 62 | #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 |
@@ -129,7 +120,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode, | |||
129 | } | 120 | } |
130 | 121 | ||
131 | static struct clock_event_device clockevent_gpt = { | 122 | static struct clock_event_device clockevent_gpt = { |
132 | .name = "gp_timer", | ||
133 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | 123 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
134 | .rating = 300, | 124 | .rating = 300, |
135 | .set_next_event = omap2_gp_timer_set_next_event, | 125 | .set_next_event = omap2_gp_timer_set_next_event, |
@@ -170,6 +160,12 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, | |||
170 | if (property && !of_get_property(np, property, NULL)) | 160 | if (property && !of_get_property(np, property, NULL)) |
171 | continue; | 161 | continue; |
172 | 162 | ||
163 | if (!property && (of_get_property(np, "ti,timer-alwon", NULL) || | ||
164 | of_get_property(np, "ti,timer-dsp", NULL) || | ||
165 | of_get_property(np, "ti,timer-pwm", NULL) || | ||
166 | of_get_property(np, "ti,timer-secure", NULL))) | ||
167 | continue; | ||
168 | |||
173 | of_add_property(np, &device_disabled); | 169 | of_add_property(np, &device_disabled); |
174 | return np; | 170 | return np; |
175 | } | 171 | } |
@@ -214,16 +210,17 @@ static u32 __init omap_dm_timer_get_errata(void) | |||
214 | } | 210 | } |
215 | 211 | ||
216 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, | 212 | static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, |
217 | int gptimer_id, | 213 | const char *fck_source, |
218 | const char *fck_source, | 214 | const char *property, |
219 | const char *property, | 215 | const char **timer_name, |
220 | int posted) | 216 | int posted) |
221 | { | 217 | { |
222 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ | 218 | char name[10]; /* 10 = sizeof("gptXX_Xck0") */ |
223 | const char *oh_name; | 219 | const char *oh_name; |
224 | struct device_node *np; | 220 | struct device_node *np; |
225 | struct omap_hwmod *oh; | 221 | struct omap_hwmod *oh; |
226 | struct resource irq, mem; | 222 | struct resource irq, mem; |
223 | struct clk *src; | ||
227 | int r = 0; | 224 | int r = 0; |
228 | 225 | ||
229 | if (of_have_populated_dt()) { | 226 | if (of_have_populated_dt()) { |
@@ -243,10 +240,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, | |||
243 | 240 | ||
244 | of_node_put(np); | 241 | of_node_put(np); |
245 | } else { | 242 | } else { |
246 | if (omap_dm_timer_reserve_systimer(gptimer_id)) | 243 | if (omap_dm_timer_reserve_systimer(timer->id)) |
247 | return -ENODEV; | 244 | return -ENODEV; |
248 | 245 | ||
249 | sprintf(name, "timer%d", gptimer_id); | 246 | sprintf(name, "timer%d", timer->id); |
250 | oh_name = name; | 247 | oh_name = name; |
251 | } | 248 | } |
252 | 249 | ||
@@ -254,6 +251,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, | |||
254 | if (!oh) | 251 | if (!oh) |
255 | return -ENODEV; | 252 | return -ENODEV; |
256 | 253 | ||
254 | *timer_name = oh->name; | ||
255 | |||
257 | if (!of_have_populated_dt()) { | 256 | if (!of_have_populated_dt()) { |
258 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, | 257 | r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, |
259 | &irq); | 258 | &irq); |
@@ -276,24 +275,24 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, | |||
276 | /* After the dmtimer is using hwmod these clocks won't be needed */ | 275 | /* After the dmtimer is using hwmod these clocks won't be needed */ |
277 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); | 276 | timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); |
278 | if (IS_ERR(timer->fclk)) | 277 | if (IS_ERR(timer->fclk)) |
279 | return -ENODEV; | 278 | return PTR_ERR(timer->fclk); |
280 | 279 | ||
281 | /* FIXME: Need to remove hard-coded test on timer ID */ | 280 | src = clk_get(NULL, fck_source); |
282 | if (gptimer_id != 12) { | 281 | if (IS_ERR(src)) |
283 | struct clk *src; | 282 | return PTR_ERR(src); |
284 | 283 | ||
285 | src = clk_get(NULL, fck_source); | 284 | if (clk_get_parent(timer->fclk) != src) { |
286 | if (IS_ERR(src)) { | 285 | r = clk_set_parent(timer->fclk, src); |
287 | r = -EINVAL; | 286 | if (r < 0) { |
288 | } else { | 287 | pr_warn("%s: %s cannot set source\n", __func__, |
289 | r = clk_set_parent(timer->fclk, src); | 288 | oh->name); |
290 | if (IS_ERR_VALUE(r)) | ||
291 | pr_warn("%s: %s cannot set source\n", | ||
292 | __func__, oh->name); | ||
293 | clk_put(src); | 289 | clk_put(src); |
290 | return r; | ||
294 | } | 291 | } |
295 | } | 292 | } |
296 | 293 | ||
294 | clk_put(src); | ||
295 | |||
297 | omap_hwmod_setup_one(oh_name); | 296 | omap_hwmod_setup_one(oh_name); |
298 | omap_hwmod_enable(oh); | 297 | omap_hwmod_enable(oh); |
299 | __omap_dm_timer_init_regs(timer); | 298 | __omap_dm_timer_init_regs(timer); |
@@ -317,6 +316,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, | |||
317 | { | 316 | { |
318 | int res; | 317 | int res; |
319 | 318 | ||
319 | clkev.id = gptimer_id; | ||
320 | clkev.errata = omap_dm_timer_get_errata(); | 320 | clkev.errata = omap_dm_timer_get_errata(); |
321 | 321 | ||
322 | /* | 322 | /* |
@@ -326,8 +326,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, | |||
326 | */ | 326 | */ |
327 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); | 327 | __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767); |
328 | 328 | ||
329 | res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property, | 329 | res = omap_dm_timer_init_one(&clkev, fck_source, property, |
330 | OMAP_TIMER_POSTED); | 330 | &clockevent_gpt.name, OMAP_TIMER_POSTED); |
331 | BUG_ON(res); | 331 | BUG_ON(res); |
332 | 332 | ||
333 | omap2_gp_timer_irq.dev_id = &clkev; | 333 | omap2_gp_timer_irq.dev_id = &clkev; |
@@ -341,8 +341,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, | |||
341 | 3, /* Timer internal resynch latency */ | 341 | 3, /* Timer internal resynch latency */ |
342 | 0xffffffff); | 342 | 0xffffffff); |
343 | 343 | ||
344 | pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", | 344 | pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, |
345 | gptimer_id, clkev.rate); | 345 | clkev.rate); |
346 | } | 346 | } |
347 | 347 | ||
348 | /* Clocksource code */ | 348 | /* Clocksource code */ |
@@ -359,7 +359,6 @@ static cycle_t clocksource_read_cycles(struct clocksource *cs) | |||
359 | } | 359 | } |
360 | 360 | ||
361 | static struct clocksource clocksource_gpt = { | 361 | static struct clocksource clocksource_gpt = { |
362 | .name = "gp_timer", | ||
363 | .rating = 300, | 362 | .rating = 300, |
364 | .read = clocksource_read_cycles, | 363 | .read = clocksource_read_cycles, |
365 | .mask = CLOCKSOURCE_MASK(32), | 364 | .mask = CLOCKSOURCE_MASK(32), |
@@ -442,13 +441,16 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void) | |||
442 | } | 441 | } |
443 | 442 | ||
444 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, | 443 | static void __init omap2_gptimer_clocksource_init(int gptimer_id, |
445 | const char *fck_source) | 444 | const char *fck_source, |
445 | const char *property) | ||
446 | { | 446 | { |
447 | int res; | 447 | int res; |
448 | 448 | ||
449 | clksrc.id = gptimer_id; | ||
449 | clksrc.errata = omap_dm_timer_get_errata(); | 450 | clksrc.errata = omap_dm_timer_get_errata(); |
450 | 451 | ||
451 | res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL, | 452 | res = omap_dm_timer_init_one(&clksrc, fck_source, property, |
453 | &clocksource_gpt.name, | ||
452 | OMAP_TIMER_NONPOSTED); | 454 | OMAP_TIMER_NONPOSTED); |
453 | BUG_ON(res); | 455 | BUG_ON(res); |
454 | 456 | ||
@@ -461,8 +463,8 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id, | |||
461 | pr_err("Could not register clocksource %s\n", | 463 | pr_err("Could not register clocksource %s\n", |
462 | clocksource_gpt.name); | 464 | clocksource_gpt.name); |
463 | else | 465 | else |
464 | pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n", | 466 | pr_info("OMAP clocksource: %s at %lu Hz\n", |
465 | gptimer_id, clksrc.rate); | 467 | clocksource_gpt.name, clksrc.rate); |
466 | } | 468 | } |
467 | 469 | ||
468 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER | 470 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER |
@@ -487,7 +489,7 @@ static void __init realtime_counter_init(void) | |||
487 | pr_err("%s: ioremap failed\n", __func__); | 489 | pr_err("%s: ioremap failed\n", __func__); |
488 | return; | 490 | return; |
489 | } | 491 | } |
490 | sys_clk = clk_get(NULL, "sys_clkin_ck"); | 492 | sys_clk = clk_get(NULL, "sys_clkin"); |
491 | if (IS_ERR(sys_clk)) { | 493 | if (IS_ERR(sys_clk)) { |
492 | pr_err("%s: failed to get system clock handle\n", __func__); | 494 | pr_err("%s: failed to get system clock handle\n", __func__); |
493 | iounmap(base); | 495 | iounmap(base); |
@@ -544,49 +546,52 @@ static inline void __init realtime_counter_init(void) | |||
544 | #endif | 546 | #endif |
545 | 547 | ||
546 | #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ | 548 | #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
547 | clksrc_nr, clksrc_src) \ | 549 | clksrc_nr, clksrc_src, clksrc_prop) \ |
548 | void __init omap##name##_gptimer_timer_init(void) \ | 550 | void __init omap##name##_gptimer_timer_init(void) \ |
549 | { \ | 551 | { \ |
550 | omap_dmtimer_init(); \ | 552 | omap_dmtimer_init(); \ |
551 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ | 553 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
552 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \ | 554 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
555 | clksrc_prop); \ | ||
553 | } | 556 | } |
554 | 557 | ||
555 | #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ | 558 | #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \ |
556 | clksrc_nr, clksrc_src) \ | 559 | clksrc_nr, clksrc_src, clksrc_prop) \ |
557 | void __init omap##name##_sync32k_timer_init(void) \ | 560 | void __init omap##name##_sync32k_timer_init(void) \ |
558 | { \ | 561 | { \ |
559 | omap_dmtimer_init(); \ | 562 | omap_dmtimer_init(); \ |
560 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ | 563 | omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \ |
561 | /* Enable the use of clocksource="gp_timer" kernel parameter */ \ | 564 | /* Enable the use of clocksource="gp_timer" kernel parameter */ \ |
562 | if (use_gptimer_clksrc) \ | 565 | if (use_gptimer_clksrc) \ |
563 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\ | 566 | omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \ |
567 | clksrc_prop); \ | ||
564 | else \ | 568 | else \ |
565 | omap2_sync32k_clocksource_init(); \ | 569 | omap2_sync32k_clocksource_init(); \ |
566 | } | 570 | } |
567 | 571 | ||
568 | #ifdef CONFIG_ARCH_OMAP2 | 572 | #ifdef CONFIG_ARCH_OMAP2 |
569 | OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon", | 573 | OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon", |
570 | 2, OMAP2_MPU_SOURCE); | 574 | 2, "timer_sys_ck", NULL); |
571 | #endif /* CONFIG_ARCH_OMAP2 */ | 575 | #endif /* CONFIG_ARCH_OMAP2 */ |
572 | 576 | ||
573 | #ifdef CONFIG_ARCH_OMAP3 | 577 | #ifdef CONFIG_ARCH_OMAP3 |
574 | OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon", | 578 | OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon", |
575 | 2, OMAP3_MPU_SOURCE); | 579 | 2, "timer_sys_ck", NULL); |
576 | OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure", | 580 | OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure", |
577 | 2, OMAP3_MPU_SOURCE); | 581 | 2, "timer_sys_ck", NULL); |
578 | OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon", | ||
579 | 2, OMAP3_MPU_SOURCE); | ||
580 | #endif /* CONFIG_ARCH_OMAP3 */ | 582 | #endif /* CONFIG_ARCH_OMAP3 */ |
581 | 583 | ||
582 | #ifdef CONFIG_SOC_AM33XX | 584 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
583 | OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon", | 585 | OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, |
584 | 2, OMAP4_MPU_SOURCE); | 586 | 1, "timer_sys_ck", "ti,timer-alwon"); |
585 | #endif /* CONFIG_SOC_AM33XX */ | 587 | #endif |
588 | |||
589 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) | ||
590 | static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", | ||
591 | 2, "sys_clkin_ck", NULL); | ||
592 | #endif | ||
586 | 593 | ||
587 | #ifdef CONFIG_ARCH_OMAP4 | 594 | #ifdef CONFIG_ARCH_OMAP4 |
588 | OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", | ||
589 | 2, OMAP4_MPU_SOURCE); | ||
590 | #ifdef CONFIG_LOCAL_TIMERS | 595 | #ifdef CONFIG_LOCAL_TIMERS |
591 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); | 596 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); |
592 | void __init omap4_local_timer_init(void) | 597 | void __init omap4_local_timer_init(void) |
@@ -615,13 +620,11 @@ void __init omap4_local_timer_init(void) | |||
615 | #endif /* CONFIG_ARCH_OMAP4 */ | 620 | #endif /* CONFIG_ARCH_OMAP4 */ |
616 | 621 | ||
617 | #ifdef CONFIG_SOC_OMAP5 | 622 | #ifdef CONFIG_SOC_OMAP5 |
618 | OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon", | ||
619 | 2, OMAP4_MPU_SOURCE); | ||
620 | void __init omap5_realtime_timer_init(void) | 623 | void __init omap5_realtime_timer_init(void) |
621 | { | 624 | { |
622 | int err; | 625 | int err; |
623 | 626 | ||
624 | omap5_sync32k_timer_init(); | 627 | omap4_sync32k_timer_init(); |
625 | realtime_counter_init(); | 628 | realtime_counter_init(); |
626 | 629 | ||
627 | err = arch_timer_of_register(); | 630 | err = arch_timer_of_register(); |
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c index 3cdc1bb8254c..6d29e6a39540 100644 --- a/arch/arm/mach-tegra/board-harmony-pcie.c +++ b/arch/arm/mach-tegra/board-harmony-pcie.c | |||
@@ -56,9 +56,9 @@ int __init harmony_pcie_init(void) | |||
56 | gpio_direction_output(en_vdd_1v05, 1); | 56 | gpio_direction_output(en_vdd_1v05, 1); |
57 | 57 | ||
58 | regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk"); | 58 | regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk"); |
59 | if (IS_ERR_OR_NULL(regulator)) { | 59 | if (IS_ERR(regulator)) { |
60 | pr_err("%s: regulator_get failed: %d\n", __func__, | 60 | err = PTR_ERR(regulator); |
61 | (int)PTR_ERR(regulator)); | 61 | pr_err("%s: regulator_get failed: %d\n", __func__, err); |
62 | goto err_reg; | 62 | goto err_reg; |
63 | } | 63 | } |
64 | 64 | ||
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c index ce7ce42a1ac9..9e8bdfa2b369 100644 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ b/arch/arm/mach-tegra/tegra2_emc.c | |||
@@ -276,7 +276,7 @@ static struct tegra_emc_pdata *tegra_emc_fill_pdata(struct platform_device *pdev | |||
276 | int i; | 276 | int i; |
277 | 277 | ||
278 | WARN_ON(pdev->dev.platform_data); | 278 | WARN_ON(pdev->dev.platform_data); |
279 | BUG_ON(IS_ERR_OR_NULL(c)); | 279 | BUG_ON(IS_ERR(c)); |
280 | 280 | ||
281 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | 281 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
282 | pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables), | 282 | pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables), |
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index 537870d3fea8..002da9a369d5 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
@@ -140,14 +140,13 @@ struct device * __init ux500_soc_device_init(const char *soc_id) | |||
140 | soc_info_populate(soc_dev_attr, soc_id); | 140 | soc_info_populate(soc_dev_attr, soc_id); |
141 | 141 | ||
142 | soc_dev = soc_device_register(soc_dev_attr); | 142 | soc_dev = soc_device_register(soc_dev_attr); |
143 | if (IS_ERR_OR_NULL(soc_dev)) { | 143 | if (IS_ERR(soc_dev)) { |
144 | kfree(soc_dev_attr); | 144 | kfree(soc_dev_attr); |
145 | return NULL; | 145 | return NULL; |
146 | } | 146 | } |
147 | 147 | ||
148 | parent = soc_device_to_device(soc_dev); | 148 | parent = soc_device_to_device(soc_dev); |
149 | if (!IS_ERR_OR_NULL(parent)) | 149 | device_create_file(parent, &ux500_soc_attr); |
150 | device_create_file(parent, &ux500_soc_attr); | ||
151 | 150 | ||
152 | return parent; | 151 | return parent; |
153 | } | 152 | } |
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index a0daa2fb5de6..e6dbc8dbe6a6 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
@@ -140,8 +140,7 @@ static int omap_dm_timer_prepare(struct omap_dm_timer *timer) | |||
140 | */ | 140 | */ |
141 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | 141 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
142 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | 142 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); |
143 | if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) { | 143 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
144 | timer->fclk = NULL; | ||
145 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); | 144 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
146 | return -EINVAL; | 145 | return -EINVAL; |
147 | } | 146 | } |
@@ -373,7 +372,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); | |||
373 | 372 | ||
374 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | 373 | struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
375 | { | 374 | { |
376 | if (timer) | 375 | if (timer && !IS_ERR(timer->fclk)) |
377 | return timer->fclk; | 376 | return timer->fclk; |
378 | return NULL; | 377 | return NULL; |
379 | } | 378 | } |
@@ -482,7 +481,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) | |||
482 | if (pdata && pdata->set_timer_src) | 481 | if (pdata && pdata->set_timer_src) |
483 | return pdata->set_timer_src(timer->pdev, source); | 482 | return pdata->set_timer_src(timer->pdev, source); |
484 | 483 | ||
485 | if (!timer->fclk) | 484 | if (IS_ERR(timer->fclk)) |
486 | return -EINVAL; | 485 | return -EINVAL; |
487 | 486 | ||
488 | switch (source) { | 487 | switch (source) { |
@@ -500,13 +499,13 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) | |||
500 | } | 499 | } |
501 | 500 | ||
502 | parent = clk_get(&timer->pdev->dev, parent_name); | 501 | parent = clk_get(&timer->pdev->dev, parent_name); |
503 | if (IS_ERR_OR_NULL(parent)) { | 502 | if (IS_ERR(parent)) { |
504 | pr_err("%s: %s not found\n", __func__, parent_name); | 503 | pr_err("%s: %s not found\n", __func__, parent_name); |
505 | return -EINVAL; | 504 | return -EINVAL; |
506 | } | 505 | } |
507 | 506 | ||
508 | ret = clk_set_parent(timer->fclk, parent); | 507 | ret = clk_set_parent(timer->fclk, parent); |
509 | if (IS_ERR_VALUE(ret)) | 508 | if (ret < 0) |
510 | pr_err("%s: failed to set %s as parent\n", __func__, | 509 | pr_err("%s: failed to set %s as parent\n", __func__, |
511 | parent_name); | 510 | parent_name); |
512 | 511 | ||
@@ -808,6 +807,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev) | |||
808 | return -ENOMEM; | 807 | return -ENOMEM; |
809 | } | 808 | } |
810 | 809 | ||
810 | timer->fclk = ERR_PTR(-ENODEV); | ||
811 | timer->io_base = devm_ioremap_resource(dev, mem); | 811 | timer->io_base = devm_ioremap_resource(dev, mem); |
812 | if (IS_ERR(timer->io_base)) | 812 | if (IS_ERR(timer->io_base)) |
813 | return PTR_ERR(timer->io_base); | 813 | return PTR_ERR(timer->io_base); |