1 files changed, 35 insertions, 19 deletions

diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index f888e0e57dc8..32dfe08023a4 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -7,15 +7,12 @@
 #include <plat/board.h>
 
 #define OMAP3_HS_USB_PORTS      3
-enum ehci_hcd_omap_mode {
-        EHCI_HCD_OMAP_MODE_UNKNOWN,
-        EHCI_HCD_OMAP_MODE_PHY,
-        EHCI_HCD_OMAP_MODE_TLL,
-        EHCI_HCD_OMAP_MODE_HSIC,
-};
 
-enum ohci_omap3_port_mode {
-        OMAP_OHCI_PORT_MODE_UNUSED,
+enum usbhs_omap_port_mode {
+        OMAP_USBHS_PORT_MODE_UNUSED,
+        OMAP_EHCI_PORT_MODE_PHY,
+        OMAP_EHCI_PORT_MODE_TLL,
+        OMAP_EHCI_PORT_MODE_HSIC,
         OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
         OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
         OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
@@ -25,24 +22,45 @@ enum ohci_omap3_port_mode {
         OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
         OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
         OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
-        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM,
+        OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
 };
 
-struct ehci_hcd_omap_platform_data {
-        enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
-        unsigned                        phy_reset:1;
+struct usbhs_omap_board_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
 
         /* have to be valid if phy_reset is true and portx is in phy mode */
         int     reset_gpio_port[OMAP3_HS_USB_PORTS];
+
+        /* Set this to true for ES2.x silicon */
+        unsigned                        es2_compatibility:1;
+
+        unsigned                        phy_reset:1;
+
+        /*
+         * Regulators for USB PHYs.
+         * Each PHY can have a separate regulator.
+         */
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
 };
 
-struct ohci_hcd_omap_platform_data {
-        enum ohci_omap3_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+struct ehci_hcd_omap_platform_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
+        int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
+        struct regulator                *regulator[OMAP3_HS_USB_PORTS];
+        unsigned                        phy_reset:1;
+};
 
-        /* Set this to true for ES2.x silicon */
+struct ohci_hcd_omap_platform_data {
+        enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
         unsigned                        es2_compatibility:1;
 };
 
+struct usbhs_omap_platform_data {
+        enum usbhs_omap_port_mode               port_mode[OMAP3_HS_USB_PORTS];
+
+        struct ehci_hcd_omap_platform_data      *ehci_data;
+        struct ohci_hcd_omap_platform_data      *ohci_data;
+};
 /*-------------------------------------------------------------------------*/
 
 #define OMAP1_OTG_BASE                  0xfffb0400
@@ -80,19 +98,17 @@ enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
 
 extern void usb_musb_init(struct omap_musb_board_data *board_data);
 
-extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
+extern void usb_ehci_init(const struct usbhs_omap_board_data *pdata);
 
-extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
+extern void usb_ohci_init(const struct usbhs_omap_board_data *pdata);
 
 extern int omap4430_phy_power(struct device *dev, int ID, int on);
 extern int omap4430_phy_set_clk(struct device *dev, int on);
 extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
 extern int omap4430_phy_suspend(struct device *dev, int suspend);
-
 #endif
 
-
 /*
  * FIXME correct answer depends on hmc_mode,
  * as does (on omap1) any nonzero value for config->otg port number