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-rw-r--r--arch/arm/plat-nomadik/Kconfig1
-rw-r--r--arch/arm/plat-nomadik/gpio.c52
-rw-r--r--arch/arm/plat-nomadik/include/plat/pincfg.h70
-rw-r--r--arch/arm/plat-nomadik/timer.c80
4 files changed, 112 insertions, 91 deletions
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index 5da3f97c537b..187f4e84bb22 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -14,6 +14,7 @@ if PLAT_NOMADIK
14 14
15config HAS_MTU 15config HAS_MTU
16 bool 16 bool
17 select HAVE_SCHED_CLOCK
17 help 18 help
18 Support for Multi Timer Unit. MTU provides access 19 Support for Multi Timer Unit. MTU provides access
19 to multiple interrupt generating programmable 20 to multiple interrupt generating programmable
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 85e6fd212a41..eda4e3a11a3d 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -119,7 +119,7 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
119} 119}
120 120
121static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, 121static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
122 pin_cfg_t cfg) 122 pin_cfg_t cfg, bool sleep)
123{ 123{
124 static const char *afnames[] = { 124 static const char *afnames[] = {
125 [NMK_GPIO_ALT_GPIO] = "GPIO", 125 [NMK_GPIO_ALT_GPIO] = "GPIO",
@@ -145,11 +145,34 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
145 int output = PIN_DIR(cfg); 145 int output = PIN_DIR(cfg);
146 int val = PIN_VAL(cfg); 146 int val = PIN_VAL(cfg);
147 147
148 dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n", 148 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
149 pin, afnames[af], pullnames[pull], slpmnames[slpm], 149 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
150 output ? "output " : "input", 150 output ? "output " : "input",
151 output ? (val ? "high" : "low") : ""); 151 output ? (val ? "high" : "low") : "");
152 152
153 if (sleep) {
154 int slpm_pull = PIN_SLPM_PULL(cfg);
155 int slpm_output = PIN_SLPM_DIR(cfg);
156 int slpm_val = PIN_SLPM_VAL(cfg);
157
158 /*
159 * The SLPM_* values are normal values + 1 to allow zero to
160 * mean "same as normal".
161 */
162 if (slpm_pull)
163 pull = slpm_pull - 1;
164 if (slpm_output)
165 output = slpm_output - 1;
166 if (slpm_val)
167 val = slpm_val - 1;
168
169 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
170 pin,
171 slpm_pull ? pullnames[pull] : "same",
172 slpm_output ? (output ? "output" : "input") : "same",
173 slpm_val ? (val ? "high" : "low") : "same");
174 }
175
153 if (output) 176 if (output)
154 __nmk_gpio_make_output(nmk_chip, offset, val); 177 __nmk_gpio_make_output(nmk_chip, offset, val);
155 else { 178 else {
@@ -175,7 +198,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
175 * side-effects. The gpio can be manipulated later using standard GPIO API 198 * side-effects. The gpio can be manipulated later using standard GPIO API
176 * calls. 199 * calls.
177 */ 200 */
178int nmk_config_pin(pin_cfg_t cfg) 201int nmk_config_pin(pin_cfg_t cfg, bool sleep)
179{ 202{
180 struct nmk_gpio_chip *nmk_chip; 203 struct nmk_gpio_chip *nmk_chip;
181 int gpio = PIN_NUM(cfg); 204 int gpio = PIN_NUM(cfg);
@@ -186,7 +209,7 @@ int nmk_config_pin(pin_cfg_t cfg)
186 return -EINVAL; 209 return -EINVAL;
187 210
188 spin_lock_irqsave(&nmk_chip->lock, flags); 211 spin_lock_irqsave(&nmk_chip->lock, flags);
189 __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg); 212 __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
190 spin_unlock_irqrestore(&nmk_chip->lock, flags); 213 spin_unlock_irqrestore(&nmk_chip->lock, flags);
191 214
192 return 0; 215 return 0;
@@ -207,7 +230,7 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num)
207 int i; 230 int i;
208 231
209 for (i = 0; i < num; i++) { 232 for (i = 0; i < num; i++) {
210 int ret = nmk_config_pin(cfgs[i]); 233 ret = nmk_config_pin(cfgs[i], false);
211 if (ret) 234 if (ret)
212 break; 235 break;
213 } 236 }
@@ -216,6 +239,21 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num)
216} 239}
217EXPORT_SYMBOL(nmk_config_pins); 240EXPORT_SYMBOL(nmk_config_pins);
218 241
242int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
243{
244 int ret = 0;
245 int i;
246
247 for (i = 0; i < num; i++) {
248 ret = nmk_config_pin(cfgs[i], true);
249 if (ret)
250 break;
251 }
252
253 return ret;
254}
255EXPORT_SYMBOL(nmk_config_pins_sleep);
256
219/** 257/**
220 * nmk_gpio_set_slpm() - configure the sleep mode of a pin 258 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
221 * @gpio: pin number 259 * @gpio: pin number
@@ -634,7 +672,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
634 672
635 chip = &nmk_chip->chip; 673 chip = &nmk_chip->chip;
636 chip->base = pdata->first_gpio; 674 chip->base = pdata->first_gpio;
637 chip->label = pdata->name; 675 chip->label = pdata->name ?: dev_name(&dev->dev);
638 chip->dev = &dev->dev; 676 chip->dev = &dev->dev;
639 chip->owner = THIS_MODULE; 677 chip->owner = THIS_MODULE;
640 678
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 8c5ae3f2acf8..05a3936ae6d1 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -19,16 +19,22 @@
19 * bit 9..10 - Alternate Function Selection 19 * bit 9..10 - Alternate Function Selection
20 * bit 11..12 - Pull up/down state 20 * bit 11..12 - Pull up/down state
21 * bit 13 - Sleep mode behaviour 21 * bit 13 - Sleep mode behaviour
22 * bit 14 - (sleep mode) Direction 22 * bit 14 - Direction
23 * bit 15 - (sleep mode) Value (if output) 23 * bit 15 - Value (if output)
24 * bit 16..18 - SLPM pull up/down state
25 * bit 19..20 - SLPM direction
26 * bit 21..22 - SLPM Value (if output)
24 * 27 *
25 * to facilitate the definition, the following macros are provided 28 * to facilitate the definition, the following macros are provided
26 * 29 *
27 * PIN_CFG_DEFAULT - default config (0): 30 * PIN_CFG_DEFAULT - default config (0):
28 * pull up/down = disabled 31 * pull up/down = disabled
29 * sleep mode = input/wakeup 32 * sleep mode = input/wakeup
30 * (sleep mode) direction = input 33 * direction = input
31 * (sleep mode) value = low 34 * value = low
35 * SLPM direction = same as normal
36 * SLPM pull = same as normal
37 * SLPM value = same as normal
32 * 38 *
33 * PIN_CFG - default config with alternate function 39 * PIN_CFG - default config with alternate function
34 * PIN_CFG_PULL - default config with alternate function and pull up/down 40 * PIN_CFG_PULL - default config with alternate function and pull up/down
@@ -75,30 +81,64 @@ typedef unsigned long pin_cfg_t;
75#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) 81#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
76#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) 82#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
77 83
78/* Shortcuts. Use these instead of separate DIR and VAL. */ 84#define PIN_SLPM_PULL_SHIFT 16
79#define PIN_INPUT PIN_DIR_INPUT 85#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
86#define PIN_SLPM_PULL(x) \
87 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
88#define PIN_SLPM_PULL_NONE \
89 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
90#define PIN_SLPM_PULL_UP \
91 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
92#define PIN_SLPM_PULL_DOWN \
93 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
94
95#define PIN_SLPM_DIR_SHIFT 19
96#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
97#define PIN_SLPM_DIR(x) \
98 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
99#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
100#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
101
102#define PIN_SLPM_VAL_SHIFT 21
103#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
104#define PIN_SLPM_VAL(x) \
105 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
106#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
107#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
108
109/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
110#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
111#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
112#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
80#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) 113#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
81#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) 114#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
82 115
83/* 116#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
84 * These are the same as the ones above, but should make more sense to the 117#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
85 * reader when seen along with a setting a pin to AF mode. 118#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
86 */ 119#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
87#define PIN_SLPM_INPUT PIN_INPUT 120#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
88#define PIN_SLPM_OUTPUT_LOW PIN_OUTPUT_LOW
89#define PIN_SLPM_OUTPUT_HIGH PIN_OUTPUT_HIGH
90 121
91#define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) 122#define PIN_CFG_DEFAULT (0)
92 123
93#define PIN_CFG(num, alt) \ 124#define PIN_CFG(num, alt) \
94 (PIN_CFG_DEFAULT |\ 125 (PIN_CFG_DEFAULT |\
95 (PIN_NUM(num) | PIN_##alt)) 126 (PIN_NUM(num) | PIN_##alt))
96 127
128#define PIN_CFG_INPUT(num, alt, pull) \
129 (PIN_CFG_DEFAULT |\
130 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
131
132#define PIN_CFG_OUTPUT(num, alt, val) \
133 (PIN_CFG_DEFAULT |\
134 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
135
97#define PIN_CFG_PULL(num, alt, pull) \ 136#define PIN_CFG_PULL(num, alt, pull) \
98 ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ 137 ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
99 (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) 138 (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
100 139
101extern int nmk_config_pin(pin_cfg_t cfg); 140extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
102extern int nmk_config_pins(pin_cfg_t *cfgs, int num); 141extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
142extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
103 143
104#endif 144#endif
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 63cdc6025bd7..41723402006b 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -17,9 +17,9 @@
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/jiffies.h> 18#include <linux/jiffies.h>
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/cnt32_to_63.h> 20#include <linux/sched.h>
21#include <linux/timer.h>
22#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/sched_clock.h>
23 23
24#include <plat/mtu.h> 24#include <plat/mtu.h>
25 25
@@ -52,81 +52,24 @@ static struct clocksource nmdk_clksrc = {
52 * Override the global weak sched_clock symbol with this 52 * Override the global weak sched_clock symbol with this
53 * local implementation which uses the clocksource to get some 53 * local implementation which uses the clocksource to get some
54 * better resolution when scheduling the kernel. 54 * better resolution when scheduling the kernel.
55 *
56 * Because the hardware timer period may be quite short
57 * (32.3 secs on the 133 MHz MTU timer selection on ux500)
58 * and because cnt32_to_63() needs to be called at least once per
59 * half period to work properly, a kernel keepwarm() timer is set up
60 * to ensure this requirement is always met.
61 *
62 * Also the sched_clock timer will wrap around at some point,
63 * here we set it to run continously for a year.
64 */ 55 */
65#define SCHED_CLOCK_MIN_WRAP 3600*24*365 56static DEFINE_CLOCK_DATA(cd);
66static struct timer_list cnt32_to_63_keepwarm_timer;
67static u32 sched_mult;
68static u32 sched_shift;
69 57
70unsigned long long notrace sched_clock(void) 58unsigned long long notrace sched_clock(void)
71{ 59{
72 u64 cycles; 60 u32 cyc;
73 61
74 if (unlikely(!mtu_base)) 62 if (unlikely(!mtu_base))
75 return 0; 63 return 0;
76 64
77 cycles = cnt32_to_63(-readl(mtu_base + MTU_VAL(0))); 65 cyc = -readl(mtu_base + MTU_VAL(0));
78 /* 66 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
79 * sched_mult is guaranteed to be even so will
80 * shift out bit 63
81 */
82 return (cycles * sched_mult) >> sched_shift;
83} 67}
84 68
85/* Just kick sched_clock every so often */ 69static void notrace nomadik_update_sched_clock(void)
86static void cnt32_to_63_keepwarm(unsigned long data)
87{ 70{
88 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); 71 u32 cyc = -readl(mtu_base + MTU_VAL(0));
89 (void) sched_clock(); 72 update_sched_clock(&cd, cyc, (u32)~0);
90}
91
92/*
93 * Set up a timer to keep sched_clock():s 32_to_63 algorithm warm
94 * once in half a 32bit timer wrap interval.
95 */
96static void __init nmdk_sched_clock_init(unsigned long rate)
97{
98 u32 v;
99 unsigned long delta;
100 u64 days;
101
102 /* Find the apropriate mult and shift factors */
103 clocks_calc_mult_shift(&sched_mult, &sched_shift,
104 rate, NSEC_PER_SEC, SCHED_CLOCK_MIN_WRAP);
105 /* We need to multiply by an even number to get rid of bit 63 */
106 if (sched_mult & 1)
107 sched_mult++;
108
109 /* Let's see what we get, take max counter and scale it */
110 days = (0xFFFFFFFFFFFFFFFFLLU * sched_mult) >> sched_shift;
111 do_div(days, NSEC_PER_SEC);
112 do_div(days, (3600*24));
113
114 pr_info("sched_clock: using %d bits @ %lu Hz wrap in %lu days\n",
115 (64 - sched_shift), rate, (unsigned long) days);
116
117 /*
118 * Program a timer to kick us at half 32bit wraparound
119 * Formula: seconds per wrap = (2^32) / f
120 */
121 v = 0xFFFFFFFFUL / rate;
122 /* We want half of the wrap time to keep cnt32_to_63 warm */
123 v /= 2;
124 pr_debug("sched_clock: prescaled timer rate: %lu Hz, "
125 "initialize keepwarm timer every %d seconds\n", rate, v);
126 /* Convert seconds to jiffies */
127 delta = msecs_to_jiffies(v*1000);
128 setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, delta);
129 mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + delta));
130} 73}
131 74
132/* Clockevent device: use one-shot mode */ 75/* Clockevent device: use one-shot mode */
@@ -222,7 +165,6 @@ void __init nmdk_timer_init(void)
222 } else { 165 } else {
223 cr |= MTU_CRn_PRESCALE_1; 166 cr |= MTU_CRn_PRESCALE_1;
224 } 167 }
225 clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
226 168
227 /* Timer 0 is the free running clocksource */ 169 /* Timer 0 is the free running clocksource */
228 writel(cr, mtu_base + MTU_CR(0)); 170 writel(cr, mtu_base + MTU_CR(0));
@@ -233,11 +175,11 @@ void __init nmdk_timer_init(void)
233 /* Now the clock source is ready */ 175 /* Now the clock source is ready */
234 nmdk_clksrc.read = nmdk_read_timer; 176 nmdk_clksrc.read = nmdk_read_timer;
235 177
236 if (clocksource_register(&nmdk_clksrc)) 178 if (clocksource_register_hz(&nmdk_clksrc, rate))
237 pr_err("timer: failed to initialize clock source %s\n", 179 pr_err("timer: failed to initialize clock source %s\n",
238 nmdk_clksrc.name); 180 nmdk_clksrc.name);
239 181
240 nmdk_sched_clock_init(rate); 182 init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
241 183
242 /* Timer 1 is used for events */ 184 /* Timer 1 is used for events */
243 185