diff options
Diffstat (limited to 'arch/arm/plat-mxc/include/mach/mxc91231.h')
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mxc91231.h | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 0ca3101ebf36..765190fe6332 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h | |||
@@ -21,14 +21,12 @@ | |||
21 | * L2CC | 21 | * L2CC |
22 | */ | 22 | */ |
23 | #define MXC91231_L2CC_BASE_ADDR 0x30000000 | 23 | #define MXC91231_L2CC_BASE_ADDR 0x30000000 |
24 | #define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000 | ||
25 | #define MXC91231_L2CC_SIZE SZ_64K | 24 | #define MXC91231_L2CC_SIZE SZ_64K |
26 | 25 | ||
27 | /* | 26 | /* |
28 | * AIPS 1 | 27 | * AIPS 1 |
29 | */ | 28 | */ |
30 | #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 | 29 | #define MXC91231_AIPS1_BASE_ADDR 0x43F00000 |
31 | #define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
32 | #define MXC91231_AIPS1_SIZE SZ_1M | 30 | #define MXC91231_AIPS1_SIZE SZ_1M |
33 | 31 | ||
34 | #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR | 32 | #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR |
@@ -53,7 +51,6 @@ | |||
53 | * AIPS 2 | 51 | * AIPS 2 |
54 | */ | 52 | */ |
55 | #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 | 53 | #define MXC91231_AIPS2_BASE_ADDR 0x53F00000 |
56 | #define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000 | ||
57 | #define MXC91231_AIPS2_SIZE SZ_1M | 54 | #define MXC91231_AIPS2_SIZE SZ_1M |
58 | 55 | ||
59 | #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) | 56 | #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) |
@@ -79,7 +76,6 @@ | |||
79 | * SPBA global module 0 | 76 | * SPBA global module 0 |
80 | */ | 77 | */ |
81 | #define MXC91231_SPBA0_BASE_ADDR 0x50000000 | 78 | #define MXC91231_SPBA0_BASE_ADDR 0x50000000 |
82 | #define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000 | ||
83 | #define MXC91231_SPBA0_SIZE SZ_1M | 79 | #define MXC91231_SPBA0_SIZE SZ_1M |
84 | 80 | ||
85 | #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) | 81 | #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) |
@@ -109,7 +105,6 @@ | |||
109 | * SPBA global module 1 | 105 | * SPBA global module 1 |
110 | */ | 106 | */ |
111 | #define MXC91231_SPBA1_BASE_ADDR 0x52000000 | 107 | #define MXC91231_SPBA1_BASE_ADDR 0x52000000 |
112 | #define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000 | ||
113 | #define MXC91231_SPBA1_SIZE SZ_1M | 108 | #define MXC91231_SPBA1_SIZE SZ_1M |
114 | 109 | ||
115 | #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) | 110 | #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) |
@@ -144,18 +139,15 @@ | |||
144 | * ROMP and AVIC | 139 | * ROMP and AVIC |
145 | */ | 140 | */ |
146 | #define MXC91231_ROMP_BASE_ADDR 0x60000000 | 141 | #define MXC91231_ROMP_BASE_ADDR 0x60000000 |
147 | #define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000 | ||
148 | #define MXC91231_ROMP_SIZE SZ_64K | 142 | #define MXC91231_ROMP_SIZE SZ_64K |
149 | 143 | ||
150 | #define MXC91231_AVIC_BASE_ADDR 0x68000000 | 144 | #define MXC91231_AVIC_BASE_ADDR 0x68000000 |
151 | #define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000 | ||
152 | #define MXC91231_AVIC_SIZE SZ_64K | 145 | #define MXC91231_AVIC_SIZE SZ_64K |
153 | 146 | ||
154 | /* | 147 | /* |
155 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 148 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
156 | */ | 149 | */ |
157 | #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 | 150 | #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 |
158 | #define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000 | ||
159 | #define MXC91231_X_MEMC_SIZE SZ_64K | 151 | #define MXC91231_X_MEMC_SIZE SZ_64K |
160 | 152 | ||
161 | #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) | 153 | #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) |
@@ -183,19 +175,10 @@ | |||
183 | /* | 175 | /* |
184 | * This macro defines the physical to virtual address mapping for all the | 176 | * This macro defines the physical to virtual address mapping for all the |
185 | * peripheral modules. It is used by passing in the physical address as x | 177 | * peripheral modules. It is used by passing in the physical address as x |
186 | * and returning the virtual address. If the physical address is not mapped, | 178 | * and returning the virtual address. |
187 | * it returns 0. | ||
188 | */ | 179 | */ |
189 | 180 | #define MXC91231_IO_P2V(x) IMX_IO_P2V(x) | |
190 | #define MXC91231_IO_ADDRESS(x) ( \ | 181 | #define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x)) |
191 | IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ | ||
192 | IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ | ||
193 | IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ | ||
194 | IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ | ||
195 | IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ | ||
196 | IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ | ||
197 | IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ | ||
198 | IMX_IO_ADDRESS(x, MXC91231_AIPS2)) | ||
199 | 182 | ||
200 | /* | 183 | /* |
201 | * Interrupt numbers | 184 | * Interrupt numbers |