1 files changed, 17 insertions, 70 deletions

diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 61cfe827498b..79e7fc01bb59 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -15,7 +15,6 @@
 #define MX31_L2CC_SIZE                  SZ_1M
 
 #define MX31_AIPS1_BASE_ADDR            0x43f00000
-#define MX31_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX31_AIPS1_SIZE                 SZ_1M
 #define MX31_MAX_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x04000)
 #define MX31_EVTMON_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x08000)
@@ -25,7 +24,10 @@
 #define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
 #define MX31_I2C1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
 #define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_OTG_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_USB_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_USB_OTG_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0000)
+#define MX31_USB_HS1_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0200)
+#define MX31_USB_HS2_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0400)
 #define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
 #define MX31_UART1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x90000)
 #define MX31_UART2_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x94000)
@@ -41,10 +43,9 @@
 #define MX31_ECT_IP2_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xbc000)
 
 #define MX31_SPBA0_BASE_ADDR            0x50000000
-#define MX31_SPBA0_BASE_ADDR_VIRT       0xfc100000
 #define MX31_SPBA0_SIZE                 SZ_1M
-#define MX31_MMC_SDHC1_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_MMC_SDHC2_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_SDHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x04000)
+#define MX31_SDHC2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x08000)
 #define MX31_UART3_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x0c000)
 #define MX31_CSPI2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x10000)
 #define MX31_SSI2_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x14000)
@@ -55,7 +56,6 @@
 #define MX31_SPBA_CTRL_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x3c000)
 
 #define MX31_AIPS2_BASE_ADDR            0x53f00000
-#define MX31_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX31_AIPS2_SIZE                 SZ_1M
 #define MX31_CCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0x80000)
 #define MX31_CSPI3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x84000)
@@ -84,7 +84,6 @@
 #define MX31_ROMP_SIZE                  SZ_1M
 
 #define MX31_AVIC_BASE_ADDR             0x68000000
-#define MX31_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX31_AVIC_SIZE                  SZ_1M
 
 #define MX31_IPU_MEM_BASE_ADDR          0x70000000
@@ -97,15 +96,14 @@
 #define MX31_CS3_BASE_ADDR              0xb2000000
 
 #define MX31_CS4_BASE_ADDR              0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX31_CS4_BASE_ADDR_VIRT         0xf6000000
 #define MX31_CS4_SIZE                   SZ_32M
 
 #define MX31_CS5_BASE_ADDR              0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS5_BASE_ADDR_VIRT         0xf8000000
 #define MX31_CS5_SIZE                   SZ_32M
 
 #define MX31_X_MEMC_BASE_ADDR           0xb8000000
-#define MX31_X_MEMC_BASE_ADDR_VIRT      0xfc320000
 #define MX31_X_MEMC_SIZE                SZ_64K
 #define MX31_NFC_BASE_ADDR                      (MX31_X_MEMC_BASE_ADDR + 0x0000)
 #define MX31_ESDCTL_BASE_ADDR                   (MX31_X_MEMC_BASE_ADDR + 0x1000)
@@ -121,12 +119,8 @@
 
 #define MX31_PCMCIA_MEM_BASE_ADDR       0xbc000000
 
-#define MX31_IO_ADDRESS(x) (                                            \
-        IMX_IO_ADDRESS(x, MX31_AIPS1) ?:                                \
-        IMX_IO_ADDRESS(x, MX31_AIPS2) ?:                                \
-        IMX_IO_ADDRESS(x, MX31_AVIC) ?:                                 \
-        IMX_IO_ADDRESS(x, MX31_X_MEMC) ?:                               \
-        IMX_IO_ADDRESS(x, MX31_SPBA0))
+#define MX31_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX31_IO_ADDRESS(x)              IOMEM(MX31_IO_P2V(x))
 
 #ifndef __ASSEMBLER__
 static inline void mx31_setup_weimcs(size_t cs,
@@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_MPEG4_ENCODER  5
 #define MX31_INT_RTIC           6
 #define MX31_INT_FIRI           7
-#define MX31_INT_MMC_SDHC2      8
-#define MX31_INT_MMC_SDHC1      9
+#define MX31_INT_SDHC2          8
+#define MX31_INT_SDHC1          9
 #define MX31_INT_I2C1           10
 #define MX31_INT_SSI2           11
 #define MX31_INT_SSI1           12
@@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_UART2          32
 #define MX31_INT_NFC            33
 #define MX31_INT_SDMA           34
-#define MX31_INT_USB1           35
-#define MX31_INT_USB2           36
-#define MX31_INT_USB3           37
-#define MX31_INT_USB4           38
+#define MX31_INT_USB_HS1        35
+#define MX31_INT_USB_HS2        36
+#define MX31_INT_USB_OTG        37
 #define MX31_INT_MSHC1          39
 #define MX31_INT_MSHC2          40
 #define MX31_INT_IPU_ERR        41
@@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_EXT_WDOG       62
 #define MX31_INT_EXT_TV         63
 
+#define MX31_DMA_REQ_SDHC1      20
+#define MX31_DMA_REQ_SDHC2      21
 #define MX31_DMA_REQ_SSI2_RX1   22
 #define MX31_DMA_REQ_SSI2_TX1   23
 #define MX31_DMA_REQ_SSI2_RX0   24
@@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs,
 
 #define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
-#define MX31_CHIP_REV_1_0               0x10
-#define MX31_CHIP_REV_1_1               0x11
-#define MX31_CHIP_REV_1_2               0x12
-#define MX31_CHIP_REV_1_3               0x13
-#define MX31_CHIP_REV_2_0               0x20
-#define MX31_CHIP_REV_2_1               0x21
-#define MX31_CHIP_REV_2_2               0x22
-#define MX31_CHIP_REV_2_3               0x23
-#define MX31_CHIP_REV_3_0               0x30
-#define MX31_CHIP_REV_3_1               0x31
-#define MX31_CHIP_REV_3_2               0x32
-
-#define MX31_SYSTEM_REV_MIN             MX31_CHIP_REV_1_0
-#define MX31_SYSTEM_REV_NUM             3
-
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
-#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
-#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
-#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
-#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
-#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
-#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
-#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
-#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
-#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
-#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
-#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
-#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
-#define MXC_INT_FIRI MX31_INT_FIRI
-#define MXC_INT_MBX MX31_INT_MBX
-#define MXC_INT_CSPI3 MX31_INT_CSPI3
-#define MXC_INT_SIM2 MX31_INT_SIM2
-#define MXC_INT_SIM1 MX31_INT_SIM1
-#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
-#define MXC_INT_USB1 MX31_INT_USB1
-#define MXC_INT_USB2 MX31_INT_USB2
-#define MXC_INT_USB3 MX31_INT_USB3
-#define MXC_INT_USB4 MX31_INT_USB4
-#define MXC_INT_MSHC2 MX31_INT_MSHC2
-#define MXC_INT_UART4 MX31_INT_UART4
-#define MXC_INT_UART5 MX31_INT_UART5
-#define MXC_INT_CCM MX31_INT_CCM
-#define MXC_INT_PCMCIA MX31_INT_PCMCIA
-#endif
-
 #endif /* ifndef __MACH_MX31_H__ */