1 files changed, 90 insertions, 4 deletions
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index ebadf4ac43fc..26bb1bab4aeb 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,13 +22,92 @@
 #include <asm/sizes.h>
-#define IMX_IO_ADDRESS(addr, module)                                    \
+#ifdef __ASSEMBLER__
-        ((void __force __iomem *)                                       \
+#define IOMEM(addr)     (addr)
-         (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
+#else
-         (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
+#define IOMEM(addr)     ((void __force __iomem *)(addr))
+#endif
+#define IMX_IO_P2V_MODULE(addr, module)                                 \
+        (((addr) - module ## _BASE_ADDR) < module ## _SIZE ?            \
+         (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
+/*
+ * This is rather complicated for humans and ugly to verify, but for a machine
+ * it's OK.  Still more as it is usually only applied to constants.  The upsides
+ * on using this approach are:
+ *
+ *  - same mapping on all i.MX machines
+ *  - works for assembler, too
+ *  - no need to nurture #defines for virtual addresses
+ *
+ * The downside it, it's hard to verify (but I have a script for that).
+ *
+ * Obviously this needs to be injective for each SoC.  In general it maps the
+ * whole address space to [0xf4000000, 0xf5ffffff].  So [0xf6000000,0xfeffffff]
+ * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
+ *
+ * It applies the following mappings for the different SoCs:
+ *
+ * mx1:
+ *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
+ * mx21:
+ *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
+ * mx25:
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
+ * mx27:
+ *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
+ * mx31:
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ * mx35:
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ * mx50:
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
+ * mx51:
+ *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
+ *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
+ *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
+ *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
+ *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ * mxc91231:
+ *      L2CC    0x30000000+0x010000     ->      0xf4400000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      ROMP    0x60000000+0x010000     ->      0xf5000000+0x010000
+ *      AVIC    0x68000000+0x010000     ->      0xf5800000+0x010000
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ *      SPBA1   0x52000000+0x100000     ->      0xf5600000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ */
+#define IMX_IO_P2V(x)   (                                               \
+                        0xf4000000 +                                    \
+                        (((x) & 0x50000000) >> 6) +                     \
+                        (((x) & 0x0b000000) >> 4) +                     \
+                        (((x) & 0x000fffff)))
+#define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
 #ifdef CONFIG_ARCH_MX5
+#include <mach/mx50.h>
 #include <mach/mx51.h>
+#include <mach/mx53.h>
 #endif
 #ifdef CONFIG_ARCH_MX3
@@ -61,4 +140,11 @@
 #include <mach/mxc.h>
+#define imx_map_entry(soc, name, _type) {                               \
+        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
+        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
+        .length = soc ## _ ## name ## _SIZE,                            \
+        .type = _type,                                                  \
+}
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index ebadf4ac43fc..26bb1bab4aeb 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,13 +22,92 @@
22		22
23	#include <asm/sizes.h>	23	#include <asm/sizes.h>
24		24
25	#define IMX_IO_ADDRESS(addr, module) \	25	#ifdef __ASSEMBLER__
26	((void __force __iomem *) \	26	#define IOMEM(addr) (addr)
27	(((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\	27	#else
28	(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))	28	#define IOMEM(addr) ((void __force __iomem *)(addr))
		29	#endif
		30
		31	#define IMX_IO_P2V_MODULE(addr, module) \
		32	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
		33	(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
		34
		35	/*
		36	* This is rather complicated for humans and ugly to verify, but for a machine
		37	* it's OK. Still more as it is usually only applied to constants. The upsides
		38	* on using this approach are:
		39	*
		40	* - same mapping on all i.MX machines
		41	* - works for assembler, too
		42	* - no need to nurture #defines for virtual addresses
		43	*
		44	* The downside it, it's hard to verify (but I have a script for that).
		45	*
		46	* Obviously this needs to be injective for each SoC. In general it maps the
		47	* whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
		48	* is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
		49	*
		50	* It applies the following mappings for the different SoCs:
		51	*
		52	* mx1:
		53	* IO 0x00200000+0x100000 -> 0xf4000000+0x100000
		54	* mx21:
		55	* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
		56	* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
		57	* X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
		58	* mx25:
		59	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
		60	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
		61	* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
		62	* mx27:
		63	* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
		64	* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
		65	* X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
		66	* mx31:
		67	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
		68	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
		69	* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
		70	* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
		71	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
		72	* mx35:
		73	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
		74	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
		75	* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
		76	* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
		77	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
		78	* mx50:
		79	* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
		80	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
		81	* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
		82	* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
		83	* mx51:
		84	* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
		85	* DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
		86	* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
		87	* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
		88	* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
		89	* mxc91231:
		90	* L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
		91	* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
		92	* ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
		93	* AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
		94	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
		95	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
		96	* SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
		97	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
		98	*/
		99	#define IMX_IO_P2V(x) ( \
		100	0xf4000000 + \
		101	(((x) & 0x50000000) >> 6) + \
		102	(((x) & 0x0b000000) >> 4) + \
		103	(((x) & 0x000fffff)))
		104
		105	#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
29		106
30	#ifdef CONFIG_ARCH_MX5	107	#ifdef CONFIG_ARCH_MX5
		108	#include <mach/mx50.h>
31	#include <mach/mx51.h>	109	#include <mach/mx51.h>
		110	#include <mach/mx53.h>
32	#endif	111	#endif
33		112
34	#ifdef CONFIG_ARCH_MX3	113	#ifdef CONFIG_ARCH_MX3
@@ -61,4 +140,11 @@
61		140
62	#include <mach/mxc.h>	141	#include <mach/mxc.h>
63		142
		143	#define imx_map_entry(soc, name, _type) { \
		144	.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
		145	.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
		146	.length = soc ## _ ## name ## _SIZE, \
		147	.type = _type, \
		148	}
		149
64	#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */	150	#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */