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path: root/arch/arm/mach-sa1100/irq.c
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Diffstat (limited to 'arch/arm/mach-sa1100/irq.c')
-rw-r--r--arch/arm/mach-sa1100/irq.c87
1 files changed, 50 insertions, 37 deletions
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 63e2901db416..2dc6a2a9c60c 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -87,7 +87,7 @@ static struct irq_domain *sa1100_normal_irqdomain;
87 */ 87 */
88static int GPIO_IRQ_rising_edge; 88static int GPIO_IRQ_rising_edge;
89static int GPIO_IRQ_falling_edge; 89static int GPIO_IRQ_falling_edge;
90static int GPIO_IRQ_mask = (1 << 11) - 1; 90static int GPIO_IRQ_mask;
91 91
92static int sa1100_gpio_type(struct irq_data *d, unsigned int type) 92static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
93{ 93{
@@ -124,6 +124,26 @@ static void sa1100_gpio_ack(struct irq_data *d)
124 GEDR = BIT(d->hwirq); 124 GEDR = BIT(d->hwirq);
125} 125}
126 126
127static void sa1100_gpio_mask(struct irq_data *d)
128{
129 unsigned int mask = BIT(d->hwirq);
130
131 GPIO_IRQ_mask &= ~mask;
132
133 GRER &= ~mask;
134 GFER &= ~mask;
135}
136
137static void sa1100_gpio_unmask(struct irq_data *d)
138{
139 unsigned int mask = BIT(d->hwirq);
140
141 GPIO_IRQ_mask |= mask;
142
143 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
144 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
145}
146
127static int sa1100_gpio_wake(struct irq_data *d, unsigned int on) 147static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
128{ 148{
129 if (on) 149 if (on)
@@ -139,8 +159,8 @@ static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
139static struct irq_chip sa1100_low_gpio_chip = { 159static struct irq_chip sa1100_low_gpio_chip = {
140 .name = "GPIO-l", 160 .name = "GPIO-l",
141 .irq_ack = sa1100_gpio_ack, 161 .irq_ack = sa1100_gpio_ack,
142 .irq_mask = sa1100_mask_irq, 162 .irq_mask = sa1100_gpio_mask,
143 .irq_unmask = sa1100_unmask_irq, 163 .irq_unmask = sa1100_gpio_unmask,
144 .irq_set_type = sa1100_gpio_type, 164 .irq_set_type = sa1100_gpio_type,
145 .irq_set_wake = sa1100_gpio_wake, 165 .irq_set_wake = sa1100_gpio_wake,
146}; 166};
@@ -163,16 +183,16 @@ static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
163static struct irq_domain *sa1100_low_gpio_irqdomain; 183static struct irq_domain *sa1100_low_gpio_irqdomain;
164 184
165/* 185/*
166 * IRQ11 (GPIO11 through 27) handler. We enter here with the 186 * IRQ 0-11 (GPIO) handler. We enter here with the
167 * irq_controller_lock held, and IRQs disabled. Decode the IRQ 187 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
168 * and call the handler. 188 * and call the handler.
169 */ 189 */
170static void 190static void
171sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc) 191sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
172{ 192{
173 unsigned int mask; 193 unsigned int mask;
174 194
175 mask = GEDR & 0xfffff800; 195 mask = GEDR;
176 do { 196 do {
177 /* 197 /*
178 * clear down all currently active IRQ sources. 198 * clear down all currently active IRQ sources.
@@ -180,8 +200,7 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
180 */ 200 */
181 GEDR = mask; 201 GEDR = mask;
182 202
183 irq = IRQ_GPIO11; 203 irq = IRQ_GPIO0;
184 mask >>= 11;
185 do { 204 do {
186 if (mask & 1) 205 if (mask & 1)
187 generic_handle_irq(irq); 206 generic_handle_irq(irq);
@@ -189,7 +208,7 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
189 irq++; 208 irq++;
190 } while (mask); 209 } while (mask);
191 210
192 mask = GEDR & 0xfffff800; 211 mask = GEDR;
193 } while (mask); 212 } while (mask);
194} 213}
195 214
@@ -198,31 +217,11 @@ sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
198 * In addition, the IRQs are all collected up into one bit in the 217 * In addition, the IRQs are all collected up into one bit in the
199 * interrupt controller registers. 218 * interrupt controller registers.
200 */ 219 */
201static void sa1100_high_gpio_mask(struct irq_data *d)
202{
203 unsigned int mask = BIT(d->hwirq);
204
205 GPIO_IRQ_mask &= ~mask;
206
207 GRER &= ~mask;
208 GFER &= ~mask;
209}
210
211static void sa1100_high_gpio_unmask(struct irq_data *d)
212{
213 unsigned int mask = BIT(d->hwirq);
214
215 GPIO_IRQ_mask |= mask;
216
217 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
218 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
219}
220
221static struct irq_chip sa1100_high_gpio_chip = { 220static struct irq_chip sa1100_high_gpio_chip = {
222 .name = "GPIO-h", 221 .name = "GPIO-h",
223 .irq_ack = sa1100_gpio_ack, 222 .irq_ack = sa1100_gpio_ack,
224 .irq_mask = sa1100_high_gpio_mask, 223 .irq_mask = sa1100_gpio_mask,
225 .irq_unmask = sa1100_high_gpio_unmask, 224 .irq_unmask = sa1100_gpio_unmask,
226 .irq_set_type = sa1100_gpio_type, 225 .irq_set_type = sa1100_gpio_type,
227 .irq_set_wake = sa1100_gpio_wake, 226 .irq_set_wake = sa1100_gpio_wake,
228}; 227};
@@ -325,7 +324,7 @@ sa1100_handle_irq(struct pt_regs *regs)
325 if (mask == 0) 324 if (mask == 0)
326 break; 325 break;
327 326
328 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0, regs); 327 handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0_SC, regs);
329 } while (1); 328 } while (1);
330} 329}
331 330
@@ -350,22 +349,36 @@ void __init sa1100_init_irq(void)
350 */ 349 */
351 ICCR = 1; 350 ICCR = 1;
352 351
352 sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
353 32, IRQ_GPIO0_SC, 0,
354 &sa1100_normal_irqdomain_ops, NULL);
355
353 sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL, 356 sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
354 11, IRQ_GPIO0, 0, 357 11, IRQ_GPIO0, 0,
355 &sa1100_low_gpio_irqdomain_ops, NULL); 358 &sa1100_low_gpio_irqdomain_ops, NULL);
356 359
357 sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
358 21, IRQ_GPIO11_27, 11,
359 &sa1100_normal_irqdomain_ops, NULL);
360
361 sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL, 360 sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
362 17, IRQ_GPIO11, 11, 361 17, IRQ_GPIO11, 11,
363 &sa1100_high_gpio_irqdomain_ops, NULL); 362 &sa1100_high_gpio_irqdomain_ops, NULL);
364 363
365 /* 364 /*
365 * Install handlers for GPIO 0-10 edge detect interrupts
366 */
367 irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
368 irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
369 irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
370 irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
371 irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
372 irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
373 irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
374 irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
375 irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
376 irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
377 irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
378 /*
366 * Install handler for GPIO 11-27 edge detect interrupts 379 * Install handler for GPIO 11-27 edge detect interrupts
367 */ 380 */
368 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler); 381 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
369 382
370 set_handle_irq(sa1100_handle_irq); 383 set_handle_irq(sa1100_handle_irq);
371 384