1 files changed, 260 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 31fd26062535..e3562624ae48 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -273,6 +273,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 };
 
 /*
+ * 'gmac' class
+ * cpsw/gmac sub system
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x8,
+        .syss_offs      = 0x4,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
+                           MSTANDBY_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
+        .name           = "gmac",
+        .sysc           = &dra7xx_gmac_sysc,
+};
+
+static struct omap_hwmod dra7xx_gmac_hwmod = {
+        .name           = "gmac",
+        .class          = &dra7xx_gmac_hwmod_class,
+        .clkdm_name     = "gmac_clkdm",
+        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
+        .main_clk       = "dpll_gmac_ck",
+        .mpu_rt_idx     = 1,
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
+                        .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mdio' class
+ */
+static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
+        .name           = "davinci_mdio",
+};
+
+static struct omap_hwmod dra7xx_mdio_hwmod = {
+        .name           = "davinci_mdio",
+        .class          = &dra7xx_mdio_hwmod_class,
+        .clkdm_name     = "gmac_clkdm",
+        .main_clk       = "dpll_gmac_ck",
+};
+
+/*
  * 'dcan' class
  *
  */
@@ -1206,6 +1256,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
         },
 };
 
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+        .name           = "ocp2scp3",
+        .class          = &dra7xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+        .name   = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+        .name           = "pcie1",
+        .class          = &dra7xx_pcie_hwmod_class,
+        .clkdm_name     = "pcie_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs   = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+        .name           = "pcie2",
+        .class          = &dra7xx_pcie_hwmod_class,
+        .clkdm_name     = "pcie_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+        .name   = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+        .name           = "pcie1-phy",
+        .class          = &dra7xx_pcie_phy_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+        .name           = "pcie2-phy",
+        .class          = &dra7xx_pcie_phy_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
 /*
  * 'qspi' class
  *
@@ -1240,6 +1381,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
 };
 
 /*
+ * 'rtcss' class
+ *
+ */
+static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
+        .sysc_offs      = 0x0078,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
+        .name   = "rtcss",
+        .sysc   = &dra7xx_rtcss_sysc,
+};
+
+/* rtcss */
+static struct omap_hwmod dra7xx_rtcss_hwmod = {
+        .name           = "rtcss",
+        .class          = &dra7xx_rtcss_hwmod_class,
+        .clkdm_name     = "rtc_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
+                        .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
  * 'sata' class
  *
  */
@@ -1990,6 +2163,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
+        .master         = &dra7xx_l4_per2_hwmod,
+        .slave          = &dra7xx_gmac_hwmod,
+        .clk            = "dpll_gmac_ck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
+        .master         = &dra7xx_gmac_hwmod,
+        .slave          = &dra7xx_mdio_hwmod,
+        .user           = OCP_USER_MPU,
+};
+
 /* l4_wkup -> dcan1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
         .master         = &dra7xx_l4_wkup_hwmod,
@@ -2317,6 +2503,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_ocp2scp3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_pcie1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+        .master         = &dra7xx_l3_main_1_hwmod,
+        .slave          = &dra7xx_pcie2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie1_phy_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+        .master         = &dra7xx_l4_cfg_hwmod,
+        .slave          = &dra7xx_pcie2_phy_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
         {
                 .pa_start       = 0x4b300000,
@@ -2335,6 +2577,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_per3 -> rtcss */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
+        .master         = &dra7xx_l4_per3_hwmod,
+        .slave          = &dra7xx_rtcss_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
         {
                 .name           = "sysc",
@@ -2633,6 +2883,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_wkup__ctrl_module_wkup,
         &dra7xx_l4_wkup__dcan1,
         &dra7xx_l4_per2__dcan2,
+        &dra7xx_l4_per2__cpgmac0,
+        &dra7xx_gmac__mdio,
         &dra7xx_l4_cfg__dma_system,
         &dra7xx_l3_main_1__dss,
         &dra7xx_l3_main_1__dispc,
@@ -2663,7 +2915,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
         &dra7xx_l4_per1__mmc4,
         &dra7xx_l4_cfg__mpu,
         &dra7xx_l4_cfg__ocp2scp1,
+        &dra7xx_l4_cfg__ocp2scp3,
+        &dra7xx_l3_main_1__pcie1,
+        &dra7xx_l4_cfg__pcie1,
+        &dra7xx_l3_main_1__pcie2,
+        &dra7xx_l4_cfg__pcie2,
+        &dra7xx_l4_cfg__pcie1_phy,
+        &dra7xx_l4_cfg__pcie2_phy,
         &dra7xx_l3_main_1__qspi,
+        &dra7xx_l4_per3__rtcss,
         &dra7xx_l4_cfg__sata,
         &dra7xx_l4_cfg__smartreflex_core,
         &dra7xx_l4_cfg__smartreflex_mpu,