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Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_33xx_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c1067
1 files changed, 0 insertions, 1067 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc51026..3c7675a6a8f4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -35,29 +35,6 @@
35 */ 35 */
36 36
37/* 37/*
38 * 'emif_fw' class
39 * instance(s): emif_fw
40 */
41static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
42 .name = "emif_fw",
43};
44
45/* emif_fw */
46static struct omap_hwmod am33xx_emif_fw_hwmod = {
47 .name = "emif_fw",
48 .class = &am33xx_emif_fw_hwmod_class,
49 .clkdm_name = "l4fw_clkdm",
50 .main_clk = "l4fw_gclk",
51 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
52 .prcm = {
53 .omap4 = {
54 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
55 .modulemode = MODULEMODE_SWCTRL,
56 },
57 },
58};
59
60/*
61 * 'emif' class 38 * 'emif' class
62 * instance(s): emif 39 * instance(s): emif
63 */ 40 */
@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
70 .sysc = &am33xx_emif_sysc, 47 .sysc = &am33xx_emif_sysc,
71}; 48};
72 49
73static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
74 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
75 { .irq = -1 },
76};
77
78/* emif */ 50/* emif */
79static struct omap_hwmod am33xx_emif_hwmod = { 51static struct omap_hwmod am33xx_emif_hwmod = {
80 .name = "emif", 52 .name = "emif",
81 .class = &am33xx_emif_hwmod_class, 53 .class = &am33xx_emif_hwmod_class,
82 .clkdm_name = "l3_clkdm", 54 .clkdm_name = "l3_clkdm",
83 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 55 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
84 .mpu_irqs = am33xx_emif_irqs,
85 .main_clk = "dpll_ddr_m2_div2_ck", 56 .main_clk = "dpll_ddr_m2_div2_ck",
86 .prcm = { 57 .prcm = {
87 .omap4 = { 58 .omap4 = {
@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
99 .name = "l3", 70 .name = "l3",
100}; 71};
101 72
102/* l3_main (l3_fast) */
103static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
104 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
105 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
106 { .irq = -1 },
107};
108
109static struct omap_hwmod am33xx_l3_main_hwmod = { 73static struct omap_hwmod am33xx_l3_main_hwmod = {
110 .name = "l3_main", 74 .name = "l3_main",
111 .class = &am33xx_l3_hwmod_class, 75 .class = &am33xx_l3_hwmod_class,
112 .clkdm_name = "l3_clkdm", 76 .clkdm_name = "l3_clkdm",
113 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 77 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
114 .mpu_irqs = am33xx_l3_main_irqs,
115 .main_clk = "l3_gclk", 78 .main_clk = "l3_gclk",
116 .prcm = { 79 .prcm = {
117 .omap4 = { 80 .omap4 = {
@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
196 }, 159 },
197}; 160};
198 161
199/* l4_fw */
200static struct omap_hwmod am33xx_l4_fw_hwmod = {
201 .name = "l4_fw",
202 .class = &am33xx_l4_hwmod_class,
203 .clkdm_name = "l4fw_clkdm",
204 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
205 .prcm = {
206 .omap4 = {
207 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
208 .modulemode = MODULEMODE_SWCTRL,
209 },
210 },
211};
212
213/* 162/*
214 * 'mpu' class 163 * 'mpu' class
215 */ 164 */
@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
217 .name = "mpu", 166 .name = "mpu",
218}; 167};
219 168
220/* mpu */
221static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
222 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
223 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
224 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
225 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
226 { .irq = -1 },
227};
228
229static struct omap_hwmod am33xx_mpu_hwmod = { 169static struct omap_hwmod am33xx_mpu_hwmod = {
230 .name = "mpu", 170 .name = "mpu",
231 .class = &am33xx_mpu_hwmod_class, 171 .class = &am33xx_mpu_hwmod_class,
232 .clkdm_name = "mpu_clkdm", 172 .clkdm_name = "mpu_clkdm",
233 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
234 .mpu_irqs = am33xx_mpu_irqs,
235 .main_clk = "dpll_mpu_m2_ck", 174 .main_clk = "dpll_mpu_m2_ck",
236 .prcm = { 175 .prcm = {
237 .omap4 = { 176 .omap4 = {
@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
253 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 }, 192 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
254}; 193};
255 194
256static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
257 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
258 { .irq = -1 },
259};
260
261/* wkup_m3 */ 195/* wkup_m3 */
262static struct omap_hwmod am33xx_wkup_m3_hwmod = { 196static struct omap_hwmod am33xx_wkup_m3_hwmod = {
263 .name = "wkup_m3", 197 .name = "wkup_m3",
@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
265 .clkdm_name = "l4_wkup_aon_clkdm", 199 .clkdm_name = "l4_wkup_aon_clkdm",
266 /* Keep hardreset asserted */ 200 /* Keep hardreset asserted */
267 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST, 201 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
268 .mpu_irqs = am33xx_wkup_m3_irqs,
269 .main_clk = "dpll_core_m4_div2_ck", 202 .main_clk = "dpll_core_m4_div2_ck",
270 .prcm = { 203 .prcm = {
271 .omap4 = { 204 .omap4 = {
@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
291 { .name = "pruss", .rst_shift = 1 }, 224 { .name = "pruss", .rst_shift = 1 },
292}; 225};
293 226
294static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
295 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
296 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
297 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
298 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
299 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
300 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
301 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
302 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
303 { .irq = -1 },
304};
305
306/* pru-icss */ 227/* pru-icss */
307/* Pseudo hwmod for reset control purpose only */ 228/* Pseudo hwmod for reset control purpose only */
308static struct omap_hwmod am33xx_pruss_hwmod = { 229static struct omap_hwmod am33xx_pruss_hwmod = {
309 .name = "pruss", 230 .name = "pruss",
310 .class = &am33xx_pruss_hwmod_class, 231 .class = &am33xx_pruss_hwmod_class,
311 .clkdm_name = "pruss_ocp_clkdm", 232 .clkdm_name = "pruss_ocp_clkdm",
312 .mpu_irqs = am33xx_pruss_irqs,
313 .main_clk = "pruss_ocp_gclk", 233 .main_clk = "pruss_ocp_gclk",
314 .prcm = { 234 .prcm = {
315 .omap4 = { 235 .omap4 = {
@@ -332,16 +252,10 @@ static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
332 { .name = "gfx", .rst_shift = 0 }, 252 { .name = "gfx", .rst_shift = 0 },
333}; 253};
334 254
335static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
336 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
337 { .irq = -1 },
338};
339
340static struct omap_hwmod am33xx_gfx_hwmod = { 255static struct omap_hwmod am33xx_gfx_hwmod = {
341 .name = "gfx", 256 .name = "gfx",
342 .class = &am33xx_gfx_hwmod_class, 257 .class = &am33xx_gfx_hwmod_class,
343 .clkdm_name = "gfx_l3_clkdm", 258 .clkdm_name = "gfx_l3_clkdm",
344 .mpu_irqs = am33xx_gfx_irqs,
345 .main_clk = "gfx_fck_div_ck", 259 .main_clk = "gfx_fck_div_ck",
346 .prcm = { 260 .prcm = {
347 .omap4 = { 261 .omap4 = {
@@ -387,16 +301,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
387 .sysc = &am33xx_adc_tsc_sysc, 301 .sysc = &am33xx_adc_tsc_sysc,
388}; 302};
389 303
390static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
391 { .irq = 16 + OMAP_INTC_START, },
392 { .irq = -1 },
393};
394
395static struct omap_hwmod am33xx_adc_tsc_hwmod = { 304static struct omap_hwmod am33xx_adc_tsc_hwmod = {
396 .name = "adc_tsc", 305 .name = "adc_tsc",
397 .class = &am33xx_adc_tsc_hwmod_class, 306 .class = &am33xx_adc_tsc_hwmod_class,
398 .clkdm_name = "l4_wkup_clkdm", 307 .clkdm_name = "l4_wkup_clkdm",
399 .mpu_irqs = am33xx_adc_tsc_irqs,
400 .main_clk = "adc_tsc_fck", 308 .main_clk = "adc_tsc_fck",
401 .prcm = { 309 .prcm = {
402 .omap4 = { 310 .omap4 = {
@@ -515,23 +423,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
515 .sysc = &am33xx_aes0_sysc, 423 .sysc = &am33xx_aes0_sysc,
516}; 424};
517 425
518static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
519 { .irq = 103 + OMAP_INTC_START, },
520 { .irq = -1 },
521};
522
523static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
524 { .name = "tx", .dma_req = 6, },
525 { .name = "rx", .dma_req = 5, },
526 { .dma_req = -1 }
527};
528
529static struct omap_hwmod am33xx_aes0_hwmod = { 426static struct omap_hwmod am33xx_aes0_hwmod = {
530 .name = "aes", 427 .name = "aes",
531 .class = &am33xx_aes0_hwmod_class, 428 .class = &am33xx_aes0_hwmod_class,
532 .clkdm_name = "l3_clkdm", 429 .clkdm_name = "l3_clkdm",
533 .mpu_irqs = am33xx_aes0_irqs,
534 .sdma_reqs = am33xx_aes0_edma_reqs,
535 .main_clk = "aes0_fck", 430 .main_clk = "aes0_fck",
536 .prcm = { 431 .prcm = {
537 .omap4 = { 432 .omap4 = {
@@ -554,22 +449,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
554 .sysc = &am33xx_sha0_sysc, 449 .sysc = &am33xx_sha0_sysc,
555}; 450};
556 451
557static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
558 { .irq = 109 + OMAP_INTC_START, },
559 { .irq = -1 },
560};
561
562static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
563 { .name = "rx", .dma_req = 36, },
564 { .dma_req = -1 }
565};
566
567static struct omap_hwmod am33xx_sha0_hwmod = { 452static struct omap_hwmod am33xx_sha0_hwmod = {
568 .name = "sham", 453 .name = "sham",
569 .class = &am33xx_sha0_hwmod_class, 454 .class = &am33xx_sha0_hwmod_class,
570 .clkdm_name = "l3_clkdm", 455 .clkdm_name = "l3_clkdm",
571 .mpu_irqs = am33xx_sha0_irqs,
572 .sdma_reqs = am33xx_sha0_edma_reqs,
573 .main_clk = "l3_gclk", 456 .main_clk = "l3_gclk",
574 .prcm = { 457 .prcm = {
575 .omap4 = { 458 .omap4 = {
@@ -604,16 +487,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
604}; 487};
605 488
606/* smartreflex0 */ 489/* smartreflex0 */
607static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
608 { .irq = 120 + OMAP_INTC_START, },
609 { .irq = -1 },
610};
611
612static struct omap_hwmod am33xx_smartreflex0_hwmod = { 490static struct omap_hwmod am33xx_smartreflex0_hwmod = {
613 .name = "smartreflex0", 491 .name = "smartreflex0",
614 .class = &am33xx_smartreflex_hwmod_class, 492 .class = &am33xx_smartreflex_hwmod_class,
615 .clkdm_name = "l4_wkup_clkdm", 493 .clkdm_name = "l4_wkup_clkdm",
616 .mpu_irqs = am33xx_smartreflex0_irqs,
617 .main_clk = "smartreflex0_fck", 494 .main_clk = "smartreflex0_fck",
618 .prcm = { 495 .prcm = {
619 .omap4 = { 496 .omap4 = {
@@ -624,16 +501,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
624}; 501};
625 502
626/* smartreflex1 */ 503/* smartreflex1 */
627static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
628 { .irq = 121 + OMAP_INTC_START, },
629 { .irq = -1 },
630};
631
632static struct omap_hwmod am33xx_smartreflex1_hwmod = { 504static struct omap_hwmod am33xx_smartreflex1_hwmod = {
633 .name = "smartreflex1", 505 .name = "smartreflex1",
634 .class = &am33xx_smartreflex_hwmod_class, 506 .class = &am33xx_smartreflex_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm", 507 .clkdm_name = "l4_wkup_clkdm",
636 .mpu_irqs = am33xx_smartreflex1_irqs,
637 .main_clk = "smartreflex1_fck", 508 .main_clk = "smartreflex1_fck",
638 .prcm = { 509 .prcm = {
639 .omap4 = { 510 .omap4 = {
@@ -650,17 +521,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
650 .name = "control", 521 .name = "control",
651}; 522};
652 523
653static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
654 { .irq = 8 + OMAP_INTC_START, },
655 { .irq = -1 },
656};
657
658static struct omap_hwmod am33xx_control_hwmod = { 524static struct omap_hwmod am33xx_control_hwmod = {
659 .name = "control", 525 .name = "control",
660 .class = &am33xx_control_hwmod_class, 526 .class = &am33xx_control_hwmod_class,
661 .clkdm_name = "l4_wkup_clkdm", 527 .clkdm_name = "l4_wkup_clkdm",
662 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 528 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
663 .mpu_irqs = am33xx_control_irqs,
664 .main_clk = "dpll_core_m4_div2_ck", 529 .main_clk = "dpll_core_m4_div2_ck",
665 .prcm = { 530 .prcm = {
666 .omap4 = { 531 .omap4 = {
@@ -690,20 +555,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
690 .sysc = &am33xx_cpgmac_sysc, 555 .sysc = &am33xx_cpgmac_sysc,
691}; 556};
692 557
693static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
694 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
695 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
696 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
697 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
698 { .irq = -1 },
699};
700
701static struct omap_hwmod am33xx_cpgmac0_hwmod = { 558static struct omap_hwmod am33xx_cpgmac0_hwmod = {
702 .name = "cpgmac0", 559 .name = "cpgmac0",
703 .class = &am33xx_cpgmac0_hwmod_class, 560 .class = &am33xx_cpgmac0_hwmod_class,
704 .clkdm_name = "cpsw_125mhz_clkdm", 561 .clkdm_name = "cpsw_125mhz_clkdm",
705 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 562 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
706 .mpu_irqs = am33xx_cpgmac0_irqs,
707 .main_clk = "cpsw_125mhz_gclk", 563 .main_clk = "cpsw_125mhz_gclk",
708 .prcm = { 564 .prcm = {
709 .omap4 = { 565 .omap4 = {
@@ -735,17 +591,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
735}; 591};
736 592
737/* dcan0 */ 593/* dcan0 */
738static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
739 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
740 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
741 { .irq = -1 },
742};
743
744static struct omap_hwmod am33xx_dcan0_hwmod = { 594static struct omap_hwmod am33xx_dcan0_hwmod = {
745 .name = "d_can0", 595 .name = "d_can0",
746 .class = &am33xx_dcan_hwmod_class, 596 .class = &am33xx_dcan_hwmod_class,
747 .clkdm_name = "l4ls_clkdm", 597 .clkdm_name = "l4ls_clkdm",
748 .mpu_irqs = am33xx_dcan0_irqs,
749 .main_clk = "dcan0_fck", 598 .main_clk = "dcan0_fck",
750 .prcm = { 599 .prcm = {
751 .omap4 = { 600 .omap4 = {
@@ -756,16 +605,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
756}; 605};
757 606
758/* dcan1 */ 607/* dcan1 */
759static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
760 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
761 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
762 { .irq = -1 },
763};
764static struct omap_hwmod am33xx_dcan1_hwmod = { 608static struct omap_hwmod am33xx_dcan1_hwmod = {
765 .name = "d_can1", 609 .name = "d_can1",
766 .class = &am33xx_dcan_hwmod_class, 610 .class = &am33xx_dcan_hwmod_class,
767 .clkdm_name = "l4ls_clkdm", 611 .clkdm_name = "l4ls_clkdm",
768 .mpu_irqs = am33xx_dcan1_irqs,
769 .main_clk = "dcan1_fck", 612 .main_clk = "dcan1_fck",
770 .prcm = { 613 .prcm = {
771 .omap4 = { 614 .omap4 = {
@@ -792,16 +635,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
792 .sysc = &am33xx_elm_sysc, 635 .sysc = &am33xx_elm_sysc,
793}; 636};
794 637
795static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
796 { .irq = 4 + OMAP_INTC_START, },
797 { .irq = -1 },
798};
799
800static struct omap_hwmod am33xx_elm_hwmod = { 638static struct omap_hwmod am33xx_elm_hwmod = {
801 .name = "elm", 639 .name = "elm",
802 .class = &am33xx_elm_hwmod_class, 640 .class = &am33xx_elm_hwmod_class,
803 .clkdm_name = "l4ls_clkdm", 641 .clkdm_name = "l4ls_clkdm",
804 .mpu_irqs = am33xx_elm_irqs,
805 .main_clk = "l4ls_gclk", 642 .main_clk = "l4ls_gclk",
806 .prcm = { 643 .prcm = {
807 .omap4 = { 644 .omap4 = {
@@ -854,45 +691,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
854}; 691};
855 692
856/* ecap0 */ 693/* ecap0 */
857static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
858 { .irq = 31 + OMAP_INTC_START, },
859 { .irq = -1 },
860};
861
862static struct omap_hwmod am33xx_ecap0_hwmod = { 694static struct omap_hwmod am33xx_ecap0_hwmod = {
863 .name = "ecap0", 695 .name = "ecap0",
864 .class = &am33xx_ecap_hwmod_class, 696 .class = &am33xx_ecap_hwmod_class,
865 .clkdm_name = "l4ls_clkdm", 697 .clkdm_name = "l4ls_clkdm",
866 .mpu_irqs = am33xx_ecap0_irqs,
867 .main_clk = "l4ls_gclk", 698 .main_clk = "l4ls_gclk",
868}; 699};
869 700
870/* eqep0 */ 701/* eqep0 */
871static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
872 { .irq = 79 + OMAP_INTC_START, },
873 { .irq = -1 },
874};
875
876static struct omap_hwmod am33xx_eqep0_hwmod = { 702static struct omap_hwmod am33xx_eqep0_hwmod = {
877 .name = "eqep0", 703 .name = "eqep0",
878 .class = &am33xx_eqep_hwmod_class, 704 .class = &am33xx_eqep_hwmod_class,
879 .clkdm_name = "l4ls_clkdm", 705 .clkdm_name = "l4ls_clkdm",
880 .mpu_irqs = am33xx_eqep0_irqs,
881 .main_clk = "l4ls_gclk", 706 .main_clk = "l4ls_gclk",
882}; 707};
883 708
884/* ehrpwm0 */ 709/* ehrpwm0 */
885static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
886 { .name = "int", .irq = 86 + OMAP_INTC_START, },
887 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
888 { .irq = -1 },
889};
890
891static struct omap_hwmod am33xx_ehrpwm0_hwmod = { 710static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
892 .name = "ehrpwm0", 711 .name = "ehrpwm0",
893 .class = &am33xx_ehrpwm_hwmod_class, 712 .class = &am33xx_ehrpwm_hwmod_class,
894 .clkdm_name = "l4ls_clkdm", 713 .clkdm_name = "l4ls_clkdm",
895 .mpu_irqs = am33xx_ehrpwm0_irqs,
896 .main_clk = "l4ls_gclk", 714 .main_clk = "l4ls_gclk",
897}; 715};
898 716
@@ -911,45 +729,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
911}; 729};
912 730
913/* ecap1 */ 731/* ecap1 */
914static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
915 { .irq = 47 + OMAP_INTC_START, },
916 { .irq = -1 },
917};
918
919static struct omap_hwmod am33xx_ecap1_hwmod = { 732static struct omap_hwmod am33xx_ecap1_hwmod = {
920 .name = "ecap1", 733 .name = "ecap1",
921 .class = &am33xx_ecap_hwmod_class, 734 .class = &am33xx_ecap_hwmod_class,
922 .clkdm_name = "l4ls_clkdm", 735 .clkdm_name = "l4ls_clkdm",
923 .mpu_irqs = am33xx_ecap1_irqs,
924 .main_clk = "l4ls_gclk", 736 .main_clk = "l4ls_gclk",
925}; 737};
926 738
927/* eqep1 */ 739/* eqep1 */
928static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
929 { .irq = 88 + OMAP_INTC_START, },
930 { .irq = -1 },
931};
932
933static struct omap_hwmod am33xx_eqep1_hwmod = { 740static struct omap_hwmod am33xx_eqep1_hwmod = {
934 .name = "eqep1", 741 .name = "eqep1",
935 .class = &am33xx_eqep_hwmod_class, 742 .class = &am33xx_eqep_hwmod_class,
936 .clkdm_name = "l4ls_clkdm", 743 .clkdm_name = "l4ls_clkdm",
937 .mpu_irqs = am33xx_eqep1_irqs,
938 .main_clk = "l4ls_gclk", 744 .main_clk = "l4ls_gclk",
939}; 745};
940 746
941/* ehrpwm1 */ 747/* ehrpwm1 */
942static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
943 { .name = "int", .irq = 87 + OMAP_INTC_START, },
944 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
945 { .irq = -1 },
946};
947
948static struct omap_hwmod am33xx_ehrpwm1_hwmod = { 748static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
949 .name = "ehrpwm1", 749 .name = "ehrpwm1",
950 .class = &am33xx_ehrpwm_hwmod_class, 750 .class = &am33xx_ehrpwm_hwmod_class,
951 .clkdm_name = "l4ls_clkdm", 751 .clkdm_name = "l4ls_clkdm",
952 .mpu_irqs = am33xx_ehrpwm1_irqs,
953 .main_clk = "l4ls_gclk", 752 .main_clk = "l4ls_gclk",
954}; 753};
955 754
@@ -968,45 +767,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
968}; 767};
969 768
970/* ecap2 */ 769/* ecap2 */
971static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
972 { .irq = 61 + OMAP_INTC_START, },
973 { .irq = -1 },
974};
975
976static struct omap_hwmod am33xx_ecap2_hwmod = { 770static struct omap_hwmod am33xx_ecap2_hwmod = {
977 .name = "ecap2", 771 .name = "ecap2",
978 .class = &am33xx_ecap_hwmod_class, 772 .class = &am33xx_ecap_hwmod_class,
979 .clkdm_name = "l4ls_clkdm", 773 .clkdm_name = "l4ls_clkdm",
980 .mpu_irqs = am33xx_ecap2_irqs,
981 .main_clk = "l4ls_gclk", 774 .main_clk = "l4ls_gclk",
982}; 775};
983 776
984/* eqep2 */ 777/* eqep2 */
985static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
986 { .irq = 89 + OMAP_INTC_START, },
987 { .irq = -1 },
988};
989
990static struct omap_hwmod am33xx_eqep2_hwmod = { 778static struct omap_hwmod am33xx_eqep2_hwmod = {
991 .name = "eqep2", 779 .name = "eqep2",
992 .class = &am33xx_eqep_hwmod_class, 780 .class = &am33xx_eqep_hwmod_class,
993 .clkdm_name = "l4ls_clkdm", 781 .clkdm_name = "l4ls_clkdm",
994 .mpu_irqs = am33xx_eqep2_irqs,
995 .main_clk = "l4ls_gclk", 782 .main_clk = "l4ls_gclk",
996}; 783};
997 784
998/* ehrpwm2 */ 785/* ehrpwm2 */
999static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
1000 { .name = "int", .irq = 39 + OMAP_INTC_START, },
1001 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
1002 { .irq = -1 },
1003};
1004
1005static struct omap_hwmod am33xx_ehrpwm2_hwmod = { 786static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
1006 .name = "ehrpwm2", 787 .name = "ehrpwm2",
1007 .class = &am33xx_ehrpwm_hwmod_class, 788 .class = &am33xx_ehrpwm_hwmod_class,
1008 .clkdm_name = "l4ls_clkdm", 789 .clkdm_name = "l4ls_clkdm",
1009 .mpu_irqs = am33xx_ehrpwm2_irqs,
1010 .main_clk = "l4ls_gclk", 790 .main_clk = "l4ls_gclk",
1011}; 791};
1012 792
@@ -1041,17 +821,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio0_dbclk" }, 821 { .role = "dbclk", .clk = "gpio0_dbclk" },
1042}; 822};
1043 823
1044static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1045 { .irq = 96 + OMAP_INTC_START, },
1046 { .irq = -1 },
1047};
1048
1049static struct omap_hwmod am33xx_gpio0_hwmod = { 824static struct omap_hwmod am33xx_gpio0_hwmod = {
1050 .name = "gpio1", 825 .name = "gpio1",
1051 .class = &am33xx_gpio_hwmod_class, 826 .class = &am33xx_gpio_hwmod_class,
1052 .clkdm_name = "l4_wkup_clkdm", 827 .clkdm_name = "l4_wkup_clkdm",
1053 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 828 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054 .mpu_irqs = am33xx_gpio0_irqs,
1055 .main_clk = "dpll_core_m4_div2_ck", 829 .main_clk = "dpll_core_m4_div2_ck",
1056 .prcm = { 830 .prcm = {
1057 .omap4 = { 831 .omap4 = {
@@ -1065,11 +839,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
1065}; 839};
1066 840
1067/* gpio1 */ 841/* gpio1 */
1068static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1069 { .irq = 98 + OMAP_INTC_START, },
1070 { .irq = -1 },
1071};
1072
1073static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 842static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1074 { .role = "dbclk", .clk = "gpio1_dbclk" }, 843 { .role = "dbclk", .clk = "gpio1_dbclk" },
1075}; 844};
@@ -1079,7 +848,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
1079 .class = &am33xx_gpio_hwmod_class, 848 .class = &am33xx_gpio_hwmod_class,
1080 .clkdm_name = "l4ls_clkdm", 849 .clkdm_name = "l4ls_clkdm",
1081 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 850 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1082 .mpu_irqs = am33xx_gpio1_irqs,
1083 .main_clk = "l4ls_gclk", 851 .main_clk = "l4ls_gclk",
1084 .prcm = { 852 .prcm = {
1085 .omap4 = { 853 .omap4 = {
@@ -1093,11 +861,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
1093}; 861};
1094 862
1095/* gpio2 */ 863/* gpio2 */
1096static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1097 { .irq = 32 + OMAP_INTC_START, },
1098 { .irq = -1 },
1099};
1100
1101static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 864static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1102 { .role = "dbclk", .clk = "gpio2_dbclk" }, 865 { .role = "dbclk", .clk = "gpio2_dbclk" },
1103}; 866};
@@ -1107,7 +870,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
1107 .class = &am33xx_gpio_hwmod_class, 870 .class = &am33xx_gpio_hwmod_class,
1108 .clkdm_name = "l4ls_clkdm", 871 .clkdm_name = "l4ls_clkdm",
1109 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 872 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1110 .mpu_irqs = am33xx_gpio2_irqs,
1111 .main_clk = "l4ls_gclk", 873 .main_clk = "l4ls_gclk",
1112 .prcm = { 874 .prcm = {
1113 .omap4 = { 875 .omap4 = {
@@ -1121,11 +883,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
1121}; 883};
1122 884
1123/* gpio3 */ 885/* gpio3 */
1124static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1125 { .irq = 62 + OMAP_INTC_START, },
1126 { .irq = -1 },
1127};
1128
1129static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 886static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1130 { .role = "dbclk", .clk = "gpio3_dbclk" }, 887 { .role = "dbclk", .clk = "gpio3_dbclk" },
1131}; 888};
@@ -1135,7 +892,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
1135 .class = &am33xx_gpio_hwmod_class, 892 .class = &am33xx_gpio_hwmod_class,
1136 .clkdm_name = "l4ls_clkdm", 893 .clkdm_name = "l4ls_clkdm",
1137 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 894 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1138 .mpu_irqs = am33xx_gpio3_irqs,
1139 .main_clk = "l4ls_gclk", 895 .main_clk = "l4ls_gclk",
1140 .prcm = { 896 .prcm = {
1141 .omap4 = { 897 .omap4 = {
@@ -1164,17 +920,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1164 .sysc = &gpmc_sysc, 920 .sysc = &gpmc_sysc,
1165}; 921};
1166 922
1167static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1168 { .irq = 100 + OMAP_INTC_START, },
1169 { .irq = -1 },
1170};
1171
1172static struct omap_hwmod am33xx_gpmc_hwmod = { 923static struct omap_hwmod am33xx_gpmc_hwmod = {
1173 .name = "gpmc", 924 .name = "gpmc",
1174 .class = &am33xx_gpmc_hwmod_class, 925 .class = &am33xx_gpmc_hwmod_class,
1175 .clkdm_name = "l3s_clkdm", 926 .clkdm_name = "l3s_clkdm",
1176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 927 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1177 .mpu_irqs = am33xx_gpmc_irqs,
1178 .main_clk = "l3s_gclk", 928 .main_clk = "l3s_gclk",
1179 .prcm = { 929 .prcm = {
1180 .omap4 = { 930 .omap4 = {
@@ -1208,23 +958,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
1208}; 958};
1209 959
1210/* i2c1 */ 960/* i2c1 */
1211static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1212 { .irq = 70 + OMAP_INTC_START, },
1213 { .irq = -1 },
1214};
1215
1216static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1217 { .name = "tx", .dma_req = 0, },
1218 { .name = "rx", .dma_req = 0, },
1219 { .dma_req = -1 }
1220};
1221
1222static struct omap_hwmod am33xx_i2c1_hwmod = { 961static struct omap_hwmod am33xx_i2c1_hwmod = {
1223 .name = "i2c1", 962 .name = "i2c1",
1224 .class = &i2c_class, 963 .class = &i2c_class,
1225 .clkdm_name = "l4_wkup_clkdm", 964 .clkdm_name = "l4_wkup_clkdm",
1226 .mpu_irqs = i2c1_mpu_irqs,
1227 .sdma_reqs = i2c1_edma_reqs,
1228 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 965 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1229 .main_clk = "dpll_per_m2_div4_wkupdm_ck", 966 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1230 .prcm = { 967 .prcm = {
@@ -1237,23 +974,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
1237}; 974};
1238 975
1239/* i2c1 */ 976/* i2c1 */
1240static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1241 { .irq = 71 + OMAP_INTC_START, },
1242 { .irq = -1 },
1243};
1244
1245static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1246 { .name = "tx", .dma_req = 0, },
1247 { .name = "rx", .dma_req = 0, },
1248 { .dma_req = -1 }
1249};
1250
1251static struct omap_hwmod am33xx_i2c2_hwmod = { 977static struct omap_hwmod am33xx_i2c2_hwmod = {
1252 .name = "i2c2", 978 .name = "i2c2",
1253 .class = &i2c_class, 979 .class = &i2c_class,
1254 .clkdm_name = "l4ls_clkdm", 980 .clkdm_name = "l4ls_clkdm",
1255 .mpu_irqs = i2c2_mpu_irqs,
1256 .sdma_reqs = i2c2_edma_reqs,
1257 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 981 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1258 .main_clk = "dpll_per_m2_div4_ck", 982 .main_clk = "dpll_per_m2_div4_ck",
1259 .prcm = { 983 .prcm = {
@@ -1266,23 +990,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
1266}; 990};
1267 991
1268/* i2c3 */ 992/* i2c3 */
1269static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1270 { .name = "tx", .dma_req = 0, },
1271 { .name = "rx", .dma_req = 0, },
1272 { .dma_req = -1 }
1273};
1274
1275static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1276 { .irq = 30 + OMAP_INTC_START, },
1277 { .irq = -1 },
1278};
1279
1280static struct omap_hwmod am33xx_i2c3_hwmod = { 993static struct omap_hwmod am33xx_i2c3_hwmod = {
1281 .name = "i2c3", 994 .name = "i2c3",
1282 .class = &i2c_class, 995 .class = &i2c_class,
1283 .clkdm_name = "l4ls_clkdm", 996 .clkdm_name = "l4ls_clkdm",
1284 .mpu_irqs = i2c3_mpu_irqs,
1285 .sdma_reqs = i2c3_edma_reqs,
1286 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 997 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1287 .main_clk = "dpll_per_m2_div4_ck", 998 .main_clk = "dpll_per_m2_div4_ck",
1288 .prcm = { 999 .prcm = {
@@ -1309,16 +1020,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1309 .sysc = &lcdc_sysc, 1020 .sysc = &lcdc_sysc,
1310}; 1021};
1311 1022
1312static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1313 { .irq = 36 + OMAP_INTC_START, },
1314 { .irq = -1 },
1315};
1316
1317static struct omap_hwmod am33xx_lcdc_hwmod = { 1023static struct omap_hwmod am33xx_lcdc_hwmod = {
1318 .name = "lcdc", 1024 .name = "lcdc",
1319 .class = &am33xx_lcdc_hwmod_class, 1025 .class = &am33xx_lcdc_hwmod_class,
1320 .clkdm_name = "lcdc_clkdm", 1026 .clkdm_name = "lcdc_clkdm",
1321 .mpu_irqs = am33xx_lcdc_irqs,
1322 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1027 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1323 .main_clk = "lcd_gclk", 1028 .main_clk = "lcd_gclk",
1324 .prcm = { 1029 .prcm = {
@@ -1348,16 +1053,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1348 .sysc = &am33xx_mailbox_sysc, 1053 .sysc = &am33xx_mailbox_sysc,
1349}; 1054};
1350 1055
1351static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1352 { .irq = 77 + OMAP_INTC_START, },
1353 { .irq = -1 },
1354};
1355
1356static struct omap_hwmod am33xx_mailbox_hwmod = { 1056static struct omap_hwmod am33xx_mailbox_hwmod = {
1357 .name = "mailbox", 1057 .name = "mailbox",
1358 .class = &am33xx_mailbox_hwmod_class, 1058 .class = &am33xx_mailbox_hwmod_class,
1359 .clkdm_name = "l4ls_clkdm", 1059 .clkdm_name = "l4ls_clkdm",
1360 .mpu_irqs = am33xx_mailbox_irqs,
1361 .main_clk = "l4ls_gclk", 1060 .main_clk = "l4ls_gclk",
1362 .prcm = { 1061 .prcm = {
1363 .omap4 = { 1062 .omap4 = {
@@ -1384,24 +1083,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1384}; 1083};
1385 1084
1386/* mcasp0 */ 1085/* mcasp0 */
1387static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1388 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1389 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1390 { .irq = -1 },
1391};
1392
1393static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1394 { .name = "tx", .dma_req = 8, },
1395 { .name = "rx", .dma_req = 9, },
1396 { .dma_req = -1 }
1397};
1398
1399static struct omap_hwmod am33xx_mcasp0_hwmod = { 1086static struct omap_hwmod am33xx_mcasp0_hwmod = {
1400 .name = "mcasp0", 1087 .name = "mcasp0",
1401 .class = &am33xx_mcasp_hwmod_class, 1088 .class = &am33xx_mcasp_hwmod_class,
1402 .clkdm_name = "l3s_clkdm", 1089 .clkdm_name = "l3s_clkdm",
1403 .mpu_irqs = am33xx_mcasp0_irqs,
1404 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1405 .main_clk = "mcasp0_fck", 1090 .main_clk = "mcasp0_fck",
1406 .prcm = { 1091 .prcm = {
1407 .omap4 = { 1092 .omap4 = {
@@ -1412,24 +1097,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
1412}; 1097};
1413 1098
1414/* mcasp1 */ 1099/* mcasp1 */
1415static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1416 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1417 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1418 { .irq = -1 },
1419};
1420
1421static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1422 { .name = "tx", .dma_req = 10, },
1423 { .name = "rx", .dma_req = 11, },
1424 { .dma_req = -1 }
1425};
1426
1427static struct omap_hwmod am33xx_mcasp1_hwmod = { 1100static struct omap_hwmod am33xx_mcasp1_hwmod = {
1428 .name = "mcasp1", 1101 .name = "mcasp1",
1429 .class = &am33xx_mcasp_hwmod_class, 1102 .class = &am33xx_mcasp_hwmod_class,
1430 .clkdm_name = "l3s_clkdm", 1103 .clkdm_name = "l3s_clkdm",
1431 .mpu_irqs = am33xx_mcasp1_irqs,
1432 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1433 .main_clk = "mcasp1_fck", 1104 .main_clk = "mcasp1_fck",
1434 .prcm = { 1105 .prcm = {
1435 .omap4 = { 1106 .omap4 = {
@@ -1457,17 +1128,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1457}; 1128};
1458 1129
1459/* mmc0 */ 1130/* mmc0 */
1460static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1461 { .irq = 64 + OMAP_INTC_START, },
1462 { .irq = -1 },
1463};
1464
1465static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1466 { .name = "tx", .dma_req = 24, },
1467 { .name = "rx", .dma_req = 25, },
1468 { .dma_req = -1 }
1469};
1470
1471static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = { 1131static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1472 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1132 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1473}; 1133};
@@ -1476,8 +1136,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
1476 .name = "mmc1", 1136 .name = "mmc1",
1477 .class = &am33xx_mmc_hwmod_class, 1137 .class = &am33xx_mmc_hwmod_class,
1478 .clkdm_name = "l4ls_clkdm", 1138 .clkdm_name = "l4ls_clkdm",
1479 .mpu_irqs = am33xx_mmc0_irqs,
1480 .sdma_reqs = am33xx_mmc0_edma_reqs,
1481 .main_clk = "mmc_clk", 1139 .main_clk = "mmc_clk",
1482 .prcm = { 1140 .prcm = {
1483 .omap4 = { 1141 .omap4 = {
@@ -1489,17 +1147,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
1489}; 1147};
1490 1148
1491/* mmc1 */ 1149/* mmc1 */
1492static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1493 { .irq = 28 + OMAP_INTC_START, },
1494 { .irq = -1 },
1495};
1496
1497static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1498 { .name = "tx", .dma_req = 2, },
1499 { .name = "rx", .dma_req = 3, },
1500 { .dma_req = -1 }
1501};
1502
1503static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = { 1150static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1504 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1151 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1505}; 1152};
@@ -1508,8 +1155,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
1508 .name = "mmc2", 1155 .name = "mmc2",
1509 .class = &am33xx_mmc_hwmod_class, 1156 .class = &am33xx_mmc_hwmod_class,
1510 .clkdm_name = "l4ls_clkdm", 1157 .clkdm_name = "l4ls_clkdm",
1511 .mpu_irqs = am33xx_mmc1_irqs,
1512 .sdma_reqs = am33xx_mmc1_edma_reqs,
1513 .main_clk = "mmc_clk", 1158 .main_clk = "mmc_clk",
1514 .prcm = { 1159 .prcm = {
1515 .omap4 = { 1160 .omap4 = {
@@ -1521,17 +1166,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
1521}; 1166};
1522 1167
1523/* mmc2 */ 1168/* mmc2 */
1524static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1525 { .irq = 29 + OMAP_INTC_START, },
1526 { .irq = -1 },
1527};
1528
1529static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1530 { .name = "tx", .dma_req = 64, },
1531 { .name = "rx", .dma_req = 65, },
1532 { .dma_req = -1 }
1533};
1534
1535static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = { 1169static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1536 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, 1170 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1537}; 1171};
@@ -1539,8 +1173,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
1539 .name = "mmc3", 1173 .name = "mmc3",
1540 .class = &am33xx_mmc_hwmod_class, 1174 .class = &am33xx_mmc_hwmod_class,
1541 .clkdm_name = "l3s_clkdm", 1175 .clkdm_name = "l3s_clkdm",
1542 .mpu_irqs = am33xx_mmc2_irqs,
1543 .sdma_reqs = am33xx_mmc2_edma_reqs,
1544 .main_clk = "mmc_clk", 1176 .main_clk = "mmc_clk",
1545 .prcm = { 1177 .prcm = {
1546 .omap4 = { 1178 .omap4 = {
@@ -1569,17 +1201,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1569 .sysc = &am33xx_rtc_sysc, 1201 .sysc = &am33xx_rtc_sysc,
1570}; 1202};
1571 1203
1572static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1573 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1574 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1575 { .irq = -1 },
1576};
1577
1578static struct omap_hwmod am33xx_rtc_hwmod = { 1204static struct omap_hwmod am33xx_rtc_hwmod = {
1579 .name = "rtc", 1205 .name = "rtc",
1580 .class = &am33xx_rtc_hwmod_class, 1206 .class = &am33xx_rtc_hwmod_class,
1581 .clkdm_name = "l4_rtc_clkdm", 1207 .clkdm_name = "l4_rtc_clkdm",
1582 .mpu_irqs = am33xx_rtc_irqs,
1583 .main_clk = "clk_32768_ck", 1208 .main_clk = "clk_32768_ck",
1584 .prcm = { 1209 .prcm = {
1585 .omap4 = { 1210 .omap4 = {
@@ -1608,19 +1233,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1608}; 1233};
1609 1234
1610/* spi0 */ 1235/* spi0 */
1611static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1612 { .irq = 65 + OMAP_INTC_START, },
1613 { .irq = -1 },
1614};
1615
1616static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1617 { .name = "rx0", .dma_req = 17 },
1618 { .name = "tx0", .dma_req = 16 },
1619 { .name = "rx1", .dma_req = 19 },
1620 { .name = "tx1", .dma_req = 18 },
1621 { .dma_req = -1 }
1622};
1623
1624static struct omap2_mcspi_dev_attr mcspi_attrib = { 1236static struct omap2_mcspi_dev_attr mcspi_attrib = {
1625 .num_chipselect = 2, 1237 .num_chipselect = 2,
1626}; 1238};
@@ -1628,8 +1240,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
1628 .name = "spi0", 1240 .name = "spi0",
1629 .class = &am33xx_spi_hwmod_class, 1241 .class = &am33xx_spi_hwmod_class,
1630 .clkdm_name = "l4ls_clkdm", 1242 .clkdm_name = "l4ls_clkdm",
1631 .mpu_irqs = am33xx_spi0_irqs,
1632 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1633 .main_clk = "dpll_per_m2_div4_ck", 1243 .main_clk = "dpll_per_m2_div4_ck",
1634 .prcm = { 1244 .prcm = {
1635 .omap4 = { 1245 .omap4 = {
@@ -1641,25 +1251,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
1641}; 1251};
1642 1252
1643/* spi1 */ 1253/* spi1 */
1644static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1645 { .irq = 125 + OMAP_INTC_START, },
1646 { .irq = -1 },
1647};
1648
1649static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1650 { .name = "rx0", .dma_req = 43 },
1651 { .name = "tx0", .dma_req = 42 },
1652 { .name = "rx1", .dma_req = 45 },
1653 { .name = "tx1", .dma_req = 44 },
1654 { .dma_req = -1 }
1655};
1656
1657static struct omap_hwmod am33xx_spi1_hwmod = { 1254static struct omap_hwmod am33xx_spi1_hwmod = {
1658 .name = "spi1", 1255 .name = "spi1",
1659 .class = &am33xx_spi_hwmod_class, 1256 .class = &am33xx_spi_hwmod_class,
1660 .clkdm_name = "l4ls_clkdm", 1257 .clkdm_name = "l4ls_clkdm",
1661 .mpu_irqs = am33xx_spi1_irqs,
1662 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1663 .main_clk = "dpll_per_m2_div4_ck", 1258 .main_clk = "dpll_per_m2_div4_ck",
1664 .prcm = { 1259 .prcm = {
1665 .omap4 = { 1260 .omap4 = {
@@ -1725,16 +1320,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1725 .sysc = &am33xx_timer1ms_sysc, 1320 .sysc = &am33xx_timer1ms_sysc,
1726}; 1321};
1727 1322
1728static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1729 { .irq = 67 + OMAP_INTC_START, },
1730 { .irq = -1 },
1731};
1732
1733static struct omap_hwmod am33xx_timer1_hwmod = { 1323static struct omap_hwmod am33xx_timer1_hwmod = {
1734 .name = "timer1", 1324 .name = "timer1",
1735 .class = &am33xx_timer1ms_hwmod_class, 1325 .class = &am33xx_timer1ms_hwmod_class,
1736 .clkdm_name = "l4_wkup_clkdm", 1326 .clkdm_name = "l4_wkup_clkdm",
1737 .mpu_irqs = am33xx_timer1_irqs,
1738 .main_clk = "timer1_fck", 1327 .main_clk = "timer1_fck",
1739 .prcm = { 1328 .prcm = {
1740 .omap4 = { 1329 .omap4 = {
@@ -1744,16 +1333,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
1744 }, 1333 },
1745}; 1334};
1746 1335
1747static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1748 { .irq = 68 + OMAP_INTC_START, },
1749 { .irq = -1 },
1750};
1751
1752static struct omap_hwmod am33xx_timer2_hwmod = { 1336static struct omap_hwmod am33xx_timer2_hwmod = {
1753 .name = "timer2", 1337 .name = "timer2",
1754 .class = &am33xx_timer_hwmod_class, 1338 .class = &am33xx_timer_hwmod_class,
1755 .clkdm_name = "l4ls_clkdm", 1339 .clkdm_name = "l4ls_clkdm",
1756 .mpu_irqs = am33xx_timer2_irqs,
1757 .main_clk = "timer2_fck", 1340 .main_clk = "timer2_fck",
1758 .prcm = { 1341 .prcm = {
1759 .omap4 = { 1342 .omap4 = {
@@ -1763,16 +1346,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
1763 }, 1346 },
1764}; 1347};
1765 1348
1766static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1767 { .irq = 69 + OMAP_INTC_START, },
1768 { .irq = -1 },
1769};
1770
1771static struct omap_hwmod am33xx_timer3_hwmod = { 1349static struct omap_hwmod am33xx_timer3_hwmod = {
1772 .name = "timer3", 1350 .name = "timer3",
1773 .class = &am33xx_timer_hwmod_class, 1351 .class = &am33xx_timer_hwmod_class,
1774 .clkdm_name = "l4ls_clkdm", 1352 .clkdm_name = "l4ls_clkdm",
1775 .mpu_irqs = am33xx_timer3_irqs,
1776 .main_clk = "timer3_fck", 1353 .main_clk = "timer3_fck",
1777 .prcm = { 1354 .prcm = {
1778 .omap4 = { 1355 .omap4 = {
@@ -1782,16 +1359,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
1782 }, 1359 },
1783}; 1360};
1784 1361
1785static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1786 { .irq = 92 + OMAP_INTC_START, },
1787 { .irq = -1 },
1788};
1789
1790static struct omap_hwmod am33xx_timer4_hwmod = { 1362static struct omap_hwmod am33xx_timer4_hwmod = {
1791 .name = "timer4", 1363 .name = "timer4",
1792 .class = &am33xx_timer_hwmod_class, 1364 .class = &am33xx_timer_hwmod_class,
1793 .clkdm_name = "l4ls_clkdm", 1365 .clkdm_name = "l4ls_clkdm",
1794 .mpu_irqs = am33xx_timer4_irqs,
1795 .main_clk = "timer4_fck", 1366 .main_clk = "timer4_fck",
1796 .prcm = { 1367 .prcm = {
1797 .omap4 = { 1368 .omap4 = {
@@ -1801,16 +1372,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
1801 }, 1372 },
1802}; 1373};
1803 1374
1804static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1805 { .irq = 93 + OMAP_INTC_START, },
1806 { .irq = -1 },
1807};
1808
1809static struct omap_hwmod am33xx_timer5_hwmod = { 1375static struct omap_hwmod am33xx_timer5_hwmod = {
1810 .name = "timer5", 1376 .name = "timer5",
1811 .class = &am33xx_timer_hwmod_class, 1377 .class = &am33xx_timer_hwmod_class,
1812 .clkdm_name = "l4ls_clkdm", 1378 .clkdm_name = "l4ls_clkdm",
1813 .mpu_irqs = am33xx_timer5_irqs,
1814 .main_clk = "timer5_fck", 1379 .main_clk = "timer5_fck",
1815 .prcm = { 1380 .prcm = {
1816 .omap4 = { 1381 .omap4 = {
@@ -1820,16 +1385,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
1820 }, 1385 },
1821}; 1386};
1822 1387
1823static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1824 { .irq = 94 + OMAP_INTC_START, },
1825 { .irq = -1 },
1826};
1827
1828static struct omap_hwmod am33xx_timer6_hwmod = { 1388static struct omap_hwmod am33xx_timer6_hwmod = {
1829 .name = "timer6", 1389 .name = "timer6",
1830 .class = &am33xx_timer_hwmod_class, 1390 .class = &am33xx_timer_hwmod_class,
1831 .clkdm_name = "l4ls_clkdm", 1391 .clkdm_name = "l4ls_clkdm",
1832 .mpu_irqs = am33xx_timer6_irqs,
1833 .main_clk = "timer6_fck", 1392 .main_clk = "timer6_fck",
1834 .prcm = { 1393 .prcm = {
1835 .omap4 = { 1394 .omap4 = {
@@ -1839,16 +1398,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
1839 }, 1398 },
1840}; 1399};
1841 1400
1842static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1843 { .irq = 95 + OMAP_INTC_START, },
1844 { .irq = -1 },
1845};
1846
1847static struct omap_hwmod am33xx_timer7_hwmod = { 1401static struct omap_hwmod am33xx_timer7_hwmod = {
1848 .name = "timer7", 1402 .name = "timer7",
1849 .class = &am33xx_timer_hwmod_class, 1403 .class = &am33xx_timer_hwmod_class,
1850 .clkdm_name = "l4ls_clkdm", 1404 .clkdm_name = "l4ls_clkdm",
1851 .mpu_irqs = am33xx_timer7_irqs,
1852 .main_clk = "timer7_fck", 1405 .main_clk = "timer7_fck",
1853 .prcm = { 1406 .prcm = {
1854 .omap4 = { 1407 .omap4 = {
@@ -1863,18 +1416,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1863 .name = "tpcc", 1416 .name = "tpcc",
1864}; 1417};
1865 1418
1866static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1867 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1868 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1869 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1870 { .irq = -1 },
1871};
1872
1873static struct omap_hwmod am33xx_tpcc_hwmod = { 1419static struct omap_hwmod am33xx_tpcc_hwmod = {
1874 .name = "tpcc", 1420 .name = "tpcc",
1875 .class = &am33xx_tpcc_hwmod_class, 1421 .class = &am33xx_tpcc_hwmod_class,
1876 .clkdm_name = "l3_clkdm", 1422 .clkdm_name = "l3_clkdm",
1877 .mpu_irqs = am33xx_tpcc_irqs,
1878 .main_clk = "l3_gclk", 1423 .main_clk = "l3_gclk",
1879 .prcm = { 1424 .prcm = {
1880 .omap4 = { 1425 .omap4 = {
@@ -1900,16 +1445,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1900}; 1445};
1901 1446
1902/* tptc0 */ 1447/* tptc0 */
1903static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1904 { .irq = 112 + OMAP_INTC_START, },
1905 { .irq = -1 },
1906};
1907
1908static struct omap_hwmod am33xx_tptc0_hwmod = { 1448static struct omap_hwmod am33xx_tptc0_hwmod = {
1909 .name = "tptc0", 1449 .name = "tptc0",
1910 .class = &am33xx_tptc_hwmod_class, 1450 .class = &am33xx_tptc_hwmod_class,
1911 .clkdm_name = "l3_clkdm", 1451 .clkdm_name = "l3_clkdm",
1912 .mpu_irqs = am33xx_tptc0_irqs,
1913 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1452 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1914 .main_clk = "l3_gclk", 1453 .main_clk = "l3_gclk",
1915 .prcm = { 1454 .prcm = {
@@ -1921,16 +1460,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
1921}; 1460};
1922 1461
1923/* tptc1 */ 1462/* tptc1 */
1924static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1925 { .irq = 113 + OMAP_INTC_START, },
1926 { .irq = -1 },
1927};
1928
1929static struct omap_hwmod am33xx_tptc1_hwmod = { 1463static struct omap_hwmod am33xx_tptc1_hwmod = {
1930 .name = "tptc1", 1464 .name = "tptc1",
1931 .class = &am33xx_tptc_hwmod_class, 1465 .class = &am33xx_tptc_hwmod_class,
1932 .clkdm_name = "l3_clkdm", 1466 .clkdm_name = "l3_clkdm",
1933 .mpu_irqs = am33xx_tptc1_irqs,
1934 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 1467 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1935 .main_clk = "l3_gclk", 1468 .main_clk = "l3_gclk",
1936 .prcm = { 1469 .prcm = {
@@ -1942,16 +1475,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
1942}; 1475};
1943 1476
1944/* tptc2 */ 1477/* tptc2 */
1945static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1946 { .irq = 114 + OMAP_INTC_START, },
1947 { .irq = -1 },
1948};
1949
1950static struct omap_hwmod am33xx_tptc2_hwmod = { 1478static struct omap_hwmod am33xx_tptc2_hwmod = {
1951 .name = "tptc2", 1479 .name = "tptc2",
1952 .class = &am33xx_tptc_hwmod_class, 1480 .class = &am33xx_tptc_hwmod_class,
1953 .clkdm_name = "l3_clkdm", 1481 .clkdm_name = "l3_clkdm",
1954 .mpu_irqs = am33xx_tptc2_irqs,
1955 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY), 1482 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1956 .main_clk = "l3_gclk", 1483 .main_clk = "l3_gclk",
1957 .prcm = { 1484 .prcm = {
@@ -1980,24 +1507,11 @@ static struct omap_hwmod_class uart_class = {
1980}; 1507};
1981 1508
1982/* uart1 */ 1509/* uart1 */
1983static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1984 { .name = "tx", .dma_req = 26, },
1985 { .name = "rx", .dma_req = 27, },
1986 { .dma_req = -1 }
1987};
1988
1989static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1990 { .irq = 72 + OMAP_INTC_START, },
1991 { .irq = -1 },
1992};
1993
1994static struct omap_hwmod am33xx_uart1_hwmod = { 1510static struct omap_hwmod am33xx_uart1_hwmod = {
1995 .name = "uart1", 1511 .name = "uart1",
1996 .class = &uart_class, 1512 .class = &uart_class,
1997 .clkdm_name = "l4_wkup_clkdm", 1513 .clkdm_name = "l4_wkup_clkdm",
1998 .flags = HWMOD_SWSUP_SIDLE_ACT, 1514 .flags = HWMOD_SWSUP_SIDLE_ACT,
1999 .mpu_irqs = am33xx_uart1_irqs,
2000 .sdma_reqs = uart1_edma_reqs,
2001 .main_clk = "dpll_per_m2_div4_wkupdm_ck", 1515 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
2002 .prcm = { 1516 .prcm = {
2003 .omap4 = { 1517 .omap4 = {
@@ -2007,18 +1521,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
2007 }, 1521 },
2008}; 1522};
2009 1523
2010static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2011 { .irq = 73 + OMAP_INTC_START, },
2012 { .irq = -1 },
2013};
2014
2015static struct omap_hwmod am33xx_uart2_hwmod = { 1524static struct omap_hwmod am33xx_uart2_hwmod = {
2016 .name = "uart2", 1525 .name = "uart2",
2017 .class = &uart_class, 1526 .class = &uart_class,
2018 .clkdm_name = "l4ls_clkdm", 1527 .clkdm_name = "l4ls_clkdm",
2019 .flags = HWMOD_SWSUP_SIDLE_ACT, 1528 .flags = HWMOD_SWSUP_SIDLE_ACT,
2020 .mpu_irqs = am33xx_uart2_irqs,
2021 .sdma_reqs = uart1_edma_reqs,
2022 .main_clk = "dpll_per_m2_div4_ck", 1529 .main_clk = "dpll_per_m2_div4_ck",
2023 .prcm = { 1530 .prcm = {
2024 .omap4 = { 1531 .omap4 = {
@@ -2029,24 +1536,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
2029}; 1536};
2030 1537
2031/* uart3 */ 1538/* uart3 */
2032static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2033 { .name = "tx", .dma_req = 30, },
2034 { .name = "rx", .dma_req = 31, },
2035 { .dma_req = -1 }
2036};
2037
2038static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2039 { .irq = 74 + OMAP_INTC_START, },
2040 { .irq = -1 },
2041};
2042
2043static struct omap_hwmod am33xx_uart3_hwmod = { 1539static struct omap_hwmod am33xx_uart3_hwmod = {
2044 .name = "uart3", 1540 .name = "uart3",
2045 .class = &uart_class, 1541 .class = &uart_class,
2046 .clkdm_name = "l4ls_clkdm", 1542 .clkdm_name = "l4ls_clkdm",
2047 .flags = HWMOD_SWSUP_SIDLE_ACT, 1543 .flags = HWMOD_SWSUP_SIDLE_ACT,
2048 .mpu_irqs = am33xx_uart3_irqs,
2049 .sdma_reqs = uart3_edma_reqs,
2050 .main_clk = "dpll_per_m2_div4_ck", 1544 .main_clk = "dpll_per_m2_div4_ck",
2051 .prcm = { 1545 .prcm = {
2052 .omap4 = { 1546 .omap4 = {
@@ -2056,18 +1550,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
2056 }, 1550 },
2057}; 1551};
2058 1552
2059static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2060 { .irq = 44 + OMAP_INTC_START, },
2061 { .irq = -1 },
2062};
2063
2064static struct omap_hwmod am33xx_uart4_hwmod = { 1553static struct omap_hwmod am33xx_uart4_hwmod = {
2065 .name = "uart4", 1554 .name = "uart4",
2066 .class = &uart_class, 1555 .class = &uart_class,
2067 .clkdm_name = "l4ls_clkdm", 1556 .clkdm_name = "l4ls_clkdm",
2068 .flags = HWMOD_SWSUP_SIDLE_ACT, 1557 .flags = HWMOD_SWSUP_SIDLE_ACT,
2069 .mpu_irqs = am33xx_uart4_irqs,
2070 .sdma_reqs = uart1_edma_reqs,
2071 .main_clk = "dpll_per_m2_div4_ck", 1558 .main_clk = "dpll_per_m2_div4_ck",
2072 .prcm = { 1559 .prcm = {
2073 .omap4 = { 1560 .omap4 = {
@@ -2077,18 +1564,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
2077 }, 1564 },
2078}; 1565};
2079 1566
2080static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2081 { .irq = 45 + OMAP_INTC_START, },
2082 { .irq = -1 },
2083};
2084
2085static struct omap_hwmod am33xx_uart5_hwmod = { 1567static struct omap_hwmod am33xx_uart5_hwmod = {
2086 .name = "uart5", 1568 .name = "uart5",
2087 .class = &uart_class, 1569 .class = &uart_class,
2088 .clkdm_name = "l4ls_clkdm", 1570 .clkdm_name = "l4ls_clkdm",
2089 .flags = HWMOD_SWSUP_SIDLE_ACT, 1571 .flags = HWMOD_SWSUP_SIDLE_ACT,
2090 .mpu_irqs = am33xx_uart5_irqs,
2091 .sdma_reqs = uart1_edma_reqs,
2092 .main_clk = "dpll_per_m2_div4_ck", 1572 .main_clk = "dpll_per_m2_div4_ck",
2093 .prcm = { 1573 .prcm = {
2094 .omap4 = { 1574 .omap4 = {
@@ -2098,18 +1578,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
2098 }, 1578 },
2099}; 1579};
2100 1580
2101static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2102 { .irq = 46 + OMAP_INTC_START, },
2103 { .irq = -1 },
2104};
2105
2106static struct omap_hwmod am33xx_uart6_hwmod = { 1581static struct omap_hwmod am33xx_uart6_hwmod = {
2107 .name = "uart6", 1582 .name = "uart6",
2108 .class = &uart_class, 1583 .class = &uart_class,
2109 .clkdm_name = "l4ls_clkdm", 1584 .clkdm_name = "l4ls_clkdm",
2110 .flags = HWMOD_SWSUP_SIDLE_ACT, 1585 .flags = HWMOD_SWSUP_SIDLE_ACT,
2111 .mpu_irqs = am33xx_uart6_irqs,
2112 .sdma_reqs = uart1_edma_reqs,
2113 .main_clk = "dpll_per_m2_div4_ck", 1586 .main_clk = "dpll_per_m2_div4_ck",
2114 .prcm = { 1587 .prcm = {
2115 .omap4 = { 1588 .omap4 = {
@@ -2173,18 +1646,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
2173 .sysc = &am33xx_usbhsotg_sysc, 1646 .sysc = &am33xx_usbhsotg_sysc,
2174}; 1647};
2175 1648
2176static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2177 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2178 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2179 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2180 { .irq = -1, },
2181};
2182
2183static struct omap_hwmod am33xx_usbss_hwmod = { 1649static struct omap_hwmod am33xx_usbss_hwmod = {
2184 .name = "usb_otg_hs", 1650 .name = "usb_otg_hs",
2185 .class = &am33xx_usbotg_class, 1651 .class = &am33xx_usbotg_class,
2186 .clkdm_name = "l3s_clkdm", 1652 .clkdm_name = "l3s_clkdm",
2187 .mpu_irqs = am33xx_usbss_mpu_irqs,
2188 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 1653 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2189 .main_clk = "usbotg_fck", 1654 .main_clk = "usbotg_fck",
2190 .prcm = { 1655 .prcm = {
@@ -2200,14 +1665,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
2200 * Interfaces 1665 * Interfaces
2201 */ 1666 */
2202 1667
2203/* l4 fw -> emif fw */
2204static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2205 .master = &am33xx_l4_fw_hwmod,
2206 .slave = &am33xx_emif_fw_hwmod,
2207 .clk = "l4fw_gclk",
2208 .user = OCP_USER_MPU,
2209};
2210
2211static struct omap_hwmod_addr_space am33xx_emif_addrs[] = { 1668static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2212 { 1669 {
2213 .pa_start = 0x4c000000, 1670 .pa_start = 0x4c000000,
@@ -2265,14 +1722,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2265 .user = OCP_USER_MPU | OCP_USER_SDMA, 1722 .user = OCP_USER_MPU | OCP_USER_SDMA,
2266}; 1723};
2267 1724
2268/* l3 s -> l4 fw */
2269static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2270 .master = &am33xx_l3_s_hwmod,
2271 .slave = &am33xx_l4_fw_hwmod,
2272 .clk = "l3s_gclk",
2273 .user = OCP_USER_MPU | OCP_USER_SDMA,
2274};
2275
2276/* l3 main -> l3 instr */ 1725/* l3 main -> l3 instr */
2277static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = { 1726static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2278 .master = &am33xx_l3_main_hwmod, 1727 .master = &am33xx_l3_main_hwmod,
@@ -2322,261 +1771,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2322}; 1771};
2323 1772
2324/* l4 wkup -> wkup m3 */ 1773/* l4 wkup -> wkup m3 */
2325static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2326 {
2327 .name = "umem",
2328 .pa_start = 0x44d00000,
2329 .pa_end = 0x44d00000 + SZ_16K - 1,
2330 .flags = ADDR_TYPE_RT
2331 },
2332 {
2333 .name = "dmem",
2334 .pa_start = 0x44d80000,
2335 .pa_end = 0x44d80000 + SZ_8K - 1,
2336 .flags = ADDR_TYPE_RT
2337 },
2338 { }
2339};
2340
2341static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = { 1774static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2342 .master = &am33xx_l4_wkup_hwmod, 1775 .master = &am33xx_l4_wkup_hwmod,
2343 .slave = &am33xx_wkup_m3_hwmod, 1776 .slave = &am33xx_wkup_m3_hwmod,
2344 .clk = "dpll_core_m4_div2_ck", 1777 .clk = "dpll_core_m4_div2_ck",
2345 .addr = am33xx_wkup_m3_addrs,
2346 .user = OCP_USER_MPU | OCP_USER_SDMA, 1778 .user = OCP_USER_MPU | OCP_USER_SDMA,
2347}; 1779};
2348 1780
2349/* l4 hs -> pru-icss */ 1781/* l4 hs -> pru-icss */
2350static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2351 {
2352 .pa_start = 0x4a300000,
2353 .pa_end = 0x4a300000 + SZ_512K - 1,
2354 .flags = ADDR_TYPE_RT
2355 },
2356 { }
2357};
2358
2359static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = { 1782static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2360 .master = &am33xx_l4_hs_hwmod, 1783 .master = &am33xx_l4_hs_hwmod,
2361 .slave = &am33xx_pruss_hwmod, 1784 .slave = &am33xx_pruss_hwmod,
2362 .clk = "dpll_core_m4_ck", 1785 .clk = "dpll_core_m4_ck",
2363 .addr = am33xx_pruss_addrs,
2364 .user = OCP_USER_MPU | OCP_USER_SDMA, 1786 .user = OCP_USER_MPU | OCP_USER_SDMA,
2365}; 1787};
2366 1788
2367/* l3 main -> gfx */ 1789/* l3 main -> gfx */
2368static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2369 {
2370 .pa_start = 0x56000000,
2371 .pa_end = 0x56000000 + SZ_16M - 1,
2372 .flags = ADDR_TYPE_RT
2373 },
2374 { }
2375};
2376
2377static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { 1790static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2378 .master = &am33xx_l3_main_hwmod, 1791 .master = &am33xx_l3_main_hwmod,
2379 .slave = &am33xx_gfx_hwmod, 1792 .slave = &am33xx_gfx_hwmod,
2380 .clk = "dpll_core_m4_ck", 1793 .clk = "dpll_core_m4_ck",
2381 .addr = am33xx_gfx_addrs,
2382 .user = OCP_USER_MPU | OCP_USER_SDMA, 1794 .user = OCP_USER_MPU | OCP_USER_SDMA,
2383}; 1795};
2384 1796
2385/* l4 wkup -> smartreflex0 */ 1797/* l4 wkup -> smartreflex0 */
2386static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2387 {
2388 .pa_start = 0x44e37000,
2389 .pa_end = 0x44e37000 + SZ_4K - 1,
2390 .flags = ADDR_TYPE_RT
2391 },
2392 { }
2393};
2394
2395static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { 1798static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2396 .master = &am33xx_l4_wkup_hwmod, 1799 .master = &am33xx_l4_wkup_hwmod,
2397 .slave = &am33xx_smartreflex0_hwmod, 1800 .slave = &am33xx_smartreflex0_hwmod,
2398 .clk = "dpll_core_m4_div2_ck", 1801 .clk = "dpll_core_m4_div2_ck",
2399 .addr = am33xx_smartreflex0_addrs,
2400 .user = OCP_USER_MPU, 1802 .user = OCP_USER_MPU,
2401}; 1803};
2402 1804
2403/* l4 wkup -> smartreflex1 */ 1805/* l4 wkup -> smartreflex1 */
2404static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2405 {
2406 .pa_start = 0x44e39000,
2407 .pa_end = 0x44e39000 + SZ_4K - 1,
2408 .flags = ADDR_TYPE_RT
2409 },
2410 { }
2411};
2412
2413static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = { 1806static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2414 .master = &am33xx_l4_wkup_hwmod, 1807 .master = &am33xx_l4_wkup_hwmod,
2415 .slave = &am33xx_smartreflex1_hwmod, 1808 .slave = &am33xx_smartreflex1_hwmod,
2416 .clk = "dpll_core_m4_div2_ck", 1809 .clk = "dpll_core_m4_div2_ck",
2417 .addr = am33xx_smartreflex1_addrs,
2418 .user = OCP_USER_MPU, 1810 .user = OCP_USER_MPU,
2419}; 1811};
2420 1812
2421/* l4 wkup -> control */ 1813/* l4 wkup -> control */
2422static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2423 {
2424 .pa_start = 0x44e10000,
2425 .pa_end = 0x44e10000 + SZ_8K - 1,
2426 .flags = ADDR_TYPE_RT
2427 },
2428 { }
2429};
2430
2431static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = { 1814static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2432 .master = &am33xx_l4_wkup_hwmod, 1815 .master = &am33xx_l4_wkup_hwmod,
2433 .slave = &am33xx_control_hwmod, 1816 .slave = &am33xx_control_hwmod,
2434 .clk = "dpll_core_m4_div2_ck", 1817 .clk = "dpll_core_m4_div2_ck",
2435 .addr = am33xx_control_addrs,
2436 .user = OCP_USER_MPU, 1818 .user = OCP_USER_MPU,
2437}; 1819};
2438 1820
2439/* l4 wkup -> rtc */ 1821/* l4 wkup -> rtc */
2440static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2441 {
2442 .pa_start = 0x44e3e000,
2443 .pa_end = 0x44e3e000 + SZ_4K - 1,
2444 .flags = ADDR_TYPE_RT
2445 },
2446 { }
2447};
2448
2449static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { 1822static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2450 .master = &am33xx_l4_wkup_hwmod, 1823 .master = &am33xx_l4_wkup_hwmod,
2451 .slave = &am33xx_rtc_hwmod, 1824 .slave = &am33xx_rtc_hwmod,
2452 .clk = "clkdiv32k_ick", 1825 .clk = "clkdiv32k_ick",
2453 .addr = am33xx_rtc_addrs,
2454 .user = OCP_USER_MPU, 1826 .user = OCP_USER_MPU,
2455}; 1827};
2456 1828
2457/* l4 per/ls -> DCAN0 */ 1829/* l4 per/ls -> DCAN0 */
2458static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2459 {
2460 .pa_start = 0x481CC000,
2461 .pa_end = 0x481CC000 + SZ_4K - 1,
2462 .flags = ADDR_TYPE_RT
2463 },
2464 { }
2465};
2466
2467static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = { 1830static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2468 .master = &am33xx_l4_ls_hwmod, 1831 .master = &am33xx_l4_ls_hwmod,
2469 .slave = &am33xx_dcan0_hwmod, 1832 .slave = &am33xx_dcan0_hwmod,
2470 .clk = "l4ls_gclk", 1833 .clk = "l4ls_gclk",
2471 .addr = am33xx_dcan0_addrs,
2472 .user = OCP_USER_MPU | OCP_USER_SDMA, 1834 .user = OCP_USER_MPU | OCP_USER_SDMA,
2473}; 1835};
2474 1836
2475/* l4 per/ls -> DCAN1 */ 1837/* l4 per/ls -> DCAN1 */
2476static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2477 {
2478 .pa_start = 0x481D0000,
2479 .pa_end = 0x481D0000 + SZ_4K - 1,
2480 .flags = ADDR_TYPE_RT
2481 },
2482 { }
2483};
2484
2485static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = { 1838static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2486 .master = &am33xx_l4_ls_hwmod, 1839 .master = &am33xx_l4_ls_hwmod,
2487 .slave = &am33xx_dcan1_hwmod, 1840 .slave = &am33xx_dcan1_hwmod,
2488 .clk = "l4ls_gclk", 1841 .clk = "l4ls_gclk",
2489 .addr = am33xx_dcan1_addrs,
2490 .user = OCP_USER_MPU | OCP_USER_SDMA, 1842 .user = OCP_USER_MPU | OCP_USER_SDMA,
2491}; 1843};
2492 1844
2493/* l4 per/ls -> GPIO2 */ 1845/* l4 per/ls -> GPIO2 */
2494static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2495 {
2496 .pa_start = 0x4804C000,
2497 .pa_end = 0x4804C000 + SZ_4K - 1,
2498 .flags = ADDR_TYPE_RT,
2499 },
2500 { }
2501};
2502
2503static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = { 1846static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2504 .master = &am33xx_l4_ls_hwmod, 1847 .master = &am33xx_l4_ls_hwmod,
2505 .slave = &am33xx_gpio1_hwmod, 1848 .slave = &am33xx_gpio1_hwmod,
2506 .clk = "l4ls_gclk", 1849 .clk = "l4ls_gclk",
2507 .addr = am33xx_gpio1_addrs,
2508 .user = OCP_USER_MPU | OCP_USER_SDMA, 1850 .user = OCP_USER_MPU | OCP_USER_SDMA,
2509}; 1851};
2510 1852
2511/* l4 per/ls -> gpio3 */ 1853/* l4 per/ls -> gpio3 */
2512static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2513 {
2514 .pa_start = 0x481AC000,
2515 .pa_end = 0x481AC000 + SZ_4K - 1,
2516 .flags = ADDR_TYPE_RT,
2517 },
2518 { }
2519};
2520
2521static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = { 1854static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2522 .master = &am33xx_l4_ls_hwmod, 1855 .master = &am33xx_l4_ls_hwmod,
2523 .slave = &am33xx_gpio2_hwmod, 1856 .slave = &am33xx_gpio2_hwmod,
2524 .clk = "l4ls_gclk", 1857 .clk = "l4ls_gclk",
2525 .addr = am33xx_gpio2_addrs,
2526 .user = OCP_USER_MPU | OCP_USER_SDMA, 1858 .user = OCP_USER_MPU | OCP_USER_SDMA,
2527}; 1859};
2528 1860
2529/* l4 per/ls -> gpio4 */ 1861/* l4 per/ls -> gpio4 */
2530static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2531 {
2532 .pa_start = 0x481AE000,
2533 .pa_end = 0x481AE000 + SZ_4K - 1,
2534 .flags = ADDR_TYPE_RT,
2535 },
2536 { }
2537};
2538
2539static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = { 1862static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2540 .master = &am33xx_l4_ls_hwmod, 1863 .master = &am33xx_l4_ls_hwmod,
2541 .slave = &am33xx_gpio3_hwmod, 1864 .slave = &am33xx_gpio3_hwmod,
2542 .clk = "l4ls_gclk", 1865 .clk = "l4ls_gclk",
2543 .addr = am33xx_gpio3_addrs,
2544 .user = OCP_USER_MPU | OCP_USER_SDMA, 1866 .user = OCP_USER_MPU | OCP_USER_SDMA,
2545}; 1867};
2546 1868
2547/* L4 WKUP -> I2C1 */ 1869/* L4 WKUP -> I2C1 */
2548static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2549 {
2550 .pa_start = 0x44E0B000,
2551 .pa_end = 0x44E0B000 + SZ_4K - 1,
2552 .flags = ADDR_TYPE_RT,
2553 },
2554 { }
2555};
2556
2557static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = { 1870static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2558 .master = &am33xx_l4_wkup_hwmod, 1871 .master = &am33xx_l4_wkup_hwmod,
2559 .slave = &am33xx_i2c1_hwmod, 1872 .slave = &am33xx_i2c1_hwmod,
2560 .clk = "dpll_core_m4_div2_ck", 1873 .clk = "dpll_core_m4_div2_ck",
2561 .addr = am33xx_i2c1_addr_space,
2562 .user = OCP_USER_MPU, 1874 .user = OCP_USER_MPU,
2563}; 1875};
2564 1876
2565/* L4 WKUP -> GPIO1 */ 1877/* L4 WKUP -> GPIO1 */
2566static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2567 {
2568 .pa_start = 0x44E07000,
2569 .pa_end = 0x44E07000 + SZ_4K - 1,
2570 .flags = ADDR_TYPE_RT,
2571 },
2572 { }
2573};
2574
2575static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = { 1878static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2576 .master = &am33xx_l4_wkup_hwmod, 1879 .master = &am33xx_l4_wkup_hwmod,
2577 .slave = &am33xx_gpio0_hwmod, 1880 .slave = &am33xx_gpio0_hwmod,
2578 .clk = "dpll_core_m4_div2_ck", 1881 .clk = "dpll_core_m4_div2_ck",
2579 .addr = am33xx_gpio0_addrs,
2580 .user = OCP_USER_MPU | OCP_USER_SDMA, 1882 .user = OCP_USER_MPU | OCP_USER_SDMA,
2581}; 1883};
2582 1884
@@ -2598,41 +1900,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2598 .user = OCP_USER_MPU, 1900 .user = OCP_USER_MPU,
2599}; 1901};
2600 1902
2601static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2602 /* cpsw ss */
2603 {
2604 .pa_start = 0x4a100000,
2605 .pa_end = 0x4a100000 + SZ_2K - 1,
2606 },
2607 /* cpsw wr */
2608 {
2609 .pa_start = 0x4a101200,
2610 .pa_end = 0x4a101200 + SZ_256 - 1,
2611 .flags = ADDR_TYPE_RT,
2612 },
2613 { }
2614};
2615
2616static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = { 1903static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2617 .master = &am33xx_l4_hs_hwmod, 1904 .master = &am33xx_l4_hs_hwmod,
2618 .slave = &am33xx_cpgmac0_hwmod, 1905 .slave = &am33xx_cpgmac0_hwmod,
2619 .clk = "cpsw_125mhz_gclk", 1906 .clk = "cpsw_125mhz_gclk",
2620 .addr = am33xx_cpgmac0_addr_space,
2621 .user = OCP_USER_MPU, 1907 .user = OCP_USER_MPU,
2622}; 1908};
2623 1909
2624static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2625 {
2626 .pa_start = 0x4A101000,
2627 .pa_end = 0x4A101000 + SZ_256 - 1,
2628 },
2629 { }
2630};
2631
2632static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = { 1910static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2633 .master = &am33xx_cpgmac0_hwmod, 1911 .master = &am33xx_cpgmac0_hwmod,
2634 .slave = &am33xx_mdio_hwmod, 1912 .slave = &am33xx_mdio_hwmod,
2635 .addr = am33xx_mdio_addr_space,
2636 .user = OCP_USER_MPU, 1913 .user = OCP_USER_MPU,
2637}; 1914};
2638 1915
@@ -2670,51 +1947,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2670 .user = OCP_USER_MPU, 1947 .user = OCP_USER_MPU,
2671}; 1948};
2672 1949
2673static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2674 {
2675 .pa_start = 0x48300100,
2676 .pa_end = 0x48300100 + SZ_128 - 1,
2677 },
2678 { }
2679};
2680
2681static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = { 1950static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2682 .master = &am33xx_epwmss0_hwmod, 1951 .master = &am33xx_epwmss0_hwmod,
2683 .slave = &am33xx_ecap0_hwmod, 1952 .slave = &am33xx_ecap0_hwmod,
2684 .clk = "l4ls_gclk", 1953 .clk = "l4ls_gclk",
2685 .addr = am33xx_ecap0_addr_space,
2686 .user = OCP_USER_MPU, 1954 .user = OCP_USER_MPU,
2687}; 1955};
2688 1956
2689static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2690 {
2691 .pa_start = 0x48300180,
2692 .pa_end = 0x48300180 + SZ_128 - 1,
2693 },
2694 { }
2695};
2696
2697static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = { 1957static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2698 .master = &am33xx_epwmss0_hwmod, 1958 .master = &am33xx_epwmss0_hwmod,
2699 .slave = &am33xx_eqep0_hwmod, 1959 .slave = &am33xx_eqep0_hwmod,
2700 .clk = "l4ls_gclk", 1960 .clk = "l4ls_gclk",
2701 .addr = am33xx_eqep0_addr_space,
2702 .user = OCP_USER_MPU, 1961 .user = OCP_USER_MPU,
2703}; 1962};
2704 1963
2705static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2706 {
2707 .pa_start = 0x48300200,
2708 .pa_end = 0x48300200 + SZ_128 - 1,
2709 },
2710 { }
2711};
2712
2713static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = { 1964static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2714 .master = &am33xx_epwmss0_hwmod, 1965 .master = &am33xx_epwmss0_hwmod,
2715 .slave = &am33xx_ehrpwm0_hwmod, 1966 .slave = &am33xx_ehrpwm0_hwmod,
2716 .clk = "l4ls_gclk", 1967 .clk = "l4ls_gclk",
2717 .addr = am33xx_ehrpwm0_addr_space,
2718 .user = OCP_USER_MPU, 1968 .user = OCP_USER_MPU,
2719}; 1969};
2720 1970
@@ -2736,51 +1986,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2736 .user = OCP_USER_MPU, 1986 .user = OCP_USER_MPU,
2737}; 1987};
2738 1988
2739static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2740 {
2741 .pa_start = 0x48302100,
2742 .pa_end = 0x48302100 + SZ_128 - 1,
2743 },
2744 { }
2745};
2746
2747static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = { 1989static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2748 .master = &am33xx_epwmss1_hwmod, 1990 .master = &am33xx_epwmss1_hwmod,
2749 .slave = &am33xx_ecap1_hwmod, 1991 .slave = &am33xx_ecap1_hwmod,
2750 .clk = "l4ls_gclk", 1992 .clk = "l4ls_gclk",
2751 .addr = am33xx_ecap1_addr_space,
2752 .user = OCP_USER_MPU, 1993 .user = OCP_USER_MPU,
2753}; 1994};
2754 1995
2755static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2756 {
2757 .pa_start = 0x48302180,
2758 .pa_end = 0x48302180 + SZ_128 - 1,
2759 },
2760 { }
2761};
2762
2763static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = { 1996static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2764 .master = &am33xx_epwmss1_hwmod, 1997 .master = &am33xx_epwmss1_hwmod,
2765 .slave = &am33xx_eqep1_hwmod, 1998 .slave = &am33xx_eqep1_hwmod,
2766 .clk = "l4ls_gclk", 1999 .clk = "l4ls_gclk",
2767 .addr = am33xx_eqep1_addr_space,
2768 .user = OCP_USER_MPU, 2000 .user = OCP_USER_MPU,
2769}; 2001};
2770 2002
2771static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2772 {
2773 .pa_start = 0x48302200,
2774 .pa_end = 0x48302200 + SZ_128 - 1,
2775 },
2776 { }
2777};
2778
2779static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = { 2003static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2780 .master = &am33xx_epwmss1_hwmod, 2004 .master = &am33xx_epwmss1_hwmod,
2781 .slave = &am33xx_ehrpwm1_hwmod, 2005 .slave = &am33xx_ehrpwm1_hwmod,
2782 .clk = "l4ls_gclk", 2006 .clk = "l4ls_gclk",
2783 .addr = am33xx_ehrpwm1_addr_space,
2784 .user = OCP_USER_MPU, 2007 .user = OCP_USER_MPU,
2785}; 2008};
2786 2009
@@ -2801,51 +2024,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2801 .user = OCP_USER_MPU, 2024 .user = OCP_USER_MPU,
2802}; 2025};
2803 2026
2804static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2805 {
2806 .pa_start = 0x48304100,
2807 .pa_end = 0x48304100 + SZ_128 - 1,
2808 },
2809 { }
2810};
2811
2812static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = { 2027static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2813 .master = &am33xx_epwmss2_hwmod, 2028 .master = &am33xx_epwmss2_hwmod,
2814 .slave = &am33xx_ecap2_hwmod, 2029 .slave = &am33xx_ecap2_hwmod,
2815 .clk = "l4ls_gclk", 2030 .clk = "l4ls_gclk",
2816 .addr = am33xx_ecap2_addr_space,
2817 .user = OCP_USER_MPU, 2031 .user = OCP_USER_MPU,
2818}; 2032};
2819 2033
2820static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2821 {
2822 .pa_start = 0x48304180,
2823 .pa_end = 0x48304180 + SZ_128 - 1,
2824 },
2825 { }
2826};
2827
2828static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = { 2034static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2829 .master = &am33xx_epwmss2_hwmod, 2035 .master = &am33xx_epwmss2_hwmod,
2830 .slave = &am33xx_eqep2_hwmod, 2036 .slave = &am33xx_eqep2_hwmod,
2831 .clk = "l4ls_gclk", 2037 .clk = "l4ls_gclk",
2832 .addr = am33xx_eqep2_addr_space,
2833 .user = OCP_USER_MPU, 2038 .user = OCP_USER_MPU,
2834}; 2039};
2835 2040
2836static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2837 {
2838 .pa_start = 0x48304200,
2839 .pa_end = 0x48304200 + SZ_128 - 1,
2840 },
2841 { }
2842};
2843
2844static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = { 2041static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2845 .master = &am33xx_epwmss2_hwmod, 2042 .master = &am33xx_epwmss2_hwmod,
2846 .slave = &am33xx_ehrpwm2_hwmod, 2043 .slave = &am33xx_ehrpwm2_hwmod,
2847 .clk = "l4ls_gclk", 2044 .clk = "l4ls_gclk",
2848 .addr = am33xx_ehrpwm2_addr_space,
2849 .user = OCP_USER_MPU, 2045 .user = OCP_USER_MPU,
2850}; 2046};
2851 2047
@@ -2868,37 +2064,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2868}; 2064};
2869 2065
2870/* i2c2 */ 2066/* i2c2 */
2871static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2872 {
2873 .pa_start = 0x4802A000,
2874 .pa_end = 0x4802A000 + SZ_4K - 1,
2875 .flags = ADDR_TYPE_RT,
2876 },
2877 { }
2878};
2879
2880static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = { 2067static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2881 .master = &am33xx_l4_ls_hwmod, 2068 .master = &am33xx_l4_ls_hwmod,
2882 .slave = &am33xx_i2c2_hwmod, 2069 .slave = &am33xx_i2c2_hwmod,
2883 .clk = "l4ls_gclk", 2070 .clk = "l4ls_gclk",
2884 .addr = am33xx_i2c2_addr_space,
2885 .user = OCP_USER_MPU, 2071 .user = OCP_USER_MPU,
2886}; 2072};
2887 2073
2888static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2889 {
2890 .pa_start = 0x4819C000,
2891 .pa_end = 0x4819C000 + SZ_4K - 1,
2892 .flags = ADDR_TYPE_RT
2893 },
2894 { }
2895};
2896
2897static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = { 2074static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2898 .master = &am33xx_l4_ls_hwmod, 2075 .master = &am33xx_l4_ls_hwmod,
2899 .slave = &am33xx_i2c3_hwmod, 2076 .slave = &am33xx_i2c3_hwmod,
2900 .clk = "l4ls_gclk", 2077 .clk = "l4ls_gclk",
2901 .addr = am33xx_i2c3_addr_space,
2902 .user = OCP_USER_MPU, 2078 .user = OCP_USER_MPU,
2903}; 2079};
2904 2080
@@ -2938,20 +2114,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2938}; 2114};
2939 2115
2940/* l4 ls -> spinlock */ 2116/* l4 ls -> spinlock */
2941static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2942 {
2943 .pa_start = 0x480Ca000,
2944 .pa_end = 0x480Ca000 + SZ_4K - 1,
2945 .flags = ADDR_TYPE_RT
2946 },
2947 { }
2948};
2949
2950static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = { 2117static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2951 .master = &am33xx_l4_ls_hwmod, 2118 .master = &am33xx_l4_ls_hwmod,
2952 .slave = &am33xx_spinlock_hwmod, 2119 .slave = &am33xx_spinlock_hwmod,
2953 .clk = "l4ls_gclk", 2120 .clk = "l4ls_gclk",
2954 .addr = am33xx_spinlock_addrs,
2955 .user = OCP_USER_MPU, 2121 .user = OCP_USER_MPU,
2956}; 2122};
2957 2123
@@ -2973,24 +2139,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2973 .user = OCP_USER_MPU, 2139 .user = OCP_USER_MPU,
2974}; 2140};
2975 2141
2976/* l3 s -> mcasp0 data */
2977static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2978 {
2979 .pa_start = 0x46000000,
2980 .pa_end = 0x46000000 + SZ_4M - 1,
2981 .flags = ADDR_TYPE_RT
2982 },
2983 { }
2984};
2985
2986static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2987 .master = &am33xx_l3_s_hwmod,
2988 .slave = &am33xx_mcasp0_hwmod,
2989 .clk = "l3s_gclk",
2990 .addr = am33xx_mcasp0_data_addr_space,
2991 .user = OCP_USER_SDMA,
2992};
2993
2994/* l4 ls -> mcasp1 */ 2142/* l4 ls -> mcasp1 */
2995static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = { 2143static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2996 { 2144 {
@@ -3009,24 +2157,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
3009 .user = OCP_USER_MPU, 2157 .user = OCP_USER_MPU,
3010}; 2158};
3011 2159
3012/* l3 s -> mcasp1 data */
3013static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
3014 {
3015 .pa_start = 0x46400000,
3016 .pa_end = 0x46400000 + SZ_4M - 1,
3017 .flags = ADDR_TYPE_RT
3018 },
3019 { }
3020};
3021
3022static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
3023 .master = &am33xx_l3_s_hwmod,
3024 .slave = &am33xx_mcasp1_hwmod,
3025 .clk = "l3s_gclk",
3026 .addr = am33xx_mcasp1_data_addr_space,
3027 .user = OCP_USER_SDMA,
3028};
3029
3030/* l4 ls -> mmc0 */ 2160/* l4 ls -> mmc0 */
3031static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = { 2161static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
3032 { 2162 {
@@ -3082,182 +2212,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3082}; 2212};
3083 2213
3084/* l4 ls -> mcspi0 */ 2214/* l4 ls -> mcspi0 */
3085static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3086 {
3087 .pa_start = 0x48030000,
3088 .pa_end = 0x48030000 + SZ_1K - 1,
3089 .flags = ADDR_TYPE_RT,
3090 },
3091 { }
3092};
3093
3094static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = { 2215static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3095 .master = &am33xx_l4_ls_hwmod, 2216 .master = &am33xx_l4_ls_hwmod,
3096 .slave = &am33xx_spi0_hwmod, 2217 .slave = &am33xx_spi0_hwmod,
3097 .clk = "l4ls_gclk", 2218 .clk = "l4ls_gclk",
3098 .addr = am33xx_mcspi0_addr_space,
3099 .user = OCP_USER_MPU, 2219 .user = OCP_USER_MPU,
3100}; 2220};
3101 2221
3102/* l4 ls -> mcspi1 */ 2222/* l4 ls -> mcspi1 */
3103static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3104 {
3105 .pa_start = 0x481A0000,
3106 .pa_end = 0x481A0000 + SZ_1K - 1,
3107 .flags = ADDR_TYPE_RT,
3108 },
3109 { }
3110};
3111
3112static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = { 2223static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3113 .master = &am33xx_l4_ls_hwmod, 2224 .master = &am33xx_l4_ls_hwmod,
3114 .slave = &am33xx_spi1_hwmod, 2225 .slave = &am33xx_spi1_hwmod,
3115 .clk = "l4ls_gclk", 2226 .clk = "l4ls_gclk",
3116 .addr = am33xx_mcspi1_addr_space,
3117 .user = OCP_USER_MPU, 2227 .user = OCP_USER_MPU,
3118}; 2228};
3119 2229
3120/* l4 wkup -> timer1 */ 2230/* l4 wkup -> timer1 */
3121static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3122 {
3123 .pa_start = 0x44E31000,
3124 .pa_end = 0x44E31000 + SZ_1K - 1,
3125 .flags = ADDR_TYPE_RT
3126 },
3127 { }
3128};
3129
3130static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = { 2231static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3131 .master = &am33xx_l4_wkup_hwmod, 2232 .master = &am33xx_l4_wkup_hwmod,
3132 .slave = &am33xx_timer1_hwmod, 2233 .slave = &am33xx_timer1_hwmod,
3133 .clk = "dpll_core_m4_div2_ck", 2234 .clk = "dpll_core_m4_div2_ck",
3134 .addr = am33xx_timer1_addr_space,
3135 .user = OCP_USER_MPU, 2235 .user = OCP_USER_MPU,
3136}; 2236};
3137 2237
3138/* l4 per -> timer2 */ 2238/* l4 per -> timer2 */
3139static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3140 {
3141 .pa_start = 0x48040000,
3142 .pa_end = 0x48040000 + SZ_1K - 1,
3143 .flags = ADDR_TYPE_RT
3144 },
3145 { }
3146};
3147
3148static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = { 2239static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3149 .master = &am33xx_l4_ls_hwmod, 2240 .master = &am33xx_l4_ls_hwmod,
3150 .slave = &am33xx_timer2_hwmod, 2241 .slave = &am33xx_timer2_hwmod,
3151 .clk = "l4ls_gclk", 2242 .clk = "l4ls_gclk",
3152 .addr = am33xx_timer2_addr_space,
3153 .user = OCP_USER_MPU, 2243 .user = OCP_USER_MPU,
3154}; 2244};
3155 2245
3156/* l4 per -> timer3 */ 2246/* l4 per -> timer3 */
3157static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3158 {
3159 .pa_start = 0x48042000,
3160 .pa_end = 0x48042000 + SZ_1K - 1,
3161 .flags = ADDR_TYPE_RT
3162 },
3163 { }
3164};
3165
3166static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = { 2247static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3167 .master = &am33xx_l4_ls_hwmod, 2248 .master = &am33xx_l4_ls_hwmod,
3168 .slave = &am33xx_timer3_hwmod, 2249 .slave = &am33xx_timer3_hwmod,
3169 .clk = "l4ls_gclk", 2250 .clk = "l4ls_gclk",
3170 .addr = am33xx_timer3_addr_space,
3171 .user = OCP_USER_MPU, 2251 .user = OCP_USER_MPU,
3172}; 2252};
3173 2253
3174/* l4 per -> timer4 */ 2254/* l4 per -> timer4 */
3175static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3176 {
3177 .pa_start = 0x48044000,
3178 .pa_end = 0x48044000 + SZ_1K - 1,
3179 .flags = ADDR_TYPE_RT
3180 },
3181 { }
3182};
3183
3184static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = { 2255static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3185 .master = &am33xx_l4_ls_hwmod, 2256 .master = &am33xx_l4_ls_hwmod,
3186 .slave = &am33xx_timer4_hwmod, 2257 .slave = &am33xx_timer4_hwmod,
3187 .clk = "l4ls_gclk", 2258 .clk = "l4ls_gclk",
3188 .addr = am33xx_timer4_addr_space,
3189 .user = OCP_USER_MPU, 2259 .user = OCP_USER_MPU,
3190}; 2260};
3191 2261
3192/* l4 per -> timer5 */ 2262/* l4 per -> timer5 */
3193static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3194 {
3195 .pa_start = 0x48046000,
3196 .pa_end = 0x48046000 + SZ_1K - 1,
3197 .flags = ADDR_TYPE_RT
3198 },
3199 { }
3200};
3201
3202static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = { 2263static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3203 .master = &am33xx_l4_ls_hwmod, 2264 .master = &am33xx_l4_ls_hwmod,
3204 .slave = &am33xx_timer5_hwmod, 2265 .slave = &am33xx_timer5_hwmod,
3205 .clk = "l4ls_gclk", 2266 .clk = "l4ls_gclk",
3206 .addr = am33xx_timer5_addr_space,
3207 .user = OCP_USER_MPU, 2267 .user = OCP_USER_MPU,
3208}; 2268};
3209 2269
3210/* l4 per -> timer6 */ 2270/* l4 per -> timer6 */
3211static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3212 {
3213 .pa_start = 0x48048000,
3214 .pa_end = 0x48048000 + SZ_1K - 1,
3215 .flags = ADDR_TYPE_RT
3216 },
3217 { }
3218};
3219
3220static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = { 2271static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3221 .master = &am33xx_l4_ls_hwmod, 2272 .master = &am33xx_l4_ls_hwmod,
3222 .slave = &am33xx_timer6_hwmod, 2273 .slave = &am33xx_timer6_hwmod,
3223 .clk = "l4ls_gclk", 2274 .clk = "l4ls_gclk",
3224 .addr = am33xx_timer6_addr_space,
3225 .user = OCP_USER_MPU, 2275 .user = OCP_USER_MPU,
3226}; 2276};
3227 2277
3228/* l4 per -> timer7 */ 2278/* l4 per -> timer7 */
3229static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3230 {
3231 .pa_start = 0x4804A000,
3232 .pa_end = 0x4804A000 + SZ_1K - 1,
3233 .flags = ADDR_TYPE_RT
3234 },
3235 { }
3236};
3237
3238static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = { 2279static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3239 .master = &am33xx_l4_ls_hwmod, 2280 .master = &am33xx_l4_ls_hwmod,
3240 .slave = &am33xx_timer7_hwmod, 2281 .slave = &am33xx_timer7_hwmod,
3241 .clk = "l4ls_gclk", 2282 .clk = "l4ls_gclk",
3242 .addr = am33xx_timer7_addr_space,
3243 .user = OCP_USER_MPU, 2283 .user = OCP_USER_MPU,
3244}; 2284};
3245 2285
3246/* l3 main -> tpcc */ 2286/* l3 main -> tpcc */
3247static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3248 {
3249 .pa_start = 0x49000000,
3250 .pa_end = 0x49000000 + SZ_32K - 1,
3251 .flags = ADDR_TYPE_RT
3252 },
3253 { }
3254};
3255
3256static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = { 2287static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3257 .master = &am33xx_l3_main_hwmod, 2288 .master = &am33xx_l3_main_hwmod,
3258 .slave = &am33xx_tpcc_hwmod, 2289 .slave = &am33xx_tpcc_hwmod,
3259 .clk = "l3_gclk", 2290 .clk = "l3_gclk",
3260 .addr = am33xx_tpcc_addr_space,
3261 .user = OCP_USER_MPU, 2291 .user = OCP_USER_MPU,
3262}; 2292};
3263 2293
@@ -3316,160 +2346,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3316}; 2346};
3317 2347
3318/* l4 wkup -> uart1 */ 2348/* l4 wkup -> uart1 */
3319static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3320 {
3321 .pa_start = 0x44E09000,
3322 .pa_end = 0x44E09000 + SZ_8K - 1,
3323 .flags = ADDR_TYPE_RT,
3324 },
3325 { }
3326};
3327
3328static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = { 2349static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3329 .master = &am33xx_l4_wkup_hwmod, 2350 .master = &am33xx_l4_wkup_hwmod,
3330 .slave = &am33xx_uart1_hwmod, 2351 .slave = &am33xx_uart1_hwmod,
3331 .clk = "dpll_core_m4_div2_ck", 2352 .clk = "dpll_core_m4_div2_ck",
3332 .addr = am33xx_uart1_addr_space,
3333 .user = OCP_USER_MPU, 2353 .user = OCP_USER_MPU,
3334}; 2354};
3335 2355
3336/* l4 ls -> uart2 */ 2356/* l4 ls -> uart2 */
3337static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3338 {
3339 .pa_start = 0x48022000,
3340 .pa_end = 0x48022000 + SZ_8K - 1,
3341 .flags = ADDR_TYPE_RT,
3342 },
3343 { }
3344};
3345
3346static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = { 2357static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3347 .master = &am33xx_l4_ls_hwmod, 2358 .master = &am33xx_l4_ls_hwmod,
3348 .slave = &am33xx_uart2_hwmod, 2359 .slave = &am33xx_uart2_hwmod,
3349 .clk = "l4ls_gclk", 2360 .clk = "l4ls_gclk",
3350 .addr = am33xx_uart2_addr_space,
3351 .user = OCP_USER_MPU, 2361 .user = OCP_USER_MPU,
3352}; 2362};
3353 2363
3354/* l4 ls -> uart3 */ 2364/* l4 ls -> uart3 */
3355static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3356 {
3357 .pa_start = 0x48024000,
3358 .pa_end = 0x48024000 + SZ_8K - 1,
3359 .flags = ADDR_TYPE_RT,
3360 },
3361 { }
3362};
3363
3364static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = { 2365static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3365 .master = &am33xx_l4_ls_hwmod, 2366 .master = &am33xx_l4_ls_hwmod,
3366 .slave = &am33xx_uart3_hwmod, 2367 .slave = &am33xx_uart3_hwmod,
3367 .clk = "l4ls_gclk", 2368 .clk = "l4ls_gclk",
3368 .addr = am33xx_uart3_addr_space,
3369 .user = OCP_USER_MPU, 2369 .user = OCP_USER_MPU,
3370}; 2370};
3371 2371
3372/* l4 ls -> uart4 */ 2372/* l4 ls -> uart4 */
3373static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3374 {
3375 .pa_start = 0x481A6000,
3376 .pa_end = 0x481A6000 + SZ_8K - 1,
3377 .flags = ADDR_TYPE_RT,
3378 },
3379 { }
3380};
3381
3382static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = { 2373static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3383 .master = &am33xx_l4_ls_hwmod, 2374 .master = &am33xx_l4_ls_hwmod,
3384 .slave = &am33xx_uart4_hwmod, 2375 .slave = &am33xx_uart4_hwmod,
3385 .clk = "l4ls_gclk", 2376 .clk = "l4ls_gclk",
3386 .addr = am33xx_uart4_addr_space,
3387 .user = OCP_USER_MPU, 2377 .user = OCP_USER_MPU,
3388}; 2378};
3389 2379
3390/* l4 ls -> uart5 */ 2380/* l4 ls -> uart5 */
3391static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3392 {
3393 .pa_start = 0x481A8000,
3394 .pa_end = 0x481A8000 + SZ_8K - 1,
3395 .flags = ADDR_TYPE_RT,
3396 },
3397 { }
3398};
3399
3400static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = { 2381static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3401 .master = &am33xx_l4_ls_hwmod, 2382 .master = &am33xx_l4_ls_hwmod,
3402 .slave = &am33xx_uart5_hwmod, 2383 .slave = &am33xx_uart5_hwmod,
3403 .clk = "l4ls_gclk", 2384 .clk = "l4ls_gclk",
3404 .addr = am33xx_uart5_addr_space,
3405 .user = OCP_USER_MPU, 2385 .user = OCP_USER_MPU,
3406}; 2386};
3407 2387
3408/* l4 ls -> uart6 */ 2388/* l4 ls -> uart6 */
3409static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3410 {
3411 .pa_start = 0x481aa000,
3412 .pa_end = 0x481aa000 + SZ_8K - 1,
3413 .flags = ADDR_TYPE_RT,
3414 },
3415 { }
3416};
3417
3418static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = { 2389static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3419 .master = &am33xx_l4_ls_hwmod, 2390 .master = &am33xx_l4_ls_hwmod,
3420 .slave = &am33xx_uart6_hwmod, 2391 .slave = &am33xx_uart6_hwmod,
3421 .clk = "l4ls_gclk", 2392 .clk = "l4ls_gclk",
3422 .addr = am33xx_uart6_addr_space,
3423 .user = OCP_USER_MPU, 2393 .user = OCP_USER_MPU,
3424}; 2394};
3425 2395
3426/* l4 wkup -> wd_timer1 */ 2396/* l4 wkup -> wd_timer1 */
3427static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3428 {
3429 .pa_start = 0x44e35000,
3430 .pa_end = 0x44e35000 + SZ_4K - 1,
3431 .flags = ADDR_TYPE_RT
3432 },
3433 { }
3434};
3435
3436static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = { 2397static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3437 .master = &am33xx_l4_wkup_hwmod, 2398 .master = &am33xx_l4_wkup_hwmod,
3438 .slave = &am33xx_wd_timer1_hwmod, 2399 .slave = &am33xx_wd_timer1_hwmod,
3439 .clk = "dpll_core_m4_div2_ck", 2400 .clk = "dpll_core_m4_div2_ck",
3440 .addr = am33xx_wd_timer1_addrs,
3441 .user = OCP_USER_MPU, 2401 .user = OCP_USER_MPU,
3442}; 2402};
3443 2403
3444/* usbss */ 2404/* usbss */
3445/* l3 s -> USBSS interface */ 2405/* l3 s -> USBSS interface */
3446static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3447 {
3448 .name = "usbss",
3449 .pa_start = 0x47400000,
3450 .pa_end = 0x47400000 + SZ_4K - 1,
3451 .flags = ADDR_TYPE_RT
3452 },
3453 {
3454 .name = "musb0",
3455 .pa_start = 0x47401000,
3456 .pa_end = 0x47401000 + SZ_2K - 1,
3457 .flags = ADDR_TYPE_RT
3458 },
3459 {
3460 .name = "musb1",
3461 .pa_start = 0x47401800,
3462 .pa_end = 0x47401800 + SZ_2K - 1,
3463 .flags = ADDR_TYPE_RT
3464 },
3465 { }
3466};
3467
3468static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = { 2406static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3469 .master = &am33xx_l3_s_hwmod, 2407 .master = &am33xx_l3_s_hwmod,
3470 .slave = &am33xx_usbss_hwmod, 2408 .slave = &am33xx_usbss_hwmod,
3471 .clk = "l3s_gclk", 2409 .clk = "l3s_gclk",
3472 .addr = am33xx_usbss_addr_space,
3473 .user = OCP_USER_MPU, 2410 .user = OCP_USER_MPU,
3474 .flags = OCPIF_SWSUP_IDLE, 2411 .flags = OCPIF_SWSUP_IDLE,
3475}; 2412};
@@ -3518,13 +2455,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
3518}; 2455};
3519 2456
3520static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 2457static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3521 &am33xx_l4_fw__emif_fw,
3522 &am33xx_l3_main__emif, 2458 &am33xx_l3_main__emif,
3523 &am33xx_mpu__l3_main, 2459 &am33xx_mpu__l3_main,
3524 &am33xx_mpu__prcm, 2460 &am33xx_mpu__prcm,
3525 &am33xx_l3_s__l4_ls, 2461 &am33xx_l3_s__l4_ls,
3526 &am33xx_l3_s__l4_wkup, 2462 &am33xx_l3_s__l4_wkup,
3527 &am33xx_l3_s__l4_fw,
3528 &am33xx_l3_main__l4_hs, 2463 &am33xx_l3_main__l4_hs,
3529 &am33xx_l3_main__l3_s, 2464 &am33xx_l3_main__l3_s,
3530 &am33xx_l3_main__l3_instr, 2465 &am33xx_l3_main__l3_instr,
@@ -3554,9 +2489,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3554 &am33xx_l4_per__i2c3, 2489 &am33xx_l4_per__i2c3,
3555 &am33xx_l4_per__mailbox, 2490 &am33xx_l4_per__mailbox,
3556 &am33xx_l4_ls__mcasp0, 2491 &am33xx_l4_ls__mcasp0,
3557 &am33xx_l3_s__mcasp0_data,
3558 &am33xx_l4_ls__mcasp1, 2492 &am33xx_l4_ls__mcasp1,
3559 &am33xx_l3_s__mcasp1_data,
3560 &am33xx_l4_ls__mmc0, 2493 &am33xx_l4_ls__mmc0,
3561 &am33xx_l4_ls__mmc1, 2494 &am33xx_l4_ls__mmc1,
3562 &am33xx_l3_s__mmc2, 2495 &am33xx_l3_s__mmc2,
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 09:42:17 -0400