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-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c1931
1 files changed, 0 insertions, 1931 deletions
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
deleted file mode 100644
index 3662f4d4c8ea..000000000000
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ /dev/null
@@ -1,1931 +0,0 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/clk-private.h>
21#include <linux/list.h>
22
23#include "soc.h"
24#include "iomap.h"
25#include "clock.h"
26#include "clock2xxx.h"
27#include "opp2xxx.h"
28#include "cm2xxx.h"
29#include "prm2xxx.h"
30#include "prm-regbits-24xx.h"
31#include "cm-regbits-24xx.h"
32#include "sdrc.h"
33#include "control.h"
34
35#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
36
37/*
38 * 2420 clock tree.
39 *
40 * NOTE:In many cases here we are assigning a 'default' parent. In
41 * many cases the parent is selectable. The set parent calls will
42 * also switch sources.
43 *
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
46 *
47 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
51 * clocks.
52 */
53
54DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
55
56DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
57
58DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
59
60static struct clk osc_ck;
61
62static const struct clk_ops osc_ck_ops = {
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static struct clk func_96m_ck;
226
227static const char *func_96m_ck_parent_names[] = {
228 "apll96_ck",
229};
230
231DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
232DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
233
234static struct clk cam_fck;
235
236static const char *cam_fck_parent_names[] = {
237 "func_96m_ck",
238};
239
240static struct clk_hw_omap cam_fck_hw = {
241 .hw = {
242 .clk = &cam_fck,
243 },
244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
245 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
246 .clkdm_name = "core_l3_clkdm",
247};
248
249DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
250
251static struct clk cam_ick;
252
253static struct clk_hw_omap cam_ick_hw = {
254 .hw = {
255 .clk = &cam_ick,
256 },
257 .ops = &clkhwops_iclk,
258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
259 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
260 .clkdm_name = "core_l4_clkdm",
261};
262
263DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
264
265static struct clk des_ick;
266
267static struct clk_hw_omap des_ick_hw = {
268 .hw = {
269 .clk = &des_ick,
270 },
271 .ops = &clkhwops_iclk_wait,
272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
273 .enable_bit = OMAP24XX_EN_DES_SHIFT,
274 .clkdm_name = "core_l4_clkdm",
275};
276
277DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
278
279static const struct clksel_rate dsp_fck_core_rates[] = {
280 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
281 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
282 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
283 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
284 { .div = 6, .val = 6, .flags = RATE_IN_242X },
285 { .div = 8, .val = 8, .flags = RATE_IN_242X },
286 { .div = 12, .val = 12, .flags = RATE_IN_242X },
287 { .div = 0 }
288};
289
290static const struct clksel dsp_fck_clksel[] = {
291 { .parent = &core_ck, .rates = dsp_fck_core_rates },
292 { .parent = NULL },
293};
294
295static const char *dsp_fck_parent_names[] = {
296 "core_ck",
297};
298
299static const struct clk_ops dsp_fck_ops = {
300 .init = &omap2_init_clk_clkdm,
301 .enable = &omap2_dflt_clk_enable,
302 .disable = &omap2_dflt_clk_disable,
303 .is_enabled = &omap2_dflt_clk_is_enabled,
304 .recalc_rate = &omap2_clksel_recalc,
305 .set_rate = &omap2_clksel_set_rate,
306 .round_rate = &omap2_clksel_round_rate,
307};
308
309DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
311 OMAP24XX_CLKSEL_DSP_MASK,
312 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
313 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
314 dsp_fck_parent_names, dsp_fck_ops);
315
316static const struct clksel dsp_ick_clksel[] = {
317 { .parent = &dsp_fck, .rates = dsp_ick_rates },
318 { .parent = NULL },
319};
320
321static const char *dsp_ick_parent_names[] = {
322 "dsp_fck",
323};
324
325DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
326 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
327 OMAP24XX_CLKSEL_DSP_IF_MASK,
328 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
329 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
330 dsp_ick_parent_names, dsp_fck_ops);
331
332static const struct clksel_rate dss1_fck_sys_rates[] = {
333 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
334 { .div = 0 }
335};
336
337static const struct clksel_rate dss1_fck_core_rates[] = {
338 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
339 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
340 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
341 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
342 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
343 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
344 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
345 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
346 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
347 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
348 { .div = 0 }
349};
350
351static const struct clksel dss1_fck_clksel[] = {
352 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
353 { .parent = &core_ck, .rates = dss1_fck_core_rates },
354 { .parent = NULL },
355};
356
357static const char *dss1_fck_parent_names[] = {
358 "sys_ck", "core_ck",
359};
360
361static struct clk dss1_fck;
362
363static const struct clk_ops dss1_fck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap2_dflt_clk_enable,
366 .disable = &omap2_dflt_clk_disable,
367 .is_enabled = &omap2_dflt_clk_is_enabled,
368 .recalc_rate = &omap2_clksel_recalc,
369 .get_parent = &omap2_clksel_find_parent_index,
370 .set_parent = &omap2_clksel_set_parent,
371};
372
373DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
374 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
375 OMAP24XX_CLKSEL_DSS1_MASK,
376 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
377 OMAP24XX_EN_DSS1_SHIFT, NULL,
378 dss1_fck_parent_names, dss1_fck_ops);
379
380static const struct clksel_rate dss2_fck_sys_rates[] = {
381 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
382 { .div = 0 }
383};
384
385static const struct clksel_rate dss2_fck_48m_rates[] = {
386 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
387 { .div = 0 }
388};
389
390static const struct clksel_rate func_48m_apll96_rates[] = {
391 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
392 { .div = 0 }
393};
394
395static const struct clksel_rate func_48m_alt_rates[] = {
396 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
397 { .div = 0 }
398};
399
400static const struct clksel func_48m_clksel[] = {
401 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
402 { .parent = &alt_ck, .rates = func_48m_alt_rates },
403 { .parent = NULL },
404};
405
406static const char *func_48m_ck_parent_names[] = {
407 "apll96_ck", "alt_ck",
408};
409
410static struct clk func_48m_ck;
411
412static const struct clk_ops func_48m_ck_ops = {
413 .init = &omap2_init_clk_clkdm,
414 .recalc_rate = &omap2_clksel_recalc,
415 .set_rate = &omap2_clksel_set_rate,
416 .round_rate = &omap2_clksel_round_rate,
417 .get_parent = &omap2_clksel_find_parent_index,
418 .set_parent = &omap2_clksel_set_parent,
419};
420
421static struct clk_hw_omap func_48m_ck_hw = {
422 .hw = {
423 .clk = &func_48m_ck,
424 },
425 .clksel = func_48m_clksel,
426 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
427 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
428 .clkdm_name = "wkup_clkdm",
429};
430
431DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
432
433static const struct clksel dss2_fck_clksel[] = {
434 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
435 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
436 { .parent = NULL },
437};
438
439static const char *dss2_fck_parent_names[] = {
440 "sys_ck", "func_48m_ck",
441};
442
443DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
444 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
445 OMAP24XX_CLKSEL_DSS2_MASK,
446 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
447 OMAP24XX_EN_DSS2_SHIFT, NULL,
448 dss2_fck_parent_names, dss1_fck_ops);
449
450static const char *func_54m_ck_parent_names[] = {
451 "apll54_ck", "alt_ck",
452};
453
454DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
455 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
456 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
457 0x0, NULL);
458
459static struct clk dss_54m_fck;
460
461static const char *dss_54m_fck_parent_names[] = {
462 "func_54m_ck",
463};
464
465static struct clk_hw_omap dss_54m_fck_hw = {
466 .hw = {
467 .clk = &dss_54m_fck,
468 },
469 .ops = &clkhwops_wait,
470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
471 .enable_bit = OMAP24XX_EN_TV_SHIFT,
472 .clkdm_name = "dss_clkdm",
473};
474
475DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
476
477static struct clk dss_ick;
478
479static struct clk_hw_omap dss_ick_hw = {
480 .hw = {
481 .clk = &dss_ick,
482 },
483 .ops = &clkhwops_iclk,
484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
485 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
486 .clkdm_name = "dss_clkdm",
487};
488
489DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
490
491static struct clk eac_fck;
492
493static struct clk_hw_omap eac_fck_hw = {
494 .hw = {
495 .clk = &eac_fck,
496 },
497 .ops = &clkhwops_wait,
498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
499 .enable_bit = OMAP2420_EN_EAC_SHIFT,
500 .clkdm_name = "core_l4_clkdm",
501};
502
503DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
504
505static struct clk eac_ick;
506
507static struct clk_hw_omap eac_ick_hw = {
508 .hw = {
509 .clk = &eac_ick,
510 },
511 .ops = &clkhwops_iclk_wait,
512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
513 .enable_bit = OMAP2420_EN_EAC_SHIFT,
514 .clkdm_name = "core_l4_clkdm",
515};
516
517DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
518
519static struct clk emul_ck;
520
521static struct clk_hw_omap emul_ck_hw = {
522 .hw = {
523 .clk = &emul_ck,
524 },
525 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
526 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
527 .clkdm_name = "wkup_clkdm",
528};
529
530DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
531
532DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
533
534static struct clk fac_fck;
535
536static const char *fac_fck_parent_names[] = {
537 "func_12m_ck",
538};
539
540static struct clk_hw_omap fac_fck_hw = {
541 .hw = {
542 .clk = &fac_fck,
543 },
544 .ops = &clkhwops_wait,
545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
546 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
547 .clkdm_name = "core_l4_clkdm",
548};
549
550DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
551
552static struct clk fac_ick;
553
554static struct clk_hw_omap fac_ick_hw = {
555 .hw = {
556 .clk = &fac_ick,
557 },
558 .ops = &clkhwops_iclk_wait,
559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
560 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
561 .clkdm_name = "core_l4_clkdm",
562};
563
564DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
565
566static const struct clksel gfx_fck_clksel[] = {
567 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
568 { .parent = NULL },
569};
570
571static const char *gfx_2d_fck_parent_names[] = {
572 "core_l3_ck",
573};
574
575DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
576 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
577 OMAP_CLKSEL_GFX_MASK,
578 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
579 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
580 gfx_2d_fck_parent_names, dsp_fck_ops);
581
582DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
583 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
584 OMAP_CLKSEL_GFX_MASK,
585 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
586 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
587 gfx_2d_fck_parent_names, dsp_fck_ops);
588
589static struct clk gfx_ick;
590
591static const char *gfx_ick_parent_names[] = {
592 "core_l3_ck",
593};
594
595static struct clk_hw_omap gfx_ick_hw = {
596 .hw = {
597 .clk = &gfx_ick,
598 },
599 .ops = &clkhwops_wait,
600 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
601 .enable_bit = OMAP_EN_GFX_SHIFT,
602 .clkdm_name = "gfx_clkdm",
603};
604
605DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
606
607static struct clk gpios_fck;
608
609static const char *gpios_fck_parent_names[] = {
610 "func_32k_ck",
611};
612
613static struct clk_hw_omap gpios_fck_hw = {
614 .hw = {
615 .clk = &gpios_fck,
616 },
617 .ops = &clkhwops_wait,
618 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
619 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
620 .clkdm_name = "wkup_clkdm",
621};
622
623DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
624
625static struct clk gpios_ick;
626
627static const char *gpios_ick_parent_names[] = {
628 "sys_ck",
629};
630
631static struct clk_hw_omap gpios_ick_hw = {
632 .hw = {
633 .clk = &gpios_ick,
634 },
635 .ops = &clkhwops_iclk_wait,
636 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
637 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
638 .clkdm_name = "wkup_clkdm",
639};
640
641DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
642
643static struct clk gpmc_fck;
644
645static struct clk_hw_omap gpmc_fck_hw = {
646 .hw = {
647 .clk = &gpmc_fck,
648 },
649 .ops = &clkhwops_iclk,
650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
651 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
652 .flags = ENABLE_ON_INIT,
653 .clkdm_name = "core_l3_clkdm",
654};
655
656DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
657
658static const struct clksel_rate gpt_alt_rates[] = {
659 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
660 { .div = 0 }
661};
662
663static const struct clksel omap24xx_gpt_clksel[] = {
664 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
665 { .parent = &sys_ck, .rates = gpt_sys_rates },
666 { .parent = &alt_ck, .rates = gpt_alt_rates },
667 { .parent = NULL },
668};
669
670static const char *gpt10_fck_parent_names[] = {
671 "func_32k_ck", "sys_ck", "alt_ck",
672};
673
674DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
675 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
676 OMAP24XX_CLKSEL_GPT10_MASK,
677 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
678 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
679 gpt10_fck_parent_names, dss1_fck_ops);
680
681static struct clk gpt10_ick;
682
683static struct clk_hw_omap gpt10_ick_hw = {
684 .hw = {
685 .clk = &gpt10_ick,
686 },
687 .ops = &clkhwops_iclk_wait,
688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
689 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
690 .clkdm_name = "core_l4_clkdm",
691};
692
693DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
694
695DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
696 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
697 OMAP24XX_CLKSEL_GPT11_MASK,
698 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
699 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
700 gpt10_fck_parent_names, dss1_fck_ops);
701
702static struct clk gpt11_ick;
703
704static struct clk_hw_omap gpt11_ick_hw = {
705 .hw = {
706 .clk = &gpt11_ick,
707 },
708 .ops = &clkhwops_iclk_wait,
709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
710 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
711 .clkdm_name = "core_l4_clkdm",
712};
713
714DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
715
716DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
717 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
718 OMAP24XX_CLKSEL_GPT12_MASK,
719 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
720 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
721 gpt10_fck_parent_names, dss1_fck_ops);
722
723static struct clk gpt12_ick;
724
725static struct clk_hw_omap gpt12_ick_hw = {
726 .hw = {
727 .clk = &gpt12_ick,
728 },
729 .ops = &clkhwops_iclk_wait,
730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
731 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
732 .clkdm_name = "core_l4_clkdm",
733};
734
735DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
736
737static const struct clk_ops gpt1_fck_ops = {
738 .init = &omap2_init_clk_clkdm,
739 .enable = &omap2_dflt_clk_enable,
740 .disable = &omap2_dflt_clk_disable,
741 .is_enabled = &omap2_dflt_clk_is_enabled,
742 .recalc_rate = &omap2_clksel_recalc,
743 .set_rate = &omap2_clksel_set_rate,
744 .round_rate = &omap2_clksel_round_rate,
745 .get_parent = &omap2_clksel_find_parent_index,
746 .set_parent = &omap2_clksel_set_parent,
747};
748
749DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
750 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
751 OMAP24XX_CLKSEL_GPT1_MASK,
752 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
753 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
754 gpt10_fck_parent_names, gpt1_fck_ops);
755
756static struct clk gpt1_ick;
757
758static struct clk_hw_omap gpt1_ick_hw = {
759 .hw = {
760 .clk = &gpt1_ick,
761 },
762 .ops = &clkhwops_iclk_wait,
763 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
764 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
765 .clkdm_name = "wkup_clkdm",
766};
767
768DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
769
770DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
771 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
772 OMAP24XX_CLKSEL_GPT2_MASK,
773 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
774 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
775 gpt10_fck_parent_names, dss1_fck_ops);
776
777static struct clk gpt2_ick;
778
779static struct clk_hw_omap gpt2_ick_hw = {
780 .hw = {
781 .clk = &gpt2_ick,
782 },
783 .ops = &clkhwops_iclk_wait,
784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
785 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
786 .clkdm_name = "core_l4_clkdm",
787};
788
789DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
790
791DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
792 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
793 OMAP24XX_CLKSEL_GPT3_MASK,
794 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
796 gpt10_fck_parent_names, dss1_fck_ops);
797
798static struct clk gpt3_ick;
799
800static struct clk_hw_omap gpt3_ick_hw = {
801 .hw = {
802 .clk = &gpt3_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
811
812DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
813 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
814 OMAP24XX_CLKSEL_GPT4_MASK,
815 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
816 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
817 gpt10_fck_parent_names, dss1_fck_ops);
818
819static struct clk gpt4_ick;
820
821static struct clk_hw_omap gpt4_ick_hw = {
822 .hw = {
823 .clk = &gpt4_ick,
824 },
825 .ops = &clkhwops_iclk_wait,
826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
827 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
828 .clkdm_name = "core_l4_clkdm",
829};
830
831DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
832
833DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
834 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
835 OMAP24XX_CLKSEL_GPT5_MASK,
836 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
837 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
838 gpt10_fck_parent_names, dss1_fck_ops);
839
840static struct clk gpt5_ick;
841
842static struct clk_hw_omap gpt5_ick_hw = {
843 .hw = {
844 .clk = &gpt5_ick,
845 },
846 .ops = &clkhwops_iclk_wait,
847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
848 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
849 .clkdm_name = "core_l4_clkdm",
850};
851
852DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
853
854DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
855 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
856 OMAP24XX_CLKSEL_GPT6_MASK,
857 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
858 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
859 gpt10_fck_parent_names, dss1_fck_ops);
860
861static struct clk gpt6_ick;
862
863static struct clk_hw_omap gpt6_ick_hw = {
864 .hw = {
865 .clk = &gpt6_ick,
866 },
867 .ops = &clkhwops_iclk_wait,
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
870 .clkdm_name = "core_l4_clkdm",
871};
872
873DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
874
875DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
876 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
877 OMAP24XX_CLKSEL_GPT7_MASK,
878 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
879 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
880 gpt10_fck_parent_names, dss1_fck_ops);
881
882static struct clk gpt7_ick;
883
884static struct clk_hw_omap gpt7_ick_hw = {
885 .hw = {
886 .clk = &gpt7_ick,
887 },
888 .ops = &clkhwops_iclk_wait,
889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
890 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
891 .clkdm_name = "core_l4_clkdm",
892};
893
894DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
895
896DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
897 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
898 OMAP24XX_CLKSEL_GPT8_MASK,
899 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
900 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
901 gpt10_fck_parent_names, dss1_fck_ops);
902
903static struct clk gpt8_ick;
904
905static struct clk_hw_omap gpt8_ick_hw = {
906 .hw = {
907 .clk = &gpt8_ick,
908 },
909 .ops = &clkhwops_iclk_wait,
910 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
911 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
912 .clkdm_name = "core_l4_clkdm",
913};
914
915DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
916
917DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
918 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
919 OMAP24XX_CLKSEL_GPT9_MASK,
920 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
921 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
922 gpt10_fck_parent_names, dss1_fck_ops);
923
924static struct clk gpt9_ick;
925
926static struct clk_hw_omap gpt9_ick_hw = {
927 .hw = {
928 .clk = &gpt9_ick,
929 },
930 .ops = &clkhwops_iclk_wait,
931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
932 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
933 .clkdm_name = "core_l4_clkdm",
934};
935
936DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
937
938static struct clk hdq_fck;
939
940static struct clk_hw_omap hdq_fck_hw = {
941 .hw = {
942 .clk = &hdq_fck,
943 },
944 .ops = &clkhwops_wait,
945 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
946 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
947 .clkdm_name = "core_l4_clkdm",
948};
949
950DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
951
952static struct clk hdq_ick;
953
954static struct clk_hw_omap hdq_ick_hw = {
955 .hw = {
956 .clk = &hdq_ick,
957 },
958 .ops = &clkhwops_iclk_wait,
959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
960 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
961 .clkdm_name = "core_l4_clkdm",
962};
963
964DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
965
966static struct clk i2c1_fck;
967
968static struct clk_hw_omap i2c1_fck_hw = {
969 .hw = {
970 .clk = &i2c1_fck,
971 },
972 .ops = &clkhwops_wait,
973 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
974 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
975 .clkdm_name = "core_l4_clkdm",
976};
977
978DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
979
980static struct clk i2c1_ick;
981
982static struct clk_hw_omap i2c1_ick_hw = {
983 .hw = {
984 .clk = &i2c1_ick,
985 },
986 .ops = &clkhwops_iclk_wait,
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
988 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
989 .clkdm_name = "core_l4_clkdm",
990};
991
992DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
993
994static struct clk i2c2_fck;
995
996static struct clk_hw_omap i2c2_fck_hw = {
997 .hw = {
998 .clk = &i2c2_fck,
999 },
1000 .ops = &clkhwops_wait,
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1002 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1003 .clkdm_name = "core_l4_clkdm",
1004};
1005
1006DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
1007
1008static struct clk i2c2_ick;
1009
1010static struct clk_hw_omap i2c2_ick_hw = {
1011 .hw = {
1012 .clk = &i2c2_ick,
1013 },
1014 .ops = &clkhwops_iclk_wait,
1015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1016 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1017 .clkdm_name = "core_l4_clkdm",
1018};
1019
1020DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
1021
1022DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
1023 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1024 OMAP2420_CLKSEL_IVA_MASK,
1025 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1026 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
1027 dsp_fck_parent_names, dsp_fck_ops);
1028
1029static struct clk iva1_mpu_int_ifck;
1030
1031static const char *iva1_mpu_int_ifck_parent_names[] = {
1032 "iva1_ifck",
1033};
1034
1035static const struct clk_ops iva1_mpu_int_ifck_ops = {
1036 .init = &omap2_init_clk_clkdm,
1037 .enable = &omap2_dflt_clk_enable,
1038 .disable = &omap2_dflt_clk_disable,
1039 .is_enabled = &omap2_dflt_clk_is_enabled,
1040 .recalc_rate = &omap_fixed_divisor_recalc,
1041};
1042
1043static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
1044 .hw = {
1045 .clk = &iva1_mpu_int_ifck,
1046 },
1047 .ops = &clkhwops_wait,
1048 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1049 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1050 .clkdm_name = "iva1_clkdm",
1051 .fixed_div = 2,
1052};
1053
1054DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
1055 iva1_mpu_int_ifck_ops);
1056
1057static struct clk mailboxes_ick;
1058
1059static struct clk_hw_omap mailboxes_ick_hw = {
1060 .hw = {
1061 .clk = &mailboxes_ick,
1062 },
1063 .ops = &clkhwops_iclk_wait,
1064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1065 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1066 .clkdm_name = "core_l4_clkdm",
1067};
1068
1069DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1070
1071static const struct clksel_rate common_mcbsp_96m_rates[] = {
1072 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1073 { .div = 0 }
1074};
1075
1076static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1077 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1078 { .div = 0 }
1079};
1080
1081static const struct clksel mcbsp_fck_clksel[] = {
1082 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1083 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1084 { .parent = NULL },
1085};
1086
1087static const char *mcbsp1_fck_parent_names[] = {
1088 "func_96m_ck", "mcbsp_clks",
1089};
1090
1091DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1092 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1093 OMAP2_MCBSP1_CLKS_MASK,
1094 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1095 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1096 mcbsp1_fck_parent_names, dss1_fck_ops);
1097
1098static struct clk mcbsp1_ick;
1099
1100static struct clk_hw_omap mcbsp1_ick_hw = {
1101 .hw = {
1102 .clk = &mcbsp1_ick,
1103 },
1104 .ops = &clkhwops_iclk_wait,
1105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1106 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1107 .clkdm_name = "core_l4_clkdm",
1108};
1109
1110DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1111
1112DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1113 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1114 OMAP2_MCBSP2_CLKS_MASK,
1115 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1116 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1117 mcbsp1_fck_parent_names, dss1_fck_ops);
1118
1119static struct clk mcbsp2_ick;
1120
1121static struct clk_hw_omap mcbsp2_ick_hw = {
1122 .hw = {
1123 .clk = &mcbsp2_ick,
1124 },
1125 .ops = &clkhwops_iclk_wait,
1126 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1127 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1128 .clkdm_name = "core_l4_clkdm",
1129};
1130
1131DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1132
1133static struct clk mcspi1_fck;
1134
1135static const char *mcspi1_fck_parent_names[] = {
1136 "func_48m_ck",
1137};
1138
1139static struct clk_hw_omap mcspi1_fck_hw = {
1140 .hw = {
1141 .clk = &mcspi1_fck,
1142 },
1143 .ops = &clkhwops_wait,
1144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1145 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1146 .clkdm_name = "core_l4_clkdm",
1147};
1148
1149DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1150
1151static struct clk mcspi1_ick;
1152
1153static struct clk_hw_omap mcspi1_ick_hw = {
1154 .hw = {
1155 .clk = &mcspi1_ick,
1156 },
1157 .ops = &clkhwops_iclk_wait,
1158 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1159 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1160 .clkdm_name = "core_l4_clkdm",
1161};
1162
1163DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1164
1165static struct clk mcspi2_fck;
1166
1167static struct clk_hw_omap mcspi2_fck_hw = {
1168 .hw = {
1169 .clk = &mcspi2_fck,
1170 },
1171 .ops = &clkhwops_wait,
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1174 .clkdm_name = "core_l4_clkdm",
1175};
1176
1177DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1178
1179static struct clk mcspi2_ick;
1180
1181static struct clk_hw_omap mcspi2_ick_hw = {
1182 .hw = {
1183 .clk = &mcspi2_ick,
1184 },
1185 .ops = &clkhwops_iclk_wait,
1186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1187 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1188 .clkdm_name = "core_l4_clkdm",
1189};
1190
1191DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1192
1193static struct clk mmc_fck;
1194
1195static struct clk_hw_omap mmc_fck_hw = {
1196 .hw = {
1197 .clk = &mmc_fck,
1198 },
1199 .ops = &clkhwops_wait,
1200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1201 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1202 .clkdm_name = "core_l4_clkdm",
1203};
1204
1205DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
1206
1207static struct clk mmc_ick;
1208
1209static struct clk_hw_omap mmc_ick_hw = {
1210 .hw = {
1211 .clk = &mmc_ick,
1212 },
1213 .ops = &clkhwops_iclk_wait,
1214 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1215 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1216 .clkdm_name = "core_l4_clkdm",
1217};
1218
1219DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
1220
1221DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1222 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1223 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1224 CLK_DIVIDER_ONE_BASED, NULL);
1225
1226static struct clk mpu_wdt_fck;
1227
1228static struct clk_hw_omap mpu_wdt_fck_hw = {
1229 .hw = {
1230 .clk = &mpu_wdt_fck,
1231 },
1232 .ops = &clkhwops_wait,
1233 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1234 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1235 .clkdm_name = "wkup_clkdm",
1236};
1237
1238DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
1239
1240static struct clk mpu_wdt_ick;
1241
1242static struct clk_hw_omap mpu_wdt_ick_hw = {
1243 .hw = {
1244 .clk = &mpu_wdt_ick,
1245 },
1246 .ops = &clkhwops_iclk_wait,
1247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1248 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1249 .clkdm_name = "wkup_clkdm",
1250};
1251
1252DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1253
1254static struct clk mspro_fck;
1255
1256static struct clk_hw_omap mspro_fck_hw = {
1257 .hw = {
1258 .clk = &mspro_fck,
1259 },
1260 .ops = &clkhwops_wait,
1261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1262 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1263 .clkdm_name = "core_l4_clkdm",
1264};
1265
1266DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1267
1268static struct clk mspro_ick;
1269
1270static struct clk_hw_omap mspro_ick_hw = {
1271 .hw = {
1272 .clk = &mspro_ick,
1273 },
1274 .ops = &clkhwops_iclk_wait,
1275 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1276 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1277 .clkdm_name = "core_l4_clkdm",
1278};
1279
1280DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1281
1282static struct clk omapctrl_ick;
1283
1284static struct clk_hw_omap omapctrl_ick_hw = {
1285 .hw = {
1286 .clk = &omapctrl_ick,
1287 },
1288 .ops = &clkhwops_iclk_wait,
1289 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1290 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1291 .flags = ENABLE_ON_INIT,
1292 .clkdm_name = "wkup_clkdm",
1293};
1294
1295DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1296
1297static struct clk pka_ick;
1298
1299static struct clk_hw_omap pka_ick_hw = {
1300 .hw = {
1301 .clk = &pka_ick,
1302 },
1303 .ops = &clkhwops_iclk_wait,
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1305 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1306 .clkdm_name = "core_l4_clkdm",
1307};
1308
1309DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1310
1311static struct clk rng_ick;
1312
1313static struct clk_hw_omap rng_ick_hw = {
1314 .hw = {
1315 .clk = &rng_ick,
1316 },
1317 .ops = &clkhwops_iclk_wait,
1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1319 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1320 .clkdm_name = "core_l4_clkdm",
1321};
1322
1323DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1324
1325static struct clk sdma_fck;
1326
1327DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1328DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1329
1330static struct clk sdma_ick;
1331
1332static struct clk_hw_omap sdma_ick_hw = {
1333 .hw = {
1334 .clk = &sdma_ick,
1335 },
1336 .ops = &clkhwops_iclk,
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1338 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1339 .clkdm_name = "core_l3_clkdm",
1340};
1341
1342DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1343
1344static struct clk sdrc_ick;
1345
1346static struct clk_hw_omap sdrc_ick_hw = {
1347 .hw = {
1348 .clk = &sdrc_ick,
1349 },
1350 .ops = &clkhwops_iclk,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1353 .flags = ENABLE_ON_INIT,
1354 .clkdm_name = "core_l3_clkdm",
1355};
1356
1357DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1358
1359static struct clk sha_ick;
1360
1361static struct clk_hw_omap sha_ick_hw = {
1362 .hw = {
1363 .clk = &sha_ick,
1364 },
1365 .ops = &clkhwops_iclk_wait,
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1367 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1368 .clkdm_name = "core_l4_clkdm",
1369};
1370
1371DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1372
1373static struct clk ssi_l4_ick;
1374
1375static struct clk_hw_omap ssi_l4_ick_hw = {
1376 .hw = {
1377 .clk = &ssi_l4_ick,
1378 },
1379 .ops = &clkhwops_iclk_wait,
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1381 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1382 .clkdm_name = "core_l4_clkdm",
1383};
1384
1385DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1386
1387static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1388 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1389 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1390 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1391 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1392 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1393 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1394 { .div = 0 }
1395};
1396
1397static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1398 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1399 { .parent = NULL },
1400};
1401
1402static const char *ssi_ssr_sst_fck_parent_names[] = {
1403 "core_ck",
1404};
1405
1406DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1407 ssi_ssr_sst_fck_clksel,
1408 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1409 OMAP24XX_CLKSEL_SSI_MASK,
1410 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1411 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1412 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1413
1414static struct clk sync_32k_ick;
1415
1416static struct clk_hw_omap sync_32k_ick_hw = {
1417 .hw = {
1418 .clk = &sync_32k_ick,
1419 },
1420 .ops = &clkhwops_iclk_wait,
1421 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1422 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1423 .flags = ENABLE_ON_INIT,
1424 .clkdm_name = "wkup_clkdm",
1425};
1426
1427DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1428
1429static const struct clksel_rate common_clkout_src_core_rates[] = {
1430 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1431 { .div = 0 }
1432};
1433
1434static const struct clksel_rate common_clkout_src_sys_rates[] = {
1435 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1436 { .div = 0 }
1437};
1438
1439static const struct clksel_rate common_clkout_src_96m_rates[] = {
1440 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1441 { .div = 0 }
1442};
1443
1444static const struct clksel_rate common_clkout_src_54m_rates[] = {
1445 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1446 { .div = 0 }
1447};
1448
1449static const struct clksel common_clkout_src_clksel[] = {
1450 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1451 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1452 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1453 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1454 { .parent = NULL },
1455};
1456
1457static const char *sys_clkout_src_parent_names[] = {
1458 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1459};
1460
1461DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1462 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1463 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1464 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1465
1466DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1467 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1468 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1469
1470DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
1471 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
1472 OMAP2420_CLKOUT2_SOURCE_MASK,
1473 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
1474 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1475
1476DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
1477 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
1478 OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1479
1480static struct clk uart1_fck;
1481
1482static struct clk_hw_omap uart1_fck_hw = {
1483 .hw = {
1484 .clk = &uart1_fck,
1485 },
1486 .ops = &clkhwops_wait,
1487 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1488 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1489 .clkdm_name = "core_l4_clkdm",
1490};
1491
1492DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1493
1494static struct clk uart1_ick;
1495
1496static struct clk_hw_omap uart1_ick_hw = {
1497 .hw = {
1498 .clk = &uart1_ick,
1499 },
1500 .ops = &clkhwops_iclk_wait,
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1502 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1503 .clkdm_name = "core_l4_clkdm",
1504};
1505
1506DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1507
1508static struct clk uart2_fck;
1509
1510static struct clk_hw_omap uart2_fck_hw = {
1511 .hw = {
1512 .clk = &uart2_fck,
1513 },
1514 .ops = &clkhwops_wait,
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1517 .clkdm_name = "core_l4_clkdm",
1518};
1519
1520DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1521
1522static struct clk uart2_ick;
1523
1524static struct clk_hw_omap uart2_ick_hw = {
1525 .hw = {
1526 .clk = &uart2_ick,
1527 },
1528 .ops = &clkhwops_iclk_wait,
1529 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1530 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1531 .clkdm_name = "core_l4_clkdm",
1532};
1533
1534DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1535
1536static struct clk uart3_fck;
1537
1538static struct clk_hw_omap uart3_fck_hw = {
1539 .hw = {
1540 .clk = &uart3_fck,
1541 },
1542 .ops = &clkhwops_wait,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1544 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1545 .clkdm_name = "core_l4_clkdm",
1546};
1547
1548DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1549
1550static struct clk uart3_ick;
1551
1552static struct clk_hw_omap uart3_ick_hw = {
1553 .hw = {
1554 .clk = &uart3_ick,
1555 },
1556 .ops = &clkhwops_iclk_wait,
1557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1558 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1559 .clkdm_name = "core_l4_clkdm",
1560};
1561
1562DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1563
1564static struct clk usb_fck;
1565
1566static struct clk_hw_omap usb_fck_hw = {
1567 .hw = {
1568 .clk = &usb_fck,
1569 },
1570 .ops = &clkhwops_wait,
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1572 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1573 .clkdm_name = "core_l3_clkdm",
1574};
1575
1576DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1577
1578static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1579 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1580 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1581 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1582 { .div = 0 }
1583};
1584
1585static const struct clksel usb_l4_ick_clksel[] = {
1586 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1587 { .parent = NULL },
1588};
1589
1590static const char *usb_l4_ick_parent_names[] = {
1591 "core_l3_ck",
1592};
1593
1594DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1595 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1596 OMAP24XX_CLKSEL_USB_MASK,
1597 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1598 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1599 usb_l4_ick_parent_names, dsp_fck_ops);
1600
1601static struct clk virt_prcm_set;
1602
1603static const char *virt_prcm_set_parent_names[] = {
1604 "mpu_ck",
1605};
1606
1607static const struct clk_ops virt_prcm_set_ops = {
1608 .recalc_rate = &omap2_table_mpu_recalc,
1609 .set_rate = &omap2_select_table_rate,
1610 .round_rate = &omap2_round_to_table_rate,
1611};
1612
1613DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1614DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1615
1616static const struct clksel_rate vlynq_fck_96m_rates[] = {
1617 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1618 { .div = 0 }
1619};
1620
1621static const struct clksel_rate vlynq_fck_core_rates[] = {
1622 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1623 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1624 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1625 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1626 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1627 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1628 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1629 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1630 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1631 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1632 { .div = 0 }
1633};
1634
1635static const struct clksel vlynq_fck_clksel[] = {
1636 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1637 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1638 { .parent = NULL },
1639};
1640
1641static const char *vlynq_fck_parent_names[] = {
1642 "func_96m_ck", "core_ck",
1643};
1644
1645DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
1646 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1647 OMAP2420_CLKSEL_VLYNQ_MASK,
1648 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
1650 vlynq_fck_parent_names, dss1_fck_ops);
1651
1652static struct clk vlynq_ick;
1653
1654static struct clk_hw_omap vlynq_ick_hw = {
1655 .hw = {
1656 .clk = &vlynq_ick,
1657 },
1658 .ops = &clkhwops_iclk_wait,
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1661 .clkdm_name = "core_l3_clkdm",
1662};
1663
1664DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
1665
1666static struct clk wdt1_ick;
1667
1668static struct clk_hw_omap wdt1_ick_hw = {
1669 .hw = {
1670 .clk = &wdt1_ick,
1671 },
1672 .ops = &clkhwops_iclk_wait,
1673 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1674 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1675 .clkdm_name = "wkup_clkdm",
1676};
1677
1678DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1679
1680static struct clk wdt3_fck;
1681
1682static struct clk_hw_omap wdt3_fck_hw = {
1683 .hw = {
1684 .clk = &wdt3_fck,
1685 },
1686 .ops = &clkhwops_wait,
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1689 .clkdm_name = "core_l4_clkdm",
1690};
1691
1692DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
1693
1694static struct clk wdt3_ick;
1695
1696static struct clk_hw_omap wdt3_ick_hw = {
1697 .hw = {
1698 .clk = &wdt3_ick,
1699 },
1700 .ops = &clkhwops_iclk_wait,
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1703 .clkdm_name = "core_l4_clkdm",
1704};
1705
1706DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
1707
1708static struct clk wdt4_fck;
1709
1710static struct clk_hw_omap wdt4_fck_hw = {
1711 .hw = {
1712 .clk = &wdt4_fck,
1713 },
1714 .ops = &clkhwops_wait,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1716 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1717 .clkdm_name = "core_l4_clkdm",
1718};
1719
1720DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
1721
1722static struct clk wdt4_ick;
1723
1724static struct clk_hw_omap wdt4_ick_hw = {
1725 .hw = {
1726 .clk = &wdt4_ick,
1727 },
1728 .ops = &clkhwops_iclk_wait,
1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1730 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1731 .clkdm_name = "core_l4_clkdm",
1732};
1733
1734DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1735
1736/*
1737 * clkdev integration
1738 */
1739
1740static struct omap_clk omap2420_clks[] = {
1741 /* external root sources */
1742 CLK(NULL, "func_32k_ck", &func_32k_ck),
1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1744 CLK(NULL, "osc_ck", &osc_ck),
1745 CLK(NULL, "sys_ck", &sys_ck),
1746 CLK(NULL, "alt_ck", &alt_ck),
1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1748 /* internal analog sources */
1749 CLK(NULL, "dpll_ck", &dpll_ck),
1750 CLK(NULL, "apll96_ck", &apll96_ck),
1751 CLK(NULL, "apll54_ck", &apll54_ck),
1752 /* internal prcm root sources */
1753 CLK(NULL, "func_54m_ck", &func_54m_ck),
1754 CLK(NULL, "core_ck", &core_ck),
1755 CLK(NULL, "func_96m_ck", &func_96m_ck),
1756 CLK(NULL, "func_48m_ck", &func_48m_ck),
1757 CLK(NULL, "func_12m_ck", &func_12m_ck),
1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1759 CLK(NULL, "sys_clkout", &sys_clkout),
1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
1761 CLK(NULL, "sys_clkout2", &sys_clkout2),
1762 CLK(NULL, "emul_ck", &emul_ck),
1763 /* mpu domain clocks */
1764 CLK(NULL, "mpu_ck", &mpu_ck),
1765 /* dsp domain clocks */
1766 CLK(NULL, "dsp_fck", &dsp_fck),
1767 CLK(NULL, "dsp_ick", &dsp_ick),
1768 CLK(NULL, "iva1_ifck", &iva1_ifck),
1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
1770 /* GFX domain clocks */
1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1773 CLK(NULL, "gfx_ick", &gfx_ick),
1774 /* DSS domain clocks */
1775 CLK("omapdss_dss", "ick", &dss_ick),
1776 CLK(NULL, "dss_ick", &dss_ick),
1777 CLK(NULL, "dss1_fck", &dss1_fck),
1778 CLK(NULL, "dss2_fck", &dss2_fck),
1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1780 /* L3 domain clocks */
1781 CLK(NULL, "core_l3_ck", &core_l3_ck),
1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1784 /* L4 domain clocks */
1785 CLK(NULL, "l4_ck", &l4_ck),
1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1787 /* virtual meta-group clock */
1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1789 /* general l4 interface ck, multi-parent functional clk */
1790 CLK(NULL, "gpt1_ick", &gpt1_ick),
1791 CLK(NULL, "gpt1_fck", &gpt1_fck),
1792 CLK(NULL, "gpt2_ick", &gpt2_ick),
1793 CLK(NULL, "gpt2_fck", &gpt2_fck),
1794 CLK(NULL, "gpt3_ick", &gpt3_ick),
1795 CLK(NULL, "gpt3_fck", &gpt3_fck),
1796 CLK(NULL, "gpt4_ick", &gpt4_ick),
1797 CLK(NULL, "gpt4_fck", &gpt4_fck),
1798 CLK(NULL, "gpt5_ick", &gpt5_ick),
1799 CLK(NULL, "gpt5_fck", &gpt5_fck),
1800 CLK(NULL, "gpt6_ick", &gpt6_ick),
1801 CLK(NULL, "gpt6_fck", &gpt6_fck),
1802 CLK(NULL, "gpt7_ick", &gpt7_ick),
1803 CLK(NULL, "gpt7_fck", &gpt7_fck),
1804 CLK(NULL, "gpt8_ick", &gpt8_ick),
1805 CLK(NULL, "gpt8_fck", &gpt8_fck),
1806 CLK(NULL, "gpt9_ick", &gpt9_ick),
1807 CLK(NULL, "gpt9_fck", &gpt9_fck),
1808 CLK(NULL, "gpt10_ick", &gpt10_ick),
1809 CLK(NULL, "gpt10_fck", &gpt10_fck),
1810 CLK(NULL, "gpt11_ick", &gpt11_ick),
1811 CLK(NULL, "gpt11_fck", &gpt11_fck),
1812 CLK(NULL, "gpt12_ick", &gpt12_ick),
1813 CLK(NULL, "gpt12_fck", &gpt12_fck),
1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1826 CLK(NULL, "uart1_ick", &uart1_ick),
1827 CLK(NULL, "uart1_fck", &uart1_fck),
1828 CLK(NULL, "uart2_ick", &uart2_ick),
1829 CLK(NULL, "uart2_fck", &uart2_fck),
1830 CLK(NULL, "uart3_ick", &uart3_ick),
1831 CLK(NULL, "uart3_fck", &uart3_fck),
1832 CLK(NULL, "gpios_ick", &gpios_ick),
1833 CLK(NULL, "gpios_fck", &gpios_fck),
1834 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1838 CLK(NULL, "wdt1_ick", &wdt1_ick),
1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1840 CLK("omap24xxcam", "fck", &cam_fck),
1841 CLK(NULL, "cam_fck", &cam_fck),
1842 CLK("omap24xxcam", "ick", &cam_ick),
1843 CLK(NULL, "cam_ick", &cam_ick),
1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1845 CLK(NULL, "wdt4_ick", &wdt4_ick),
1846 CLK(NULL, "wdt4_fck", &wdt4_fck),
1847 CLK(NULL, "wdt3_ick", &wdt3_ick),
1848 CLK(NULL, "wdt3_fck", &wdt3_fck),
1849 CLK(NULL, "mspro_ick", &mspro_ick),
1850 CLK(NULL, "mspro_fck", &mspro_fck),
1851 CLK("mmci-omap.0", "ick", &mmc_ick),
1852 CLK(NULL, "mmc_ick", &mmc_ick),
1853 CLK("mmci-omap.0", "fck", &mmc_fck),
1854 CLK(NULL, "mmc_fck", &mmc_fck),
1855 CLK(NULL, "fac_ick", &fac_ick),
1856 CLK(NULL, "fac_fck", &fac_fck),
1857 CLK(NULL, "eac_ick", &eac_ick),
1858 CLK(NULL, "eac_fck", &eac_fck),
1859 CLK("omap_hdq.0", "ick", &hdq_ick),
1860 CLK(NULL, "hdq_ick", &hdq_ick),
1861 CLK("omap_hdq.0", "fck", &hdq_fck),
1862 CLK(NULL, "hdq_fck", &hdq_fck),
1863 CLK("omap_i2c.1", "ick", &i2c1_ick),
1864 CLK(NULL, "i2c1_ick", &i2c1_ick),
1865 CLK(NULL, "i2c1_fck", &i2c1_fck),
1866 CLK("omap_i2c.2", "ick", &i2c2_ick),
1867 CLK(NULL, "i2c2_ick", &i2c2_ick),
1868 CLK(NULL, "i2c2_fck", &i2c2_fck),
1869 CLK(NULL, "gpmc_fck", &gpmc_fck),
1870 CLK(NULL, "sdma_fck", &sdma_fck),
1871 CLK(NULL, "sdma_ick", &sdma_ick),
1872 CLK(NULL, "sdrc_ick", &sdrc_ick),
1873 CLK(NULL, "vlynq_ick", &vlynq_ick),
1874 CLK(NULL, "vlynq_fck", &vlynq_fck),
1875 CLK(NULL, "des_ick", &des_ick),
1876 CLK("omap-sham", "ick", &sha_ick),
1877 CLK(NULL, "sha_ick", &sha_ick),
1878 CLK("omap_rng", "ick", &rng_ick),
1879 CLK(NULL, "rng_ick", &rng_ick),
1880 CLK("omap-aes", "ick", &aes_ick),
1881 CLK(NULL, "aes_ick", &aes_ick),
1882 CLK(NULL, "pka_ick", &pka_ick),
1883 CLK(NULL, "usb_fck", &usb_fck),
1884 CLK("musb-hdrc", "fck", &osc_ck),
1885 CLK(NULL, "timer_32k_ck", &func_32k_ck),
1886 CLK(NULL, "timer_sys_ck", &sys_ck),
1887 CLK(NULL, "timer_ext_ck", &alt_ck),
1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
1889};
1890
1891
1892static const char *enable_init_clks[] = {
1893 "apll96_ck",
1894 "apll54_ck",
1895 "sync_32k_ick",
1896 "omapctrl_ick",
1897 "gpmc_fck",
1898 "sdrc_ick",
1899};
1900
1901/*
1902 * init code
1903 */
1904
1905int __init omap2420_clk_init(void)
1906{
1907 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1908 cpu_mask = RATE_IN_242X;
1909 rate_table = omap2420_rate_table;
1910
1911 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
1912
1913 omap2xxx_clkt_vps_check_bootloader_rates();
1914
1915 omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
1916
1917 omap2xxx_clkt_vps_late_init();
1918
1919 omap2_clk_disable_autoidle_all();
1920
1921 omap2_clk_enable_init_clocks(enable_init_clks,
1922 ARRAY_SIZE(enable_init_clks));
1923
1924 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1925 (clk_get_rate(&sys_ck) / 1000000),
1926 (clk_get_rate(&sys_ck) / 100000) % 10,
1927 (clk_get_rate(&dpll_ck) / 1000000),
1928 (clk_get_rate(&mpu_ck) / 1000000));
1929
1930 return 0;
1931}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 19:41:09 -0500