diff options
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r-- | arch/arm/include/asm/cacheflush.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/pgtable-3level.h | 15 | ||||
-rw-r--r-- | arch/arm/include/asm/spinlock.h | 15 |
3 files changed, 13 insertions, 18 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index e9a49fe0284e..8b8b61685a34 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h | |||
@@ -212,6 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, | |||
212 | static inline void __flush_icache_all(void) | 212 | static inline void __flush_icache_all(void) |
213 | { | 213 | { |
214 | __flush_icache_preferred(); | 214 | __flush_icache_preferred(); |
215 | dsb(); | ||
215 | } | 216 | } |
216 | 217 | ||
217 | /* | 218 | /* |
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h index 03243f7eeddf..85c60adc8b60 100644 --- a/arch/arm/include/asm/pgtable-3level.h +++ b/arch/arm/include/asm/pgtable-3level.h | |||
@@ -120,13 +120,16 @@ | |||
120 | /* | 120 | /* |
121 | * 2nd stage PTE definitions for LPAE. | 121 | * 2nd stage PTE definitions for LPAE. |
122 | */ | 122 | */ |
123 | #define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */ | 123 | #define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */ |
124 | #define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */ | 124 | #define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */ |
125 | #define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */ | 125 | #define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */ |
126 | #define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ | 126 | #define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */ |
127 | #define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ | 127 | #define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2) |
128 | 128 | ||
129 | #define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ | 129 | #define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */ |
130 | #define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */ | ||
131 | |||
132 | #define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */ | ||
130 | 133 | ||
131 | /* | 134 | /* |
132 | * Hyp-mode PL2 PTE definitions for LPAE. | 135 | * Hyp-mode PL2 PTE definitions for LPAE. |
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h index ef3c6072aa45..ac4bfae26702 100644 --- a/arch/arm/include/asm/spinlock.h +++ b/arch/arm/include/asm/spinlock.h | |||
@@ -37,18 +37,9 @@ | |||
37 | 37 | ||
38 | static inline void dsb_sev(void) | 38 | static inline void dsb_sev(void) |
39 | { | 39 | { |
40 | #if __LINUX_ARM_ARCH__ >= 7 | 40 | |
41 | __asm__ __volatile__ ( | 41 | dsb(ishst); |
42 | "dsb ishst\n" | 42 | __asm__(SEV); |
43 | SEV | ||
44 | ); | ||
45 | #else | ||
46 | __asm__ __volatile__ ( | ||
47 | "mcr p15, 0, %0, c7, c10, 4\n" | ||
48 | SEV | ||
49 | : : "r" (0) | ||
50 | ); | ||
51 | #endif | ||
52 | } | 43 | } |
53 | 44 | ||
54 | /* | 45 | /* |