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Diffstat (limited to 'arch/arm/include/asm/hardware/cache-l2x0.h')
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h62
1 files changed, 59 insertions, 3 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 16bd48031583..7df239bcdf27 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -20,6 +20,8 @@
20#ifndef __ASM_ARM_HARDWARE_L2X0_H 20#ifndef __ASM_ARM_HARDWARE_L2X0_H
21#define __ASM_ARM_HARDWARE_L2X0_H 21#define __ASM_ARM_HARDWARE_L2X0_H
22 22
23#include <linux/errno.h>
24
23#define L2X0_CACHE_ID 0x000 25#define L2X0_CACHE_ID 0x000
24#define L2X0_CACHE_TYPE 0x004 26#define L2X0_CACHE_TYPE 0x004
25#define L2X0_CTRL 0x100 27#define L2X0_CTRL 0x100
@@ -45,8 +47,15 @@
45#define L2X0_CLEAN_INV_LINE_PA 0x7F0 47#define L2X0_CLEAN_INV_LINE_PA 0x7F0
46#define L2X0_CLEAN_INV_LINE_IDX 0x7F8 48#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
47#define L2X0_CLEAN_INV_WAY 0x7FC 49#define L2X0_CLEAN_INV_WAY 0x7FC
48#define L2X0_LOCKDOWN_WAY_D 0x900 50/*
49#define L2X0_LOCKDOWN_WAY_I 0x904 51 * The lockdown registers repeat 8 times for L310, the L210 has only one
52 * D and one I lockdown register at 0x0900 and 0x0904.
53 */
54#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
55#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
56#define L2X0_LOCKDOWN_STRIDE 0x08
57#define L2X0_ADDR_FILTER_START 0xC00
58#define L2X0_ADDR_FILTER_END 0xC04
50#define L2X0_TEST_OPERATION 0xF00 59#define L2X0_TEST_OPERATION 0xF00
51#define L2X0_LINE_DATA 0xF10 60#define L2X0_LINE_DATA 0xF10
52#define L2X0_LINE_TAG 0xF30 61#define L2X0_LINE_TAG 0xF30
@@ -60,11 +69,26 @@
60#define L2X0_CACHE_ID_PART_MASK (0xf << 6) 69#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
61#define L2X0_CACHE_ID_PART_L210 (1 << 6) 70#define L2X0_CACHE_ID_PART_L210 (1 << 6)
62#define L2X0_CACHE_ID_PART_L310 (3 << 6) 71#define L2X0_CACHE_ID_PART_L310 (3 << 6)
72#define L2X0_CACHE_ID_RTL_MASK 0x3f
73#define L2X0_CACHE_ID_RTL_R0P0 0x0
74#define L2X0_CACHE_ID_RTL_R1P0 0x2
75#define L2X0_CACHE_ID_RTL_R2P0 0x4
76#define L2X0_CACHE_ID_RTL_R3P0 0x5
77#define L2X0_CACHE_ID_RTL_R3P1 0x6
78#define L2X0_CACHE_ID_RTL_R3P2 0x8
63 79
64#define L2X0_AUX_CTRL_MASK 0xc0000fff 80#define L2X0_AUX_CTRL_MASK 0xc0000fff
81#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
82#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
83#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
84#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
85#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
86#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
87#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
88#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
65#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 89#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
66#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 90#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
67#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) 91#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
68#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 92#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
69#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 93#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
70#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 94#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
@@ -72,8 +96,40 @@
72#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 96#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
73#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 97#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
74 98
99#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
100#define L2X0_LATENCY_CTRL_RD_SHIFT 4
101#define L2X0_LATENCY_CTRL_WR_SHIFT 8
102
103#define L2X0_ADDR_FILTER_EN 1
104
75#ifndef __ASSEMBLY__ 105#ifndef __ASSEMBLY__
76extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); 106extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
107#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
108extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask);
109#else
110static inline int l2x0_of_init(__u32 aux_val, __u32 aux_mask)
111{
112 return -ENODEV;
113}
77#endif 114#endif
78 115
116struct l2x0_regs {
117 unsigned long phy_base;
118 unsigned long aux_ctrl;
119 /*
120 * Whether the following registers need to be saved/restored
121 * depends on platform
122 */
123 unsigned long tag_latency;
124 unsigned long data_latency;
125 unsigned long filter_start;
126 unsigned long filter_end;
127 unsigned long prefetch_ctrl;
128 unsigned long pwr_ctrl;
129};
130
131extern struct l2x0_regs l2x0_saved_regs;
132
133#endif /* __ASSEMBLY__ */
134
79#endif 135#endif