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-rw-r--r--arch/arm/include/asm/assembler.h69
1 files changed, 60 insertions, 9 deletions
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 4abe57279c66..7bbf325a4f31 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -108,33 +108,37 @@
108 .endm 108 .endm
109#endif 109#endif
110 110
111 .macro asm_trace_hardirqs_off 111 .macro asm_trace_hardirqs_off, save=1
112#if defined(CONFIG_TRACE_IRQFLAGS) 112#if defined(CONFIG_TRACE_IRQFLAGS)
113 .if \save
113 stmdb sp!, {r0-r3, ip, lr} 114 stmdb sp!, {r0-r3, ip, lr}
115 .endif
114 bl trace_hardirqs_off 116 bl trace_hardirqs_off
117 .if \save
115 ldmia sp!, {r0-r3, ip, lr} 118 ldmia sp!, {r0-r3, ip, lr}
119 .endif
116#endif 120#endif
117 .endm 121 .endm
118 122
119 .macro asm_trace_hardirqs_on_cond, cond 123 .macro asm_trace_hardirqs_on, cond=al, save=1
120#if defined(CONFIG_TRACE_IRQFLAGS) 124#if defined(CONFIG_TRACE_IRQFLAGS)
121 /* 125 /*
122 * actually the registers should be pushed and pop'd conditionally, but 126 * actually the registers should be pushed and pop'd conditionally, but
123 * after bl the flags are certainly clobbered 127 * after bl the flags are certainly clobbered
124 */ 128 */
129 .if \save
125 stmdb sp!, {r0-r3, ip, lr} 130 stmdb sp!, {r0-r3, ip, lr}
131 .endif
126 bl\cond trace_hardirqs_on 132 bl\cond trace_hardirqs_on
133 .if \save
127 ldmia sp!, {r0-r3, ip, lr} 134 ldmia sp!, {r0-r3, ip, lr}
135 .endif
128#endif 136#endif
129 .endm 137 .endm
130 138
131 .macro asm_trace_hardirqs_on 139 .macro disable_irq, save=1
132 asm_trace_hardirqs_on_cond al
133 .endm
134
135 .macro disable_irq
136 disable_irq_notrace 140 disable_irq_notrace
137 asm_trace_hardirqs_off 141 asm_trace_hardirqs_off \save
138 .endm 142 .endm
139 143
140 .macro enable_irq 144 .macro enable_irq
@@ -173,7 +177,7 @@
173 177
174 .macro restore_irqs, oldcpsr 178 .macro restore_irqs, oldcpsr
175 tst \oldcpsr, #PSR_I_BIT 179 tst \oldcpsr, #PSR_I_BIT
176 asm_trace_hardirqs_on_cond eq 180 asm_trace_hardirqs_on cond=eq
177 restore_irqs_notrace \oldcpsr 181 restore_irqs_notrace \oldcpsr
178 .endm 182 .endm
179 183
@@ -445,6 +449,53 @@ THUMB( orr \reg , \reg , #PSR_T_BIT )
445#endif 449#endif
446 .endm 450 .endm
447 451
452 .macro uaccess_disable, tmp, isb=1
453#ifdef CONFIG_CPU_SW_DOMAIN_PAN
454 /*
455 * Whenever we re-enter userspace, the domains should always be
456 * set appropriately.
457 */
458 mov \tmp, #DACR_UACCESS_DISABLE
459 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
460 .if \isb
461 instr_sync
462 .endif
463#endif
464 .endm
465
466 .macro uaccess_enable, tmp, isb=1
467#ifdef CONFIG_CPU_SW_DOMAIN_PAN
468 /*
469 * Whenever we re-enter userspace, the domains should always be
470 * set appropriately.
471 */
472 mov \tmp, #DACR_UACCESS_ENABLE
473 mcr p15, 0, \tmp, c3, c0, 0
474 .if \isb
475 instr_sync
476 .endif
477#endif
478 .endm
479
480 .macro uaccess_save, tmp
481#ifdef CONFIG_CPU_SW_DOMAIN_PAN
482 mrc p15, 0, \tmp, c3, c0, 0
483 str \tmp, [sp, #S_FRAME_SIZE]
484#endif
485 .endm
486
487 .macro uaccess_restore
488#ifdef CONFIG_CPU_SW_DOMAIN_PAN
489 ldr r0, [sp, #S_FRAME_SIZE]
490 mcr p15, 0, r0, c3, c0, 0
491#endif
492 .endm
493
494 .macro uaccess_save_and_disable, tmp
495 uaccess_save \tmp
496 uaccess_disable \tmp
497 .endm
498
448 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo 499 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
449 .macro ret\c, reg 500 .macro ret\c, reg
450#if __LINUX_ARM_ARCH__ < 6 501#if __LINUX_ARM_ARCH__ < 6