diff options
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r-- | arch/arm/boot/dts/tegra30.dtsi | 72 |
1 files changed, 42 insertions, 30 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 31259b09e7cc..ed8e7700b46d 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
@@ -1,5 +1,6 @@ | |||
1 | #include <dt-bindings/clock/tegra30-car.h> | 1 | #include <dt-bindings/clock/tegra30-car.h> |
2 | #include <dt-bindings/gpio/tegra-gpio.h> | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
3 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> | ||
3 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
4 | 5 | ||
5 | #include "skeleton.dtsi" | 6 | #include "skeleton.dtsi" |
@@ -16,7 +17,7 @@ | |||
16 | serial4 = &uarte; | 17 | serial4 = &uarte; |
17 | }; | 18 | }; |
18 | 19 | ||
19 | pcie-controller { | 20 | pcie-controller@00003000 { |
20 | compatible = "nvidia,tegra30-pcie"; | 21 | compatible = "nvidia,tegra30-pcie"; |
21 | device_type = "pci"; | 22 | device_type = "pci"; |
22 | reg = <0x00003000 0x00000800 /* PADS registers */ | 23 | reg = <0x00003000 0x00000800 /* PADS registers */ |
@@ -89,7 +90,7 @@ | |||
89 | }; | 90 | }; |
90 | }; | 91 | }; |
91 | 92 | ||
92 | host1x { | 93 | host1x@50000000 { |
93 | compatible = "nvidia,tegra30-host1x", "simple-bus"; | 94 | compatible = "nvidia,tegra30-host1x", "simple-bus"; |
94 | reg = <0x50000000 0x00024000>; | 95 | reg = <0x50000000 0x00024000>; |
95 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ | 96 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
@@ -103,7 +104,7 @@ | |||
103 | 104 | ||
104 | ranges = <0x54000000 0x54000000 0x04000000>; | 105 | ranges = <0x54000000 0x54000000 0x04000000>; |
105 | 106 | ||
106 | mpe { | 107 | mpe@54040000 { |
107 | compatible = "nvidia,tegra30-mpe"; | 108 | compatible = "nvidia,tegra30-mpe"; |
108 | reg = <0x54040000 0x00040000>; | 109 | reg = <0x54040000 0x00040000>; |
109 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; | 110 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
@@ -112,7 +113,7 @@ | |||
112 | reset-names = "mpe"; | 113 | reset-names = "mpe"; |
113 | }; | 114 | }; |
114 | 115 | ||
115 | vi { | 116 | vi@54080000 { |
116 | compatible = "nvidia,tegra30-vi"; | 117 | compatible = "nvidia,tegra30-vi"; |
117 | reg = <0x54080000 0x00040000>; | 118 | reg = <0x54080000 0x00040000>; |
118 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | 119 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
@@ -121,7 +122,7 @@ | |||
121 | reset-names = "vi"; | 122 | reset-names = "vi"; |
122 | }; | 123 | }; |
123 | 124 | ||
124 | epp { | 125 | epp@540c0000 { |
125 | compatible = "nvidia,tegra30-epp"; | 126 | compatible = "nvidia,tegra30-epp"; |
126 | reg = <0x540c0000 0x00040000>; | 127 | reg = <0x540c0000 0x00040000>; |
127 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; | 128 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
@@ -130,7 +131,7 @@ | |||
130 | reset-names = "epp"; | 131 | reset-names = "epp"; |
131 | }; | 132 | }; |
132 | 133 | ||
133 | isp { | 134 | isp@54100000 { |
134 | compatible = "nvidia,tegra30-isp"; | 135 | compatible = "nvidia,tegra30-isp"; |
135 | reg = <0x54100000 0x00040000>; | 136 | reg = <0x54100000 0x00040000>; |
136 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | 137 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
@@ -139,7 +140,7 @@ | |||
139 | reset-names = "isp"; | 140 | reset-names = "isp"; |
140 | }; | 141 | }; |
141 | 142 | ||
142 | gr2d { | 143 | gr2d@54140000 { |
143 | compatible = "nvidia,tegra30-gr2d"; | 144 | compatible = "nvidia,tegra30-gr2d"; |
144 | reg = <0x54140000 0x00040000>; | 145 | reg = <0x54140000 0x00040000>; |
145 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; | 146 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
@@ -148,7 +149,7 @@ | |||
148 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; | 149 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
149 | }; | 150 | }; |
150 | 151 | ||
151 | gr3d { | 152 | gr3d@54180000 { |
152 | compatible = "nvidia,tegra30-gr3d"; | 153 | compatible = "nvidia,tegra30-gr3d"; |
153 | reg = <0x54180000 0x00040000>; | 154 | reg = <0x54180000 0x00040000>; |
154 | clocks = <&tegra_car TEGRA30_CLK_GR3D | 155 | clocks = <&tegra_car TEGRA30_CLK_GR3D |
@@ -189,7 +190,7 @@ | |||
189 | }; | 190 | }; |
190 | }; | 191 | }; |
191 | 192 | ||
192 | hdmi { | 193 | hdmi@54280000 { |
193 | compatible = "nvidia,tegra30-hdmi"; | 194 | compatible = "nvidia,tegra30-hdmi"; |
194 | reg = <0x54280000 0x00040000>; | 195 | reg = <0x54280000 0x00040000>; |
195 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | 196 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
@@ -201,7 +202,7 @@ | |||
201 | status = "disabled"; | 202 | status = "disabled"; |
202 | }; | 203 | }; |
203 | 204 | ||
204 | tvo { | 205 | tvo@542c0000 { |
205 | compatible = "nvidia,tegra30-tvo"; | 206 | compatible = "nvidia,tegra30-tvo"; |
206 | reg = <0x542c0000 0x00040000>; | 207 | reg = <0x542c0000 0x00040000>; |
207 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; | 208 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
@@ -209,7 +210,7 @@ | |||
209 | status = "disabled"; | 210 | status = "disabled"; |
210 | }; | 211 | }; |
211 | 212 | ||
212 | dsi { | 213 | dsi@54300000 { |
213 | compatible = "nvidia,tegra30-dsi"; | 214 | compatible = "nvidia,tegra30-dsi"; |
214 | reg = <0x54300000 0x00040000>; | 215 | reg = <0x54300000 0x00040000>; |
215 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; | 216 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
@@ -227,7 +228,7 @@ | |||
227 | clocks = <&tegra_car TEGRA30_CLK_TWD>; | 228 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
228 | }; | 229 | }; |
229 | 230 | ||
230 | intc: interrupt-controller { | 231 | intc: interrupt-controller@50041000 { |
231 | compatible = "arm,cortex-a9-gic"; | 232 | compatible = "arm,cortex-a9-gic"; |
232 | reg = <0x50041000 0x1000 | 233 | reg = <0x50041000 0x1000 |
233 | 0x50040100 0x0100>; | 234 | 0x50040100 0x0100>; |
@@ -235,7 +236,7 @@ | |||
235 | #interrupt-cells = <3>; | 236 | #interrupt-cells = <3>; |
236 | }; | 237 | }; |
237 | 238 | ||
238 | cache-controller { | 239 | cache-controller@50043000 { |
239 | compatible = "arm,pl310-cache"; | 240 | compatible = "arm,pl310-cache"; |
240 | reg = <0x50043000 0x1000>; | 241 | reg = <0x50043000 0x1000>; |
241 | arm,data-latency = <6 6 2>; | 242 | arm,data-latency = <6 6 2>; |
@@ -256,14 +257,14 @@ | |||
256 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; | 257 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
257 | }; | 258 | }; |
258 | 259 | ||
259 | tegra_car: clock { | 260 | tegra_car: clock@60006000 { |
260 | compatible = "nvidia,tegra30-car"; | 261 | compatible = "nvidia,tegra30-car"; |
261 | reg = <0x60006000 0x1000>; | 262 | reg = <0x60006000 0x1000>; |
262 | #clock-cells = <1>; | 263 | #clock-cells = <1>; |
263 | #reset-cells = <1>; | 264 | #reset-cells = <1>; |
264 | }; | 265 | }; |
265 | 266 | ||
266 | apbdma: dma { | 267 | apbdma: dma@6000a000 { |
267 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; | 268 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
268 | reg = <0x6000a000 0x1400>; | 269 | reg = <0x6000a000 0x1400>; |
269 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | 270 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
@@ -304,12 +305,12 @@ | |||
304 | #dma-cells = <1>; | 305 | #dma-cells = <1>; |
305 | }; | 306 | }; |
306 | 307 | ||
307 | ahb: ahb { | 308 | ahb: ahb@6000c004 { |
308 | compatible = "nvidia,tegra30-ahb"; | 309 | compatible = "nvidia,tegra30-ahb"; |
309 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ | 310 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ |
310 | }; | 311 | }; |
311 | 312 | ||
312 | gpio: gpio { | 313 | gpio: gpio@6000d000 { |
313 | compatible = "nvidia,tegra30-gpio"; | 314 | compatible = "nvidia,tegra30-gpio"; |
314 | reg = <0x6000d000 0x1000>; | 315 | reg = <0x6000d000 0x1000>; |
315 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, | 316 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
@@ -326,7 +327,7 @@ | |||
326 | interrupt-controller; | 327 | interrupt-controller; |
327 | }; | 328 | }; |
328 | 329 | ||
329 | pinmux: pinmux { | 330 | pinmux: pinmux@70000868 { |
330 | compatible = "nvidia,tegra30-pinmux"; | 331 | compatible = "nvidia,tegra30-pinmux"; |
331 | reg = <0x70000868 0xd4 /* Pad control registers */ | 332 | reg = <0x70000868 0xd4 /* Pad control registers */ |
332 | 0x70003000 0x3e4>; /* Mux registers */ | 333 | 0x70003000 0x3e4>; /* Mux registers */ |
@@ -405,7 +406,7 @@ | |||
405 | status = "disabled"; | 406 | status = "disabled"; |
406 | }; | 407 | }; |
407 | 408 | ||
408 | pwm: pwm { | 409 | pwm: pwm@7000a000 { |
409 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; | 410 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
410 | reg = <0x7000a000 0x100>; | 411 | reg = <0x7000a000 0x100>; |
411 | #pwm-cells = <2>; | 412 | #pwm-cells = <2>; |
@@ -415,7 +416,7 @@ | |||
415 | status = "disabled"; | 416 | status = "disabled"; |
416 | }; | 417 | }; |
417 | 418 | ||
418 | rtc { | 419 | rtc@7000e000 { |
419 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | 420 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; |
420 | reg = <0x7000e000 0x100>; | 421 | reg = <0x7000e000 0x100>; |
421 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | 422 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
@@ -586,7 +587,7 @@ | |||
586 | status = "disabled"; | 587 | status = "disabled"; |
587 | }; | 588 | }; |
588 | 589 | ||
589 | kbc { | 590 | kbc@7000e200 { |
590 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; | 591 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; |
591 | reg = <0x7000e200 0x100>; | 592 | reg = <0x7000e200 0x100>; |
592 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | 593 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
@@ -596,14 +597,14 @@ | |||
596 | status = "disabled"; | 597 | status = "disabled"; |
597 | }; | 598 | }; |
598 | 599 | ||
599 | pmc { | 600 | pmc@7000e400 { |
600 | compatible = "nvidia,tegra30-pmc"; | 601 | compatible = "nvidia,tegra30-pmc"; |
601 | reg = <0x7000e400 0x400>; | 602 | reg = <0x7000e400 0x400>; |
602 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; | 603 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
603 | clock-names = "pclk", "clk32k_in"; | 604 | clock-names = "pclk", "clk32k_in"; |
604 | }; | 605 | }; |
605 | 606 | ||
606 | memory-controller { | 607 | memory-controller@7000f000 { |
607 | compatible = "nvidia,tegra30-mc"; | 608 | compatible = "nvidia,tegra30-mc"; |
608 | reg = <0x7000f000 0x010 | 609 | reg = <0x7000f000 0x010 |
609 | 0x7000f03c 0x1b4 | 610 | 0x7000f03c 0x1b4 |
@@ -612,7 +613,7 @@ | |||
612 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | 613 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
613 | }; | 614 | }; |
614 | 615 | ||
615 | iommu { | 616 | iommu@7000f010 { |
616 | compatible = "nvidia,tegra30-smmu"; | 617 | compatible = "nvidia,tegra30-smmu"; |
617 | reg = <0x7000f010 0x02c | 618 | reg = <0x7000f010 0x02c |
618 | 0x7000f1f0 0x010 | 619 | 0x7000f1f0 0x010 |
@@ -622,7 +623,7 @@ | |||
622 | nvidia,ahb = <&ahb>; | 623 | nvidia,ahb = <&ahb>; |
623 | }; | 624 | }; |
624 | 625 | ||
625 | ahub { | 626 | ahub@70080000 { |
626 | compatible = "nvidia,tegra30-ahub"; | 627 | compatible = "nvidia,tegra30-ahub"; |
627 | reg = <0x70080000 0x200 | 628 | reg = <0x70080000 0x200 |
628 | 0x70080200 0x100>; | 629 | 0x70080200 0x100>; |
@@ -784,7 +785,7 @@ | |||
784 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | 785 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; |
785 | reg = <0x7d004000 0x4000>; | 786 | reg = <0x7d004000 0x4000>; |
786 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | 787 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
787 | phy_type = "ulpi"; | 788 | phy_type = "utmi"; |
788 | clocks = <&tegra_car TEGRA30_CLK_USB2>; | 789 | clocks = <&tegra_car TEGRA30_CLK_USB2>; |
789 | resets = <&tegra_car 58>; | 790 | resets = <&tegra_car 58>; |
790 | reset-names = "usb"; | 791 | reset-names = "usb"; |
@@ -794,12 +795,23 @@ | |||
794 | 795 | ||
795 | phy2: usb-phy@7d004000 { | 796 | phy2: usb-phy@7d004000 { |
796 | compatible = "nvidia,tegra30-usb-phy"; | 797 | compatible = "nvidia,tegra30-usb-phy"; |
797 | reg = <0x7d004000 0x4000>; | 798 | reg = <0x7d004000 0x4000 0x7d000000 0x4000>; |
798 | phy_type = "ulpi"; | 799 | phy_type = "utmi"; |
799 | clocks = <&tegra_car TEGRA30_CLK_USB2>, | 800 | clocks = <&tegra_car TEGRA30_CLK_USB2>, |
800 | <&tegra_car TEGRA30_CLK_PLL_U>, | 801 | <&tegra_car TEGRA30_CLK_PLL_U>, |
801 | <&tegra_car TEGRA30_CLK_CDEV2>; | 802 | <&tegra_car TEGRA30_CLK_USBD>; |
802 | clock-names = "reg", "pll_u", "ulpi-link"; | 803 | clock-names = "reg", "pll_u", "utmi-pads"; |
804 | nvidia,hssync-start-delay = <9>; | ||
805 | nvidia,idle-wait-delay = <17>; | ||
806 | nvidia,elastic-limit = <16>; | ||
807 | nvidia,term-range-adj = <6>; | ||
808 | nvidia,xcvr-setup = <51>; | ||
809 | nvidia.xcvr-setup-use-fuses; | ||
810 | nvidia,xcvr-lsfslew = <2>; | ||
811 | nvidia,xcvr-lsrslew = <2>; | ||
812 | nvidia,xcvr-hsslew = <32>; | ||
813 | nvidia,hssquelch-level = <2>; | ||
814 | nvidia,hsdiscon-level = <5>; | ||
803 | status = "disabled"; | 815 | status = "disabled"; |
804 | }; | 816 | }; |
805 | 817 | ||