diff options
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
-rw-r--r-- | arch/arm/boot/dts/tegra20-trimslice.dts | 54 |
1 files changed, 30 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 78deea5c0d21..216fa6d50c65 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
@@ -1,17 +1,23 @@ | |||
1 | /dts-v1/; | 1 | /dts-v1/; |
2 | 2 | ||
3 | #include <dt-bindings/input/input.h> | ||
3 | #include "tegra20.dtsi" | 4 | #include "tegra20.dtsi" |
4 | 5 | ||
5 | / { | 6 | / { |
6 | model = "Compulab TrimSlice board"; | 7 | model = "Compulab TrimSlice board"; |
7 | compatible = "compulab,trimslice", "nvidia,tegra20"; | 8 | compatible = "compulab,trimslice", "nvidia,tegra20"; |
8 | 9 | ||
10 | aliases { | ||
11 | rtc0 = "/i2c@7000c500/rtc@56"; | ||
12 | rtc1 = "/rtc@7000e000"; | ||
13 | }; | ||
14 | |||
9 | memory { | 15 | memory { |
10 | reg = <0x00000000 0x40000000>; | 16 | reg = <0x00000000 0x40000000>; |
11 | }; | 17 | }; |
12 | 18 | ||
13 | host1x { | 19 | host1x@50000000 { |
14 | hdmi { | 20 | hdmi@54280000 { |
15 | status = "okay"; | 21 | status = "okay"; |
16 | 22 | ||
17 | vdd-supply = <&hdmi_vdd_reg>; | 23 | vdd-supply = <&hdmi_vdd_reg>; |
@@ -23,7 +29,7 @@ | |||
23 | }; | 29 | }; |
24 | }; | 30 | }; |
25 | 31 | ||
26 | pinmux { | 32 | pinmux@70000014 { |
27 | pinctrl-names = "default"; | 33 | pinctrl-names = "default"; |
28 | pinctrl-0 = <&state_default>; | 34 | pinctrl-0 = <&state_default>; |
29 | 35 | ||
@@ -191,49 +197,49 @@ | |||
191 | "dtb", "dtc", "dtd", "dte", "gmb", | 197 | "dtb", "dtc", "dtd", "dte", "gmb", |
192 | "gme", "i2cp", "pta", "slxc", "slxd", | 198 | "gme", "i2cp", "pta", "slxc", "slxd", |
193 | "spdi", "spdo", "uda"; | 199 | "spdi", "spdo", "uda"; |
194 | nvidia,pull = <0>; | 200 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
195 | nvidia,tristate = <1>; | 201 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
196 | }; | 202 | }; |
197 | conf_atb { | 203 | conf_atb { |
198 | nvidia,pins = "atb", "cdev1", "cdev2", "dap1", | 204 | nvidia,pins = "atb", "cdev1", "cdev2", "dap1", |
199 | "gma", "gmc", "gmd", "gpu", "gpu7", | 205 | "gma", "gmc", "gmd", "gpu", "gpu7", |
200 | "gpv", "sdio1", "slxa", "slxk", "uac"; | 206 | "gpv", "sdio1", "slxa", "slxk", "uac"; |
201 | nvidia,pull = <0>; | 207 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
202 | nvidia,tristate = <0>; | 208 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
203 | }; | 209 | }; |
204 | conf_ck32 { | 210 | conf_ck32 { |
205 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | 211 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
206 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | 212 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
207 | nvidia,pull = <0>; | 213 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
208 | }; | 214 | }; |
209 | conf_csus { | 215 | conf_csus { |
210 | nvidia,pins = "csus", "spia", "spib", | 216 | nvidia,pins = "csus", "spia", "spib", |
211 | "spid", "spif"; | 217 | "spid", "spif"; |
212 | nvidia,pull = <1>; | 218 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
213 | nvidia,tristate = <1>; | 219 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
214 | }; | 220 | }; |
215 | conf_ddc { | 221 | conf_ddc { |
216 | nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; | 222 | nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; |
217 | nvidia,pull = <2>; | 223 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
218 | nvidia,tristate = <0>; | 224 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
219 | }; | 225 | }; |
220 | conf_hdint { | 226 | conf_hdint { |
221 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | 227 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
222 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", | 228 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
223 | "lvp0", "pmc"; | 229 | "lvp0", "pmc"; |
224 | nvidia,tristate = <1>; | 230 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
225 | }; | 231 | }; |
226 | conf_irrx { | 232 | conf_irrx { |
227 | nvidia,pins = "irrx", "irtx", "kbca", "kbcb", | 233 | nvidia,pins = "irrx", "irtx", "kbca", "kbcb", |
228 | "kbcc", "kbcd", "kbce", "kbcf", "owc", | 234 | "kbcc", "kbcd", "kbce", "kbcf", "owc", |
229 | "spic", "spie", "spig", "spih", "uaa", | 235 | "spic", "spie", "spig", "spih", "uaa", |
230 | "uab", "uad", "uca", "ucb"; | 236 | "uab", "uad", "uca", "ucb"; |
231 | nvidia,pull = <2>; | 237 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
232 | nvidia,tristate = <1>; | 238 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
233 | }; | 239 | }; |
234 | conf_lc { | 240 | conf_lc { |
235 | nvidia,pins = "lc", "ls"; | 241 | nvidia,pins = "lc", "ls"; |
236 | nvidia,pull = <2>; | 242 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
237 | }; | 243 | }; |
238 | conf_ld0 { | 244 | conf_ld0 { |
239 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | 245 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
@@ -243,17 +249,17 @@ | |||
243 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | 249 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
244 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", | 250 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
245 | "lvs", "sdb"; | 251 | "lvs", "sdb"; |
246 | nvidia,tristate = <0>; | 252 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
247 | }; | 253 | }; |
248 | conf_ld17_0 { | 254 | conf_ld17_0 { |
249 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | 255 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
250 | "ld23_22"; | 256 | "ld23_22"; |
251 | nvidia,pull = <1>; | 257 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
252 | }; | 258 | }; |
253 | conf_spif { | 259 | conf_spif { |
254 | nvidia,pins = "spif"; | 260 | nvidia,pins = "spif"; |
255 | nvidia,pull = <1>; | 261 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
256 | nvidia,tristate = <0>; | 262 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
257 | }; | 263 | }; |
258 | }; | 264 | }; |
259 | }; | 265 | }; |
@@ -301,7 +307,7 @@ | |||
301 | }; | 307 | }; |
302 | }; | 308 | }; |
303 | 309 | ||
304 | pmc { | 310 | pmc@7000e400 { |
305 | nvidia,suspend-mode = <1>; | 311 | nvidia,suspend-mode = <1>; |
306 | nvidia,cpu-pwr-good-time = <5000>; | 312 | nvidia,cpu-pwr-good-time = <5000>; |
307 | nvidia,cpu-pwr-off-time = <5000>; | 313 | nvidia,cpu-pwr-off-time = <5000>; |
@@ -310,7 +316,7 @@ | |||
310 | nvidia,sys-clock-req-active-high; | 316 | nvidia,sys-clock-req-active-high; |
311 | }; | 317 | }; |
312 | 318 | ||
313 | pcie-controller { | 319 | pcie-controller@80003000 { |
314 | status = "okay"; | 320 | status = "okay"; |
315 | pex-clk-supply = <&pci_clk_reg>; | 321 | pex-clk-supply = <&pci_clk_reg>; |
316 | vdd-supply = <&pci_vdd_reg>; | 322 | vdd-supply = <&pci_vdd_reg>; |
@@ -366,7 +372,7 @@ | |||
366 | #address-cells = <1>; | 372 | #address-cells = <1>; |
367 | #size-cells = <0>; | 373 | #size-cells = <0>; |
368 | 374 | ||
369 | clk32k_in: clock { | 375 | clk32k_in: clock@0 { |
370 | compatible = "fixed-clock"; | 376 | compatible = "fixed-clock"; |
371 | reg=<0>; | 377 | reg=<0>; |
372 | #clock-cells = <0>; | 378 | #clock-cells = <0>; |
@@ -380,7 +386,7 @@ | |||
380 | power { | 386 | power { |
381 | label = "Power"; | 387 | label = "Power"; |
382 | gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; | 388 | gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; |
383 | linux,code = <116>; /* KEY_POWER */ | 389 | linux,code = <KEY_POWER>; |
384 | gpio-key,wakeup; | 390 | gpio-key,wakeup; |
385 | }; | 391 | }; |
386 | }; | 392 | }; |