1 files changed, 383 insertions, 30 deletions

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 9987dd0e9c59..f48487c2a970 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -8,6 +8,10 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/clock/r8a7790-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
         compatible = "renesas,r8a7790";
         interrupt-parent = <&gic>;
@@ -84,14 +88,14 @@
                         <0 0xf1002000 0 0x1000>,
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         gpio0: gpio@e6050000 {
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6050000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 4 0x4>;
+                interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
@@ -103,7 +107,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6051000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 5 0x4>;
+                interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 32 32>;
@@ -115,7 +119,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6052000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 6 0x4>;
+                interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 64 32>;
@@ -127,7 +131,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6053000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 7 0x4>;
+                interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 96 32>;
@@ -139,7 +143,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6054000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 8 0x4>;
+                interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 128 32>;
@@ -151,7 +155,7 @@
                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
                 reg = <0 0xe6055000 0 0x50>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 9 0x4>;
+                interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 160 32>;
@@ -159,21 +163,31 @@
                 interrupt-controller;
         };
 
+        thermal@e61f0000 {
+                compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+        };
+
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                                <1 14 0xf08>,
-                                <1 11 0xf08>,
-                                <1 10 0xf08>;
+                interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         irqc0: interrupt-controller@e61c0000 {
-                compatible = "renesas,irqc";
+                compatible = "renesas,irqc-r8a7790", "renesas,irqc";
                 #interrupt-cells = <2>;
                 interrupt-controller;
                 reg = <0 0xe61c0000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         i2c0: i2c@e6508000 {
@@ -182,7 +196,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6508000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 287 0x4>;
+                interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C0>;
                 status = "disabled";
         };
 
@@ -192,7 +207,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6518000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 288 0x4>;
+                interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C1>;
                 status = "disabled";
         };
 
@@ -202,7 +218,8 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6530000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 286 0x4>;
+                interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C2>;
                 status = "disabled";
         };
 
@@ -212,24 +229,27 @@
                 compatible = "renesas,i2c-r8a7790";
                 reg = <0 0xe6540000 0 0x40>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 290 0x4>;
+                interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_I2C3>;
                 status = "disabled";
         };
 
         mmcif0: mmcif@ee200000 {
-                compatible = "renesas,sh-mmcif";
+                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee200000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 169 0x4>;
+                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
 
-        mmcif1: mmcif@ee220000 {
-                compatible = "renesas,sh-mmcif";
+        mmcif1: mmc@ee220000 {
+                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                 reg = <0 0xee220000 0 0x80>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 170 0x4>;
+                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
                 reg-io-width = <4>;
                 status = "disabled";
         };
@@ -239,39 +259,372 @@
                 reg = <0 0xe6060000 0 0x250>;
         };
 
-        sdhi0: sdhi@ee100000 {
+        sdhi0: sd@ee100000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee100000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 165 4>;
+                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi1: sdhi@ee120000 {
+        sdhi1: sd@ee120000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee120000 0 0x200>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 166 4>;
+                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi2: sdhi@ee140000 {
+        sdhi2: sd@ee140000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee140000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 167 4>;
+                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
 
-        sdhi3: sdhi@ee160000 {
+        sdhi3: sd@ee160000 {
                 compatible = "renesas,sdhi-r8a7790";
                 reg = <0 0xee160000 0 0x100>;
                 interrupt-parent = <&gic>;
-                interrupts = <0 168 4>;
+                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
                 cap-sd-highspeed;
                 status = "disabled";
         };
+
+        clocks {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                /* External root clock */
+                extal_clk: extal_clk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        /* This value must be overriden by the board. */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7790-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "sdh", "sd0", "sd1",
+                                             "z";
+                };
+
+                /* Variable factor clocks */
+                sd2_clk: sd2_clk@e6150078 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150078 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd2";
+                };
+                sd3_clk: sd3_clk@e615007c {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615007c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "sd3";
+                };
+                mmc0_clk: mmc0_clk@e6150240 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150240 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc0";
+                };
+                mmc1_clk: mmc1_clk@e6150244 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150244 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "mmc1";
+                };
+                ssp_clk: ssp_clk@e6150248 {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe6150248 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssp";
+                };
+                ssprs_clk: ssprs_clk@e615024c {
+                        compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                        reg = <0 0xe615024c 0 4>;
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-output-names = "ssprs";
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "pll1_div2";
+                };
+                z2_clk: z2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "z2";
+                };
+                zg_clk: zg_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zg";
+                };
+                zx_clk: zx_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <3>;
+                        clock-mult = <1>;
+                        clock-output-names = "zx";
+                };
+                zs_clk: zs_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                        clock-output-names = "zs";
+                };
+                hp_clk: hp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "hp";
+                };
+                i_clk: i_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "i";
+                };
+                b_clk: b_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clock-output-names = "b";
+                };
+                p_clk: p_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                        clock-output-names = "p";
+                };
+                cl_clk: cl_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                        clock-output-names = "cl";
+                };
+                m2_clk: m2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "m2";
+                };
+                imp_clk: imp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "imp";
+                };
+                rclk_clk: rclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(48 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "rclk";
+                };
+                oscclk_clk: oscclk_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <(12 * 1024)>;
+                        clock-mult = <1>;
+                        clock-output-names = "oscclk";
+                };
+                zb3_clk: zb3_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3";
+                };
+                zb3d2_clk: zb3d2_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "zb3d2";
+                };
+                ddr_clk: ddr_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clock-output-names = "ddr";
+                };
+                mp_clk: mp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&pll1_div2_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <15>;
+                        clock-mult = <1>;
+                        clock-output-names = "mp";
+                };
+                cp_clk: cp_clk {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&extal_clk>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clock-output-names = "cp";
+                };
+
+                /* Gate clocks */
+                mstp0_clks: mstp0_clks@e6150130 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+                        clocks = <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
+                        clock-output-names = "msiof0";
+                };
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+                                 <&zs_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
+                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
+                        >;
+                        clock-output-names =
+                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+                                 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
+                                R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
+                                R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
+                        >;
+                        clock-output-names =
+                                "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
+                                "scifb1", "msiof1", "msiof3", "scifb2";
+                };
+                mstp3_clks: mstp3_clks@e615013c {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                        clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
+                                 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
+                                 <&mmc0_clk>, <&rclk_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
+                                R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
+                        >;
+                        clock-output-names =
+                                "tpu0", "mmcif1", "sdhi3", "sdhi2",
+                                "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                };
+                mstp5_clks: mstp5_clks@e6150144 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+                        clocks = <&extal_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
+                        clock-output-names = "thermal", "pwm";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+                                 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
+                                 <&zx_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
+                                R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
+                                R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
+                                R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
+                        >;
+                        clock-output-names =
+                                "ehci", "hsusb", "hscif1", "hscif0", "scif1",
+                                "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
+                };
+                mstp8_clks: mstp8_clks@e6150990 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+                        clocks = <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <R8A7790_CLK_ETHER>;
+                        clock-output-names = "ether";
+                };
+                mstp9_clks: mstp9_clks@e6150994 {
+                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
+                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        renesas,clock-indices = <
+                                R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
+                                R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
+                                R8A7790_CLK_I2C0
+                        >;
+                        clock-output-names =
+                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
+                };
+        };
 };