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-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi196
1 files changed, 101 insertions, 95 deletions
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index ca00d8326c87..bacab11c10dc 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,134 +22,140 @@
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp"; 23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24 24
25 L2: l2-cache { 25 soc {
26 compatible = "marvell,aurora-system-cache"; 26 internal-regs {
27 reg = <0xd0008000 0x1000>; 27 L2: l2-cache {
28 cache-id-part = <0x100>; 28 compatible = "marvell,aurora-system-cache";
29 wt-override; 29 reg = <0x08000 0x1000>;
30 }; 30 cache-id-part = <0x100>;
31 wt-override;
32 };
31 33
32 mpic: interrupt-controller@d0020000 { 34 mpic: interrupt-controller@20000 {
33 reg = <0xd0020a00 0x2d0>, 35 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
34 <0xd0021070 0x58>; 36 };
35 };
36 37
37 armada-370-xp-pmsu@d0022000 { 38 armada-370-xp-pmsu@22000 {
38 compatible = "marvell,armada-370-xp-pmsu"; 39 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>, 40 reg = <0x22100 0x430>, <0x20800 0x20>;
40 <0xd0020800 0x20>; 41 };
41 };
42 42
43 soc { 43 serial@12200 {
44 serial@d0012200 {
45 compatible = "snps,dw-apb-uart"; 44 compatible = "snps,dw-apb-uart";
46 reg = <0xd0012200 0x100>; 45 reg = <0x12200 0x100>;
47 reg-shift = <2>; 46 reg-shift = <2>;
48 interrupts = <43>; 47 interrupts = <43>;
49 reg-io-width = <1>; 48 reg-io-width = <1>;
50 status = "disabled"; 49 status = "disabled";
51 }; 50 };
52 serial@d0012300 { 51 serial@12300 {
53 compatible = "snps,dw-apb-uart"; 52 compatible = "snps,dw-apb-uart";
54 reg = <0xd0012300 0x100>; 53 reg = <0x12300 0x100>;
55 reg-shift = <2>; 54 reg-shift = <2>;
56 interrupts = <44>; 55 interrupts = <44>;
57 reg-io-width = <1>; 56 reg-io-width = <1>;
58 status = "disabled"; 57 status = "disabled";
59 }; 58 };
60 59
61 timer@d0020300 { 60 timer@20300 {
62 marvell,timer-25Mhz; 61 marvell,timer-25Mhz;
63 }; 62 };
64 63
65 coreclk: mvebu-sar@d0018230 { 64 coreclk: mvebu-sar@18230 {
66 compatible = "marvell,armada-xp-core-clock"; 65 compatible = "marvell,armada-xp-core-clock";
67 reg = <0xd0018230 0x08>; 66 reg = <0x18230 0x08>;
68 #clock-cells = <1>; 67 #clock-cells = <1>;
69 }; 68 };
70 69
71 cpuclk: clock-complex@d0018700 { 70 cpuclk: clock-complex@18700 {
72 #clock-cells = <1>; 71 #clock-cells = <1>;
73 compatible = "marvell,armada-xp-cpu-clock"; 72 compatible = "marvell,armada-xp-cpu-clock";
74 reg = <0xd0018700 0xA0>; 73 reg = <0x18700 0xA0>;
75 clocks = <&coreclk 1>; 74 clocks = <&coreclk 1>;
76 }; 75 };
77 76
78 gateclk: clock-gating-control@d0018220 { 77 gateclk: clock-gating-control@18220 {
79 compatible = "marvell,armada-xp-gating-clock"; 78 compatible = "marvell,armada-xp-gating-clock";
80 reg = <0xd0018220 0x4>; 79 reg = <0x18220 0x4>;
81 clocks = <&coreclk 0>; 80 clocks = <&coreclk 0>;
82 #clock-cells = <1>; 81 #clock-cells = <1>;
83 }; 82 };
84 83
85 system-controller@d0018200 { 84 system-controller@18200 {
86 compatible = "marvell,armada-370-xp-system-controller"; 85 compatible = "marvell,armada-370-xp-system-controller";
87 reg = <0xd0018200 0x500>; 86 reg = <0x18200 0x500>;
88 }; 87 };
89 88
90 ethernet@d0030000 { 89 ethernet@30000 {
91 compatible = "marvell,armada-370-neta"; 90 compatible = "marvell,armada-370-neta";
92 reg = <0xd0030000 0x2500>; 91 reg = <0x30000 0x2500>;
93 interrupts = <12>; 92 interrupts = <12>;
94 clocks = <&gateclk 2>; 93 clocks = <&gateclk 2>;
95 status = "disabled"; 94 status = "disabled";
96 };
97
98 xor@d0060900 {
99 compatible = "marvell,orion-xor";
100 reg = <0xd0060900 0x100
101 0xd0060b00 0x100>;
102 clocks = <&gateclk 22>;
103 status = "okay";
104
105 xor10 {
106 interrupts = <51>;
107 dmacap,memcpy;
108 dmacap,xor;
109 };
110 xor11 {
111 interrupts = <52>;
112 dmacap,memcpy;
113 dmacap,xor;
114 dmacap,memset;
115 }; 95 };
116 };
117 96
118 xor@d00f0900 { 97 xor@60900 {
119 compatible = "marvell,orion-xor"; 98 compatible = "marvell,orion-xor";
120 reg = <0xd00F0900 0x100 99 reg = <0x60900 0x100
121 0xd00F0B00 0x100>; 100 0x60b00 0x100>;
122 clocks = <&gateclk 28>; 101 clocks = <&gateclk 22>;
123 status = "okay"; 102 status = "okay";
103
104 xor10 {
105 interrupts = <51>;
106 dmacap,memcpy;
107 dmacap,xor;
108 };
109 xor11 {
110 interrupts = <52>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
115 };
124 116
125 xor00 { 117 xor@f0900 {
126 interrupts = <94>; 118 compatible = "marvell,orion-xor";
127 dmacap,memcpy; 119 reg = <0xF0900 0x100
128 dmacap,xor; 120 0xF0B00 0x100>;
121 clocks = <&gateclk 28>;
122 status = "okay";
123
124 xor00 {
125 interrupts = <94>;
126 dmacap,memcpy;
127 dmacap,xor;
128 };
129 xor01 {
130 interrupts = <95>;
131 dmacap,memcpy;
132 dmacap,xor;
133 dmacap,memset;
134 };
129 }; 135 };
130 xor01 { 136
131 interrupts = <95>; 137 usb@50000 {
132 dmacap,memcpy; 138 clocks = <&gateclk 18>;
133 dmacap,xor;
134 dmacap,memset;
135 }; 139 };
136 };
137 140
138 usb@d0050000 { 141 usb@51000 {
139 clocks = <&gateclk 18>; 142 clocks = <&gateclk 19>;
140 }; 143 };
141 144
142 usb@d0051000 { 145 usb@52000 {
143 clocks = <&gateclk 19>; 146 compatible = "marvell,orion-ehci";
144 }; 147 reg = <0x52000 0x500>;
148 interrupts = <47>;
149 clocks = <&gateclk 20>;
150 status = "disabled";
151 };
145 152
146 usb@d0052000 { 153 thermal@182b0 {
147 compatible = "marvell,orion-ehci"; 154 compatible = "marvell,armadaxp-thermal";
148 reg = <0xd0052000 0x500>; 155 reg = <0x182b0 0x4
149 interrupts = <47>; 156 0x184d0 0x4>;
150 clocks = <&gateclk 20>; 157 status = "okay";
151 status = "disabled"; 158 };
152 }; 159 };
153
154 }; 160 };
155}; 161};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 15:02:12 -0500