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Diffstat (limited to 'arch/arm/boot/dts/armada-xp-mv78260.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi308
1 files changed, 155 insertions, 153 deletions
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 1faacd13d514..f4029f015aff 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -45,177 +45,179 @@
45 }; 45 };
46 46
47 soc { 47 soc {
48 pinctrl { 48 internal-regs {
49 compatible = "marvell,mv78260-pinctrl"; 49 pinctrl {
50 reg = <0x18000 0x38>; 50 compatible = "marvell,mv78260-pinctrl";
51 51 reg = <0x18000 0x38>;
52 sdio_pins: sdio-pins { 52
53 marvell,pins = "mpp30", "mpp31", "mpp32", 53 sdio_pins: sdio-pins {
54 "mpp33", "mpp34", "mpp35"; 54 marvell,pins = "mpp30", "mpp31", "mpp32",
55 marvell,function = "sd0"; 55 "mpp33", "mpp34", "mpp35";
56 marvell,function = "sd0";
57 };
56 }; 58 };
57 };
58 59
59 gpio0: gpio@18100 { 60 gpio0: gpio@18100 {
60 compatible = "marvell,orion-gpio"; 61 compatible = "marvell,orion-gpio";
61 reg = <0x18100 0x40>; 62 reg = <0x18100 0x40>;
62 ngpios = <32>; 63 ngpios = <32>;
63 gpio-controller; 64 gpio-controller;
64 #gpio-cells = <2>; 65 #gpio-cells = <2>;
65 interrupt-controller; 66 interrupt-controller;
66 #interrupts-cells = <2>; 67 #interrupts-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 68 interrupts = <82>, <83>, <84>, <85>;
68 }; 69 };
69 70
70 gpio1: gpio@18140 { 71 gpio1: gpio@18140 {
71 compatible = "marvell,orion-gpio"; 72 compatible = "marvell,orion-gpio";
72 reg = <0x18140 0x40>; 73 reg = <0x18140 0x40>;
73 ngpios = <32>; 74 ngpios = <32>;
74 gpio-controller; 75 gpio-controller;
75 #gpio-cells = <2>; 76 #gpio-cells = <2>;
76 interrupt-controller; 77 interrupt-controller;
77 #interrupts-cells = <2>; 78 #interrupts-cells = <2>;
78 interrupts = <87>, <88>, <89>, <90>; 79 interrupts = <87>, <88>, <89>, <90>;
79 }; 80 };
80 81
81 gpio2: gpio@18180 { 82 gpio2: gpio@18180 {
82 compatible = "marvell,orion-gpio"; 83 compatible = "marvell,orion-gpio";
83 reg = <0x18180 0x40>; 84 reg = <0x18180 0x40>;
84 ngpios = <3>; 85 ngpios = <3>;
85 gpio-controller; 86 gpio-controller;
86 #gpio-cells = <2>; 87 #gpio-cells = <2>;
87 interrupt-controller; 88 interrupt-controller;
88 #interrupts-cells = <2>; 89 #interrupts-cells = <2>;
89 interrupts = <91>; 90 interrupts = <91>;
90 }; 91 };
91 92
92 ethernet@34000 { 93 ethernet@34000 {
93 compatible = "marvell,armada-370-neta"; 94 compatible = "marvell,armada-370-neta";
94 reg = <0x34000 0x2500>; 95 reg = <0x34000 0x2500>;
95 interrupts = <14>; 96 interrupts = <14>;
96 clocks = <&gateclk 1>; 97 clocks = <&gateclk 1>;
97 status = "disabled"; 98 status = "disabled";
98 };
99
100 /*
101 * MV78260 has 3 PCIe units Gen2.0: Two units can be
102 * configured as x4 or quad x1 lanes. One unit is
103 * x4/x1.
104 */
105 pcie-controller {
106 compatible = "marvell,armada-xp-pcie";
107 status = "disabled";
108 device_type = "pci";
109
110 #address-cells = <3>;
111 #size-cells = <2>;
112
113 bus-range = <0x00 0xff>;
114
115 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
116 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
117 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
118 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
119 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
120 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
121 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
122 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
123 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
124
125 pcie@1,0 {
126 device_type = "pci";
127 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
128 reg = <0x0800 0 0 0 0>;
129 #address-cells = <3>;
130 #size-cells = <2>;
131 #interrupt-cells = <1>;
132 ranges;
133 interrupt-map-mask = <0 0 0 0>;
134 interrupt-map = <0 0 0 0 &mpic 58>;
135 marvell,pcie-port = <0>;
136 marvell,pcie-lane = <0>;
137 clocks = <&gateclk 5>;
138 status = "disabled";
139 }; 99 };
140 100
141 pcie@2,0 { 101 /*
142 device_type = "pci"; 102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
143 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 103 * configured as x4 or quad x1 lanes. One unit is
144 reg = <0x1000 0 0 0 0>; 104 * x4/x1.
145 #address-cells = <3>; 105 */
146 #size-cells = <2>; 106 pcie-controller {
147 #interrupt-cells = <1>; 107 compatible = "marvell,armada-xp-pcie";
148 ranges;
149 interrupt-map-mask = <0 0 0 0>;
150 interrupt-map = <0 0 0 0 &mpic 59>;
151 marvell,pcie-port = <0>;
152 marvell,pcie-lane = <1>;
153 clocks = <&gateclk 6>;
154 status = "disabled"; 108 status = "disabled";
155 };
156
157 pcie@3,0 {
158 device_type = "pci"; 109 device_type = "pci";
159 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
160 reg = <0x1800 0 0 0 0>;
161 #address-cells = <3>;
162 #size-cells = <2>;
163 #interrupt-cells = <1>;
164 ranges;
165 interrupt-map-mask = <0 0 0 0>;
166 interrupt-map = <0 0 0 0 &mpic 60>;
167 marvell,pcie-port = <0>;
168 marvell,pcie-lane = <2>;
169 clocks = <&gateclk 7>;
170 status = "disabled";
171 };
172 110
173 pcie@4,0 {
174 device_type = "pci";
175 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
176 reg = <0x2000 0 0 0 0>;
177 #address-cells = <3>; 111 #address-cells = <3>;
178 #size-cells = <2>; 112 #size-cells = <2>;
179 #interrupt-cells = <1>;
180 ranges;
181 interrupt-map-mask = <0 0 0 0>;
182 interrupt-map = <0 0 0 0 &mpic 61>;
183 marvell,pcie-port = <0>;
184 marvell,pcie-lane = <3>;
185 clocks = <&gateclk 8>;
186 status = "disabled";
187 };
188 113
189 pcie@9,0 { 114 bus-range = <0x00 0xff>;
190 device_type = "pci"; 115
191 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
192 reg = <0x4800 0 0 0 0>; 117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
193 #address-cells = <3>; 118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
194 #size-cells = <2>; 119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
195 #interrupt-cells = <1>; 120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
196 ranges; 121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
197 interrupt-map-mask = <0 0 0 0>; 122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
198 interrupt-map = <0 0 0 0 &mpic 99>; 123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
199 marvell,pcie-port = <2>; 124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
200 marvell,pcie-lane = <0>; 125
201 clocks = <&gateclk 26>; 126 pcie@1,0 {
202 status = "disabled"; 127 device_type = "pci";
203 }; 128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
204 129 reg = <0x0800 0 0 0 0>;
205 pcie@10,0 { 130 #address-cells = <3>;
206 device_type = "pci"; 131 #size-cells = <2>;
207 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; 132 #interrupt-cells = <1>;
208 reg = <0x5000 0 0 0 0>; 133 ranges;
209 #address-cells = <3>; 134 interrupt-map-mask = <0 0 0 0>;
210 #size-cells = <2>; 135 interrupt-map = <0 0 0 0 &mpic 58>;
211 #interrupt-cells = <1>; 136 marvell,pcie-port = <0>;
212 ranges; 137 marvell,pcie-lane = <0>;
213 interrupt-map-mask = <0 0 0 0>; 138 clocks = <&gateclk 5>;
214 interrupt-map = <0 0 0 0 &mpic 103>; 139 status = "disabled";
215 marvell,pcie-port = <3>; 140 };
216 marvell,pcie-lane = <0>; 141
217 clocks = <&gateclk 27>; 142 pcie@2,0 {
218 status = "disabled"; 143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
219 }; 221 };
220 }; 222 };
221 }; 223 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 11:31:25 -0500