1 files changed, 105 insertions, 103 deletions
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 55bcbff39469..d9972c9a9279 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -37,126 +37,128 @@
        };
        soc {
-                serial@12000 {
+                internal-regs {
-                        clock-frequency = <250000000>;
+                        serial@12000 {
-                        status = "okay";
+                                clock-frequency = <250000000>;
-                };
+                                status = "okay";
-                serial@12100 {
-                        clock-frequency = <250000000>;
-                        status = "okay";
-                };
-                serial@12200 {
-                        clock-frequency = <250000000>;
-                        status = "okay";
-                };
-                serial@12300 {
-                        clock-frequency = <250000000>;
-                        status = "okay";
-                };
-                sata@a0000 {
-                        nr-ports = <2>;
-                        status = "okay";
-                };
-                mdio {
-                        phy0: ethernet-phy@0 {
-                                reg = <16>;
                        };
+                        serial@12100 {
-                        phy1: ethernet-phy@1 {
+                                clock-frequency = <250000000>;
-                                reg = <17>;
+                                status = "okay";
                        };
+                        serial@12200 {
-                        phy2: ethernet-phy@2 {
+                                clock-frequency = <250000000>;
-                                reg = <18>;
+                                status = "okay";
+                        };
+                        serial@12300 {
+                                clock-frequency = <250000000>;
+                                status = "okay";
                        };
-                        phy3: ethernet-phy@3 {
+                        sata@a0000 {
-                                reg = <19>;
+                                nr-ports = <2>;
+                                status = "okay";
                        };
-                };
-                ethernet@70000 {
+                        mdio {
-                        status = "okay";
+                                phy0: ethernet-phy@0 {
-                        phy = <&phy0>;
+                                        reg = <16>;
-                        phy-mode = "rgmii-id";
+                                };
-                };
-                ethernet@74000 {
-                        status = "okay";
-                        phy = <&phy1>;
-                        phy-mode = "rgmii-id";
-                };
-                ethernet@30000 {
-                        status = "okay";
-                        phy = <&phy2>;
-                        phy-mode = "rgmii-id";
-                };
-                ethernet@34000 {
-                        status = "okay";
-                        phy = <&phy3>;
-                        phy-mode = "rgmii-id";
-                };
-                spi0: spi@10600 {
+                                phy1: ethernet-phy@1 {
-                        status = "okay";
+                                        reg = <17>;
+                                };
-                        spi-flash@0 {
+                                phy2: ethernet-phy@2 {
-                                #address-cells = <1>;
+                                        reg = <18>;
-                                #size-cells = <1>;
+                                };
-                                compatible = "n25q128a13";
-                                reg = <0>; /* Chip select 0 */
-                                spi-max-frequency = <108000000>;
-                        };
-                };
-                devbus-bootcs@10400 {
+                                phy3: ethernet-phy@3 {
-                        status = "okay";
+                                        reg = <19>;
-                        ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
+                                };
-                        /* Device Bus parameters are required */
-                        /* Read parameters */
-                        devbus,bus-width    = <8>;
-                        devbus,turn-off-ps  = <60000>;
-                        devbus,badr-skew-ps = <0>;
-                        devbus,acc-first-ps = <124000>;
-                        devbus,acc-next-ps  = <248000>;
-                        devbus,rd-setup-ps  = <0>;
-                        devbus,rd-hold-ps   = <0>;
-                        /* Write parameters */
-                        devbus,sync-enable = <0>;
-                        devbus,wr-high-ps  = <60000>;
-                        devbus,wr-low-ps   = <60000>;
-                        devbus,ale-wr-ps   = <60000>;
-                        /* NOR 16 MiB */
-                        nor@0 {
-                                compatible = "cfi-flash";
-                                reg = <0 0x1000000>;
-                                bank-width = <2>;
                        };
-                };
-                pcie-controller {
+                        ethernet@70000 {
-                        status = "okay";
+                                status = "okay";
+                                phy = <&phy0>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@74000 {
+                                status = "okay";
+                                phy = <&phy1>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@30000 {
+                                status = "okay";
+                                phy = <&phy2>;
+                                phy-mode = "rgmii-id";
+                        };
+                        ethernet@34000 {
+                                status = "okay";
+                                phy = <&phy3>;
+                                phy-mode = "rgmii-id";
+                        };
-                        /*
+                        spi0: spi@10600 {
-                         * The 3 slots are physically present as
-                         * standard PCIe slots on the board.
-                         */
-                        pcie@1,0 {
-                                /* Port 0, Lane 0 */
                                status = "okay";
+                                spi-flash@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "n25q128a13";
+                                        reg = <0>; /* Chip select 0 */
+                                        spi-max-frequency = <108000000>;
+                                };
                        };
-                        pcie@9,0 {
-                                /* Port 2, Lane 0 */
+                        devbus-bootcs@10400 {
                                status = "okay";
+                                ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
+                                /* Device Bus parameters are required */
+                                /* Read parameters */
+                                devbus,bus-width    = <8>;
+                                devbus,turn-off-ps  = <60000>;
+                                devbus,badr-skew-ps = <0>;
+                                devbus,acc-first-ps = <124000>;
+                                devbus,acc-next-ps  = <248000>;
+                                devbus,rd-setup-ps  = <0>;
+                                devbus,rd-hold-ps   = <0>;
+                                /* Write parameters */
+                                devbus,sync-enable = <0>;
+                                devbus,wr-high-ps  = <60000>;
+                                devbus,wr-low-ps   = <60000>;
+                                devbus,ale-wr-ps   = <60000>;
+                                /* NOR 16 MiB */
+                                nor@0 {
+                                        compatible = "cfi-flash";
+                                        reg = <0 0x1000000>;
+                                        bank-width = <2>;
+                                };
                        };
-                        pcie@10,0 {
-                                /* Port 3, Lane 0 */
+                        pcie-controller {
                                status = "okay";
+                                /*
+                                 * The 3 slots are physically present as
+                                 * standard PCIe slots on the board.
+                                 */
+                                pcie@1,0 {
+                                        /* Port 0, Lane 0 */
+                                        status = "okay";
+                                };
+                                pcie@9,0 {
+                                        /* Port 2, Lane 0 */
+                                        status = "okay";
+                                };
+                                pcie@10,0 {
+                                        /* Port 3, Lane 0 */
+                                        status = "okay";
+                                };
                        };
                };
        };

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 55bcbff39469..d9972c9a9279 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -37,126 +37,128 @@
37	};	37	};
38		38
39	soc {	39	soc {
40	serial@12000 {	40	internal-regs {
41	clock-frequency = <250000000>;	41	serial@12000 {
42	status = "okay";	42	clock-frequency = <250000000>;
43	};	43	status = "okay";
44	serial@12100 {
45	clock-frequency = <250000000>;
46	status = "okay";
47	};
48	serial@12200 {
49	clock-frequency = <250000000>;
50	status = "okay";
51	};
52	serial@12300 {
53	clock-frequency = <250000000>;
54	status = "okay";
55	};
56
57	sata@a0000 {
58	nr-ports = <2>;
59	status = "okay";
60	};
61
62	mdio {
63	phy0: ethernet-phy@0 {
64	reg = <16>;
65	};	44	};
66		45	serial@12100 {
67	phy1: ethernet-phy@1 {	46	clock-frequency = <250000000>;
68	reg = <17>;	47	status = "okay";
69	};	48	};
70		49	serial@12200 {
71	phy2: ethernet-phy@2 {	50	clock-frequency = <250000000>;
72	reg = <18>;	51	status = "okay";
		52	};
		53	serial@12300 {
		54	clock-frequency = <250000000>;
		55	status = "okay";
73	};	56	};
74		57
75	phy3: ethernet-phy@3 {	58	sata@a0000 {
76	reg = <19>;	59	nr-ports = <2>;
		60	status = "okay";
77	};	61	};
78	};
79		62
80	ethernet@70000 {	63	mdio {
81	status = "okay";	64	phy0: ethernet-phy@0 {
82	phy = <&phy0>;	65	reg = <16>;
83	phy-mode = "rgmii-id";	66	};
84	};
85	ethernet@74000 {
86	status = "okay";
87	phy = <&phy1>;
88	phy-mode = "rgmii-id";
89	};
90	ethernet@30000 {
91	status = "okay";
92	phy = <&phy2>;
93	phy-mode = "rgmii-id";
94	};
95	ethernet@34000 {
96	status = "okay";
97	phy = <&phy3>;
98	phy-mode = "rgmii-id";
99	};
100		67
101	spi0: spi@10600 {	68	phy1: ethernet-phy@1 {
102	status = "okay";	69	reg = <17>;
		70	};
103		71
104	spi-flash@0 {	72	phy2: ethernet-phy@2 {
105	#address-cells = <1>;	73	reg = <18>;
106	#size-cells = <1>;	74	};
107	compatible = "n25q128a13";
108	reg = <0>; /* Chip select 0 */
109	spi-max-frequency = <108000000>;
110	};
111	};
112		75
113	devbus-bootcs@10400 {	76	phy3: ethernet-phy@3 {
114	status = "okay";	77	reg = <19>;
115	ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */	78	};
116
117	/* Device Bus parameters are required */
118
119	/* Read parameters */
120	devbus,bus-width = <8>;
121	devbus,turn-off-ps = <60000>;
122	devbus,badr-skew-ps = <0>;
123	devbus,acc-first-ps = <124000>;
124	devbus,acc-next-ps = <248000>;
125	devbus,rd-setup-ps = <0>;
126	devbus,rd-hold-ps = <0>;
127
128	/* Write parameters */
129	devbus,sync-enable = <0>;
130	devbus,wr-high-ps = <60000>;
131	devbus,wr-low-ps = <60000>;
132	devbus,ale-wr-ps = <60000>;
133
134	/* NOR 16 MiB */
135	nor@0 {
136	compatible = "cfi-flash";
137	reg = <0 0x1000000>;
138	bank-width = <2>;
139	};	79	};
140	};
141		80
142	pcie-controller {	81	ethernet@70000 {
143	status = "okay";	82	status = "okay";
		83	phy = <&phy0>;
		84	phy-mode = "rgmii-id";
		85	};
		86	ethernet@74000 {
		87	status = "okay";
		88	phy = <&phy1>;
		89	phy-mode = "rgmii-id";
		90	};
		91	ethernet@30000 {
		92	status = "okay";
		93	phy = <&phy2>;
		94	phy-mode = "rgmii-id";
		95	};
		96	ethernet@34000 {
		97	status = "okay";
		98	phy = <&phy3>;
		99	phy-mode = "rgmii-id";
		100	};
144		101
145	/*	102	spi0: spi@10600 {
146	* The 3 slots are physically present as
147	* standard PCIe slots on the board.
148	*/
149	pcie@1,0 {
150	/* Port 0, Lane 0 */
151	status = "okay";	103	status = "okay";
		104
		105	spi-flash@0 {
		106	#address-cells = <1>;
		107	#size-cells = <1>;
		108	compatible = "n25q128a13";
		109	reg = <0>; /* Chip select 0 */
		110	spi-max-frequency = <108000000>;
		111	};
152	};	112	};
153	pcie@9,0 {	113
154	/* Port 2, Lane 0 */	114	devbus-bootcs@10400 {
155	status = "okay";	115	status = "okay";
		116	ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
		117
		118	/* Device Bus parameters are required */
		119
		120	/* Read parameters */
		121	devbus,bus-width = <8>;
		122	devbus,turn-off-ps = <60000>;
		123	devbus,badr-skew-ps = <0>;
		124	devbus,acc-first-ps = <124000>;
		125	devbus,acc-next-ps = <248000>;
		126	devbus,rd-setup-ps = <0>;
		127	devbus,rd-hold-ps = <0>;
		128
		129	/* Write parameters */
		130	devbus,sync-enable = <0>;
		131	devbus,wr-high-ps = <60000>;
		132	devbus,wr-low-ps = <60000>;
		133	devbus,ale-wr-ps = <60000>;
		134
		135	/* NOR 16 MiB */
		136	nor@0 {
		137	compatible = "cfi-flash";
		138	reg = <0 0x1000000>;
		139	bank-width = <2>;
		140	};
156	};	141	};
157	pcie@10,0 {	142
158	/* Port 3, Lane 0 */	143	pcie-controller {
159	status = "okay";	144	status = "okay";
		145
		146	/*
		147	* The 3 slots are physically present as
		148	* standard PCIe slots on the board.
		149	*/
		150	pcie@1,0 {
		151	/* Port 0, Lane 0 */
		152	status = "okay";
		153	};
		154	pcie@9,0 {
		155	/* Port 2, Lane 0 */
		156	status = "okay";
		157	};
		158	pcie@10,0 {
		159	/* Port 3, Lane 0 */
		160	status = "okay";
		161	};
160	};	162	};
161	};	163	};
162	};	164	};