1 files changed, 20 insertions, 5 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 41cbb4a53066..0d1b717e1eca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -188,6 +188,9 @@ config ARCH_HAS_ILOG2_U64
 config ARCH_HAS_BANDGAP
         bool
 
+config FIX_EARLYCON_MEM
+        def_bool y if MMU
+
 config GENERIC_HWEIGHT
         bool
         default y
@@ -1496,6 +1499,7 @@ config HOTPLUG_CPU
 config ARM_PSCI
         bool "Support for the ARM Power State Coordination Interface (PSCI)"
         depends on CPU_V7
+        select ARM_PSCI_FW
         help
           Say Y here if you want Linux to communicate with system firmware
           implementing the PSCI specification for CPU-centric power
@@ -1700,13 +1704,24 @@ config HIGHPTE
           consumed by page tables.  Setting this option will allow
           user-space 2nd level page tables to reside in high memory.
 
-config HW_PERF_EVENTS
-        bool "Enable hardware performance counter support for perf events"
-        depends on PERF_EVENTS
+config CPU_SW_DOMAIN_PAN
+        bool "Enable use of CPU domains to implement privileged no-access"
+        depends on MMU && !ARM_LPAE
         default y
         help
-          Enable hardware performance counter support for perf events. If
-          disabled, perf events will use software events only.
+          Increase kernel security by ensuring that normal kernel accesses
+          are unable to access userspace addresses.  This can help prevent
+          use-after-free bugs becoming an exploitable privilege escalation
+          by ensuring that magic values (such as LIST_POISON) will always
+          fault when dereferenced.
+
+          CPUs with low-vector mappings use a best-efforts implementation.
+          Their lower 1MB needs to remain accessible for the vectors, but
+          the remainder of userspace will become appropriately inaccessible.
+
+config HW_PERF_EVENTS
+        def_bool y
+        depends on ARM_PMU
 
 config SYS_SUPPORTS_HUGETLBFS
        def_bool y