aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/ata/marvell.txt6
-rw-r--r--Documentation/devicetree/bindings/phy/berlin-sata-phy.txt4
-rw-r--r--Documentation/devicetree/bindings/phy/berlin-usb-phy.txt16
-rw-r--r--Documentation/devicetree/bindings/phy/phy-miphy28lp.txt128
-rw-r--r--Documentation/devicetree/bindings/phy/phy-mvebu.txt43
-rw-r--r--Documentation/devicetree/bindings/phy/samsung-phy.txt6
-rw-r--r--Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt24
-rw-r--r--Documentation/devicetree/bindings/usb/dwc3.txt23
-rw-r--r--Documentation/devicetree/bindings/usb/exynos-usb.txt6
-rw-r--r--Documentation/devicetree/bindings/usb/pxa-usb.txt22
-rw-r--r--Documentation/devicetree/bindings/usb/usb-ohci.txt2
11 files changed, 277 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index 1c8351604d38..b460edd12766 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
6- interrupts : Interrupt controller is using 6- interrupts : Interrupt controller is using
7- nr-ports : Number of SATA ports in use. 7- nr-ports : Number of SATA ports in use.
8 8
9Optional Properties:
10- phys : List of phandles to sata phys
11- phy-names : Should be "0", "1", etc, one number per phandle
12
9Example: 13Example:
10 14
11 sata@80000 { 15 sata@80000 {
12 compatible = "marvell,orion-sata"; 16 compatible = "marvell,orion-sata";
13 reg = <0x80000 0x5000>; 17 reg = <0x80000 0x5000>;
14 interrupts = <21>; 18 interrupts = <21>;
19 phys = <&sata_phy0>, <&sata_phy1>;
20 phy-names = "0", "1";
15 nr-ports = <2>; 21 nr-ports = <2>;
16 } 22 }
diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
index 88f8c23384c0..c0155f842f62 100644
--- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
@@ -2,7 +2,9 @@ Berlin SATA PHY
2--------------- 2---------------
3 3
4Required properties: 4Required properties:
5- compatible: should be "marvell,berlin2q-sata-phy" 5- compatible: should be one of
6 "marvell,berlin2-sata-phy"
7 "marvell,berlin2q-sata-phy"
6- address-cells: should be 1 8- address-cells: should be 1
7- size-cells: should be 0 9- size-cells: should be 0
8- phy-cells: from the generic PHY bindings, must be 1 10- phy-cells: from the generic PHY bindings, must be 1
diff --git a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
new file mode 100644
index 000000000000..be33780f668e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
@@ -0,0 +1,16 @@
1* Marvell Berlin USB PHY
2
3Required properties:
4- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
5- reg: base address and length of the registers
6- #phys-cells: should be 0
7- resets: reference to the reset controller
8
9Example:
10
11 usb-phy@f774000 {
12 compatible = "marvell,berlin2-usb-phy";
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
16 };
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
new file mode 100644
index 000000000000..46a135dae6b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -0,0 +1,128 @@
1STMicroelectronics STi MIPHY28LP PHY binding
2============================================
3
4This binding describes a miphy device that is used to control PHY hardware
5for SATA, PCIe or USB3.
6
7Required properties (controller (parent) node):
8- compatible : Should be "st,miphy28lp-phy".
9- st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
11
12Required nodes : A sub-node is required for each channel the controller
13 provides. Address range information including the usual
14 'reg' and 'reg-names' properties are used inside these
15 nodes to describe the controller's topology. These nodes
16 are translated by the driver's .xlate() function.
17
18Required properties (port (child) node):
19- #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
24- reg : Address and length of the register set for the device.
25- reg-names : The names of the register addresses corresponding to the registers
26 filled in "reg". It can also contain the offset of the system configuration
27 registers used as glue-logic to setup the device for SATA/PCIe or USB3
28 devices.
29- resets : phandle to the parent reset controller.
30- reset-names : Associated name must be "miphy-sw-rst".
31
32Optional properties (port (child) node):
33- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
34 is not available in all the MiPHY. For example, for STiH407, only the
35 MiPHY0 has this bit.
36- st,osc-force-ext : to select the external oscillator. This can change from
37 different MiPHY inside the same SoC.
38- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
39 register.
40- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
41 line).
42- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
43- st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
44
45example:
46
47 miphy28lp_phy: miphy28lp@9b22000 {
48 compatible = "st,miphy28lp-phy";
49 st,syscfg = <&syscfg_core>;
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 phy_port0: port@9b22000 {
55 reg = <0x9b22000 0xff>,
56 <0x9b09000 0xff>,
57 <0x9b04000 0xff>,
58 <0x114 0x4>, /* sysctrl MiPHY cntrl */
59 <0x818 0x4>, /* sysctrl MiPHY status*/
60 <0xe0 0x4>, /* sysctrl PCIe */
61 <0xec 0x4>; /* sysctrl SATA */
62 reg-names = "sata-up",
63 "pcie-up",
64 "pipew",
65 "miphy-ctrl-glue",
66 "miphy-status-glue",
67 "pcie-glue",
68 "sata-glue";
69 #phy-cells = <1>;
70 st,osc-rdy;
71 reset-names = "miphy-sw-rst";
72 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
73 };
74
75 phy_port1: port@9b2a000 {
76 reg = <0x9b2a000 0xff>,
77 <0x9b19000 0xff>,
78 <0x9b14000 0xff>,
79 <0x118 0x4>,
80 <0x81c 0x4>,
81 <0xe4 0x4>,
82 <0xf0 0x4>;
83 reg-names = "sata-up",
84 "pcie-up",
85 "pipew",
86 "miphy-ctrl-glue",
87 "miphy-status-glue",
88 "pcie-glue",
89 "sata-glue";
90 #phy-cells = <1>;
91 st,osc-force-ext;
92 reset-names = "miphy-sw-rst";
93 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
94 };
95
96 phy_port2: port@8f95000 {
97 reg = <0x8f95000 0xff>,
98 <0x8f90000 0xff>,
99 <0x11c 0x4>,
100 <0x820 0x4>;
101 reg-names = "pipew",
102 "usb3-up",
103 "miphy-ctrl-glue",
104 "miphy-status-glue";
105 #phy-cells = <1>;
106 reset-names = "miphy-sw-rst";
107 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
108 };
109 };
110
111
112Specifying phy control of devices
113=================================
114
115Device nodes should specify the configuration required in their "phys"
116property, containing a phandle to the miphy device node and an index
117specifying which configuration to use, as described in phy-bindings.txt.
118
119example:
120 sata0: sata@9b20000 {
121 ...
122 phys = <&phy_port0 PHY_TYPE_SATA>;
123 ...
124 };
125
126Macro definitions for the supported miphy configuration can be found in:
127
128include/dt-bindings/phy/phy-miphy28lp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
new file mode 100644
index 000000000000..f95b6260a3b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
@@ -0,0 +1,43 @@
1* Marvell MVEBU SATA PHY
2
3Power control for the SATA phy found on Marvell MVEBU SoCs.
4
5This document extends the binding described in phy-bindings.txt
6
7Required properties :
8
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
13
14Example:
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
17 reg = <0x84000 0x0334>;
18 clocks = <&gate_clk 15>;
19 clock-names = "sata";
20 #phy-cells = <0>;
21 status = "ok";
22 };
23
24Armada 375 USB cluster
25----------------------
26
27Armada 375 comes with an USB2 host and device controller and an USB3
28controller. The USB cluster control register allows to manage common
29features of both USB controllers.
30
31Required properties:
32
33- compatible: "marvell,armada-375-usb-cluster"
34- reg: Should contain usb cluster register location and length.
35- #phy-cells : from the generic phy bindings, must be 1. Possible
36values are 1 (USB2), 2 (USB3).
37
38Example:
39 usbcluster: usb-cluster@18400 {
40 compatible = "marvell,armada-375-usb-cluster";
41 reg = <0x18400 0x4>;
42 #phy-cells = <1>
43 };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c7130f..d5bad920827f 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
128- compatible : Should be set to one of the following supported values: 128- compatible : Should be set to one of the following supported values:
129 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, 129 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
130 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. 130 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
131 - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
131- reg : Register offset and length of USB DRD PHY register set; 132- reg : Register offset and length of USB DRD PHY register set;
132- clocks: Clock IDs array as required by the controller 133- clocks: Clock IDs array as required by the controller
133- clock-names: names of clocks correseponding to IDs in the clock property; 134- clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
138 PHY operations, associated by phy name. It is used to 139 PHY operations, associated by phy name. It is used to
139 determine bit values for clock settings register. 140 determine bit values for clock settings register.
140 For Exynos5420 this is given as 'sclk_usbphy30' in CMU. 141 For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
142 - optional clocks: Exynos7 SoC has now following additional
143 gate clocks available:
144 - phy_pipe: for PIPE3 phy
145 - phy_utmi: for UTMI+ phy
146 - itp: for ITP generation
141- samsung,pmu-syscon: phandle for PMU system controller interface, used to 147- samsung,pmu-syscon: phandle for PMU system controller interface, used to
142 control pmu registers for power isolation. 148 control pmu registers for power isolation.
143- #phy-cells : from the generic PHY bindings, must be 1; 149- #phy-cells : from the generic PHY bindings, must be 1;
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
new file mode 100644
index 000000000000..27f8b1e5ee46
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
@@ -0,0 +1,24 @@
1* USB2 ChipIdea USB controller for ci13xxx
2
3Required properties:
4- compatible: should be "chipidea,usb2"
5- reg: base address and length of the registers
6- interrupts: interrupt for the USB controller
7
8Optional properties:
9- clocks: reference to the USB clock
10- phys: reference to the USB PHY
11- phy-names: should be "usb-phy"
12- vbus-supply: reference to the VBUS regulator
13
14Example:
15
16 usb@f7ed0000 {
17 compatible = "chipidea,usb2";
18 reg = <0xf7ed0000 0x10000>;
19 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
20 clocks = <&chip CLKID_USB0>;
21 phys = <&usb_phy0>;
22 phy-names = "usb-phy";
23 vbus-supply = <&reg_usb0_vbus>;
24 };
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 471366d6a129..cd7f0454e13a 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -14,6 +14,29 @@ Optional properties:
14 - phys: from the *Generic PHY* bindings 14 - phys: from the *Generic PHY* bindings
15 - phy-names: from the *Generic PHY* bindings 15 - phy-names: from the *Generic PHY* bindings
16 - tx-fifo-resize: determines if the FIFO *has* to be reallocated. 16 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
17 - snps,disable_scramble_quirk: true when SW should disable data scrambling.
18 Only really useful for FPGA builds.
19 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
20 - snps,lpm-nyet-threshold: LPM NYET threshold
21 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
22 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
23 - snps,req_p1p2p3_quirk: when set, the core will always request for
24 P1/P2/P3 transition sequence.
25 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
26 amount of 8B10B errors occur.
27 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
28 from P0 to P1/P2/P3.
29 - snps,lfps_filter_quirk: when set core will filter LFPS reception.
30 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
31 Polling LFPS after RX.Detect.
32 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
33 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
34 LTSSM during USB3 Compliance mode.
35 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
36 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
37 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
38 utmi_l1_suspend_n, false when asserts utmi_sleep_n
39 - snps,hird-threshold: HIRD threshold
17 40
18This is usually a subnode to DWC3 glue to which it is connected. 41This is usually a subnode to DWC3 glue to which it is connected.
19 42
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index a3b5990d0f2c..9b4dbe3b2acc 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -82,8 +82,10 @@ Example:
82 82
83DWC3 83DWC3
84Required properties: 84Required properties:
85 - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3 85 - compatible: should be one of the following -
86 controller. 86 "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
87 Exynos5250/5420.
88 "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
87 - #address-cells, #size-cells : should be '1' if the device has sub-nodes 89 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
88 with 'reg' property. 90 with 'reg' property.
89 - ranges: allows valid 1:1 translation between child's address space and 91 - ranges: allows valid 1:1 translation between child's address space and
diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt
index 79729a948d5a..9c331799b87c 100644
--- a/Documentation/devicetree/bindings/usb/pxa-usb.txt
+++ b/Documentation/devicetree/bindings/usb/pxa-usb.txt
@@ -29,3 +29,25 @@ Example:
29 marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ 29 marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */
30 }; 30 };
31 31
32UDC
33
34Required properties:
35 - compatible: Should be "marvell,pxa270-udc" for USB controllers
36 used in device mode.
37 - reg: usb device MMIO address space
38 - interrupts: single interrupt generated by the UDC IP
39 - clocks: input clock of the UDC IP (see clock-bindings.txt)
40
41Optional properties:
42 - gpios:
43 - gpio activated to control the USB D+ pullup (see gpio.txt)
44
45Example:
46
47 pxa27x_udc: udc@40600000 {
48 compatible = "marvell,pxa270-udc";
49 reg = <0x40600000 0x10000>;
50 interrupts = <11>;
51 clocks = <&pxa2xx_clks 11>;
52 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
53 };
diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
index b968a1aea995..19233b7365e1 100644
--- a/Documentation/devicetree/bindings/usb/usb-ohci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
@@ -9,6 +9,8 @@ Optional properties:
9- big-endian-regs : boolean, set this for hcds with big-endian registers 9- big-endian-regs : boolean, set this for hcds with big-endian registers
10- big-endian-desc : boolean, set this for hcds with big-endian descriptors 10- big-endian-desc : boolean, set this for hcds with big-endian descriptors
11- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc 11- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
12- no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA
13- num-ports : u32, to override the detected port count
12- clocks : a list of phandle + clock specifier pairs 14- clocks : a list of phandle + clock specifier pairs
13- phys : phandle + phy specifier pair 15- phys : phandle + phy specifier pair
14- phy-names : "usb" 16- phy-names : "usb"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 13:31:35 -0500