13 files changed, 244 insertions, 19 deletions

diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 5fac246a9530..3509707f9320 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -14,6 +14,9 @@ Required nodes:
 - core-module: the root node to the Integrator platforms must have
   a core-module with regs and the compatible string
   "arm,core-module-integrator"
+- external-bus-interface: the root node to the Integrator platforms
+  must have an external bus interface with regs and the
+  compatible-string "arm,external-bus-interface"
 
   Required properties for the core module:
   - regs: the location and size of the core module registers, one
@@ -48,6 +51,11 @@ Required nodes:
                 reg = <0x10000000 0x200>;
         };
 
+        ebi@12000000 {
+                compatible = "arm,external-bus-interface";
+                reg = <0x12000000 0x100>;
+        };
+
         syscon {
                 compatible = "arm,integrator-ap-syscon";
                 reg = <0x11000000 0x100>;
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
index ad031211b5b8..2742e9cfd6b1 100644
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible: Should be "atmel,<chip>-aic"
+  <chip> can be "at91rm9200" or "sama5d3"
 - interrupt-controller: Identifies the node as an interrupt controller.
 - interrupt-parent: For single AIC system, it is an empty property.
 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 78530e621a1e..16f60b41c147 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -58,7 +58,8 @@ Example:
         };
 
 RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91sam9260-sdramc",
+- compatible: Should be "atmel,at91rm9200-sdramc",
+                        "atmel,at91sam9260-sdramc",
                         "atmel,at91sam9g45-ddramc",
 - reg: Should contain registers location and length
   For at91sam9263 and at91sam9g45 you must specify 2 entries.
diff --git a/Documentation/devicetree/bindings/arm/moxart.txt b/Documentation/devicetree/bindings/arm/moxart.txt
new file mode 100644
index 000000000000..11087edb0658
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/moxart.txt
@@ -0,0 +1,12 @@
+MOXA ART device tree bindings
+
+Boards with the MOXA ART SoC shall have the following properties:
+
+Required root node property:
+
+compatible = "moxa,moxart";
+
+Boards:
+
+- UC-7112-LX: embedded computer
+  compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart"
diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
index 5039c0a12f55..0ab3251a6ec2 100644
--- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
@@ -1,7 +1,12 @@
 SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
 
 Properties:
- - name : should be 'sysreg';
  - compatible : should contain "samsung,<chip name>-sysreg", "syscon";
    For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
  - reg : offset and length of the register set.
+
+Example:
+        syscon@10010000 {
+                compatible = "samsung,exynos4-sysreg", "syscon";
+                reg = <0x10010000 0x400>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
new file mode 100644
index 000000000000..952e373178d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -0,0 +1,28 @@
+* Renesas CPG DIV6 Clock
+
+The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
+Generator (CPG). They clock input is divided by a configurable factor from 1
+to 64.
+
+Required Properties:
+
+  - compatible: Must be one of the following
+    - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
+    - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,cpg-div6-clock" for generic DIV6 clocks
+  - reg: Base address and length of the memory resource used by the DIV6 clock
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 0
+  - clock-output-names: The name of the clock as a free-form string
+
+
+Example
+-------
+
+        sd2_clk: sd2_clk@e6150078 {
+                compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
+                reg = <0 0xe6150078 0 4>;
+                clocks = <&pll1_div2_clk>;
+                #clock-cells = <0>;
+                clock-output-names = "sd2";
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
new file mode 100644
index 000000000000..a6a352c2771e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -0,0 +1,51 @@
+* Renesas CPG Module Stop (MSTP) Clocks
+
+The CPG can gate SoC device clocks. The gates are organized in groups of up to
+32 gates.
+
+This device tree binding describes a single 32 gate clocks group per node.
+Clocks are referenced by user nodes by the MSTP node phandle and the clock
+index in the group, from 0 to 31.
+
+Required Properties:
+
+  - compatible: Must be one of the following
+    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
+    - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+    - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
+  - reg: Base address and length of the I/O mapped registers used by the MSTP
+    clocks. The first register is the clock control register and is mandatory.
+    The second register is the clock status register and is optional when not
+    implemented in hardware.
+  - clocks: Reference to the parent clocks, one per output clock. The parents
+    must appear in the same order as the output clocks.
+  - #clock-cells: Must be 1
+  - clock-output-names: The name of the clocks as free-form strings
+  - renesas,indices: Indices of the gate clocks into the group (0 to 31)
+
+The clocks, clock-output-names and renesas,indices properties contain one
+entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
+gate clocks must not be declared.
+
+
+Example
+-------
+
+        #include <dt-bindings/clock/r8a7790-clock.h>
+
+        mstp3_clks: mstp3_clks@e615013c {
+                compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
+                reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+                clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
+                         <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
+                         <&mmc0_clk>;
+                #clock-cells = <1>;
+                clock-output-names =
+                        "tpu0", "mmcif1", "sdhi3", "sdhi2",
+                         "sdhi1", "sdhi0", "mmcif0";
+                renesas,clock-indices = <
+                        R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+                        R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
+                        R8A7790_CLK_MMCIF0
+                >;
+        };
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
new file mode 100644
index 000000000000..7b41c2fe54db
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -0,0 +1,32 @@
+* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
+
+The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
+and several fixed ratio dividers.
+
+Required Properties:
+
+  - compatible: Must be one of
+    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
+    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
+    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
+
+  - reg: Base address and length of the memory resource used by the CPG
+
+  - clocks: Reference to the parent clock
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "main",
+    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"
+
+
+Example
+-------
+
+        cpg_clocks: cpg_clocks@e6150000 {
+                compatible = "renesas,r8a7790-cpg-clocks",
+                             "renesas,rcar-gen2-cpg-clocks";
+                reg = <0 0xe6150000 0 0x1000>;
+                clocks = <&extal_clk>;
+                #clock-cells = <1>;
+                clock-output-names = "main", "pll0, "pll1", "pll3",
+                                     "lb", "qspi", "sdh", "sd0", "sd1", "z";
+        };
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index a8c21c256baa..1f5729f10621 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -50,6 +50,9 @@ Each dmas request consists of 4 cells:
         0x00000008: Use fixed channel:
                 Use automatic channel selection when unset
                 Use DMA request line number when set
+        0x00000010: Set channel as high priority:
+                Normal priority when unset
+                High priority when set
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index c67b975c8906..532b1d440abc 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
           specific extensions.
         - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
           specific extensions.
+        - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
+          specific extensions.
 
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
   unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index b5a86d20ee36..167d5dab9f64 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -31,38 +31,58 @@ Required properties:
         7: ..
         i: Local Timer Interrupt n
 
-Example 1: In this example, the system uses only the first global timer
-           interrupt generated by MCT and the remaining three global timer
-           interrupts are unused. Two local timer interrupts have been
-           specified.
+  For MCT block that uses a per-processor interrupt for local timers, such
+  as ones compatible with "samsung,exynos4412-mct", only one local timer
+  interrupt might be specified, meaning that all local timers use the same
+  per processor interrupt.
+
+Example 1: In this example, the IP contains two local timers, using separate
+           interrupts, so two local timer interrupts have been specified,
+           in addition to four global timer interrupts.
 
         mct@10050000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x10050000 0x800>;
-                interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
+                interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
                              <0 42 0>, <0 48 0>;
         };
 
-Example 2: In this example, the MCT global and local timer interrupts are
-           connected to two separate interrupt controllers. Hence, an
-           interrupt-map is created to map the interrupts to the respective
-           interrupt controllers.
+Example 2: In this example, the timer interrupts are connected to two separate
+           interrupt controllers. Hence, an interrupt-map is created to map
+           the interrupts to the respective interrupt controllers.
 
         mct@101C0000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
-                interrupt-controller;
-                #interrups-cells = <2>;
                 interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
 
                 mct_map: mct-map {
-                        #interrupt-cells = <2>;
+                        #interrupt-cells = <1>;
                         #address-cells = <0>;
                         #size-cells = <0>;
-                        interrupt-map = <0x0 0 &combiner 23 3>,
-                                        <0x4 0 &gic 0 120 0>,
-                                        <0x5 0 &gic 0 121 0>;
+                        interrupt-map = <0 &gic 0 57 0>,
+                                        <1 &gic 0 69 0>,
+                                        <2 &combiner 12 6>,
+                                        <3 &combiner 12 7>,
+                                        <4 &gic 0 42 0>,
+                                        <5 &gic 0 48 0>;
                 };
         };
+
+Example 3: In this example, the IP contains four local timers, but using
+           a per-processor interrupt to handle them. Either all the local
+           timer interrupts can be specified, with the same interrupt specifier
+           value or just the first one.
+
+        mct@10050000 {
+                compatible = "samsung,exynos4412-mct";
+                reg = <0x10050000 0x800>;
+
+                /* Both ways are possible in this case. Either: */
+                interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+                             <0 42 0>;
+                /* or: */
+                interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
+                             <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/keystone-phy.txt b/Documentation/devicetree/bindings/usb/keystone-phy.txt
new file mode 100644
index 000000000000..f37b3a86341d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/keystone-phy.txt
@@ -0,0 +1,20 @@
+TI Keystone USB PHY
+
+Required properties:
+ - compatible: should be "ti,keystone-usbphy".
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+   with 'reg' property.
+ - reg : Address and length of the usb phy control register set.
+
+The main purpose of this PHY driver is to enable the USB PHY reference clock
+gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
+an NOP PHY driver.  Hence this node is referenced as both the usb2 and usb3
+phy node in the USB Glue layer driver node.
+
+usb_phy: usb_phy@2620738 {
+        compatible = "ti,keystone-usbphy";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x2620738 32>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt
new file mode 100644
index 000000000000..60527d335b58
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/keystone-usb.txt
@@ -0,0 +1,42 @@
+TI Keystone Soc USB Controller
+
+DWC3 GLUE
+
+Required properties:
+ - compatible: should be "ti,keystone-dwc3".
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+   with 'reg' property.
+ - reg : Address and length of the register set for the USB subsystem on
+   the SOC.
+ - interrupts : The irq number of this device that is used to interrupt the
+   MPU.
+ - ranges: allows valid 1:1 translation between child's address space and
+   parent's address space.
+ - clocks: Clock IDs array as required by the controller.
+ - clock-names: names of clocks correseponding to IDs in the clock property.
+
+Sub-nodes:
+The dwc3 core should be added as subnode to Keystone DWC3 glue.
+- dwc3 :
+   The binding details of dwc3 can be found in:
+   Documentation/devicetree/bindings/usb/dwc3.txt
+
+Example:
+        usb: usb@2680000 {
+                compatible = "ti,keystone-dwc3";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x2680000 0x10000>;
+                clocks = <&clkusb>;
+                clock-names = "usb";
+                interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                ranges;
+                status = "disabled";
+
+                dwc3@2690000 {
+                        compatible = "synopsys,dwc3";
+                        reg = <0x2690000 0x70000>;
+                        interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+                        usb-phy = <&usb_phy>, <&usb_phy>;
+                };
+        };