1 files changed, 77 insertions, 40 deletions

diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
index f5948c48b9a2..6b1cab17f52d 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -11,8 +11,7 @@ Required properties:
   be 0 or 1, since we have 2 DSI controllers at most for now.
 - interrupts: The interrupt signal from the DSI block.
 - power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clocks: Phandles to device clocks.
 - clock-names: the following clocks are required:
   * "mdp_core_clk"
   * "iface_clk"
@@ -23,16 +22,21 @@ Required properties:
   * "core_clk"
   For DSIv2, we need an additional clock:
    * "src_clk"
+- assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform.
+- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
+  by a DSI PHY block. See [1] for details on clock bindings.
 - vdd-supply: phandle to vdd regulator device node
 - vddio-supply: phandle to vdd-io regulator device node
 - vdda-supply: phandle to vdda regulator device node
-- qcom,dsi-phy: phandle to DSI PHY device node
+- phys: phandle to DSI PHY device node
+- phy-names: the name of the corresponding PHY device
 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
+- ports: Contains 2 DSI controller ports as child nodes. Each port contains
+  an endpoint subnode as defined in [2] and [3].
 
 Optional properties:
 - panel@0: Node of panel connected to this DSI controller.
-  See files in Documentation/devicetree/bindings/display/panel/ for each supported
-  panel.
+  See files in [4] for each supported panel.
 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
   driving a panel which needs 2 DSI links.
 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
@@ -44,34 +48,38 @@ Optional properties:
 - pinctrl-names: the pin control state names; should contain "default"
 - pinctrl-0: the default pinctrl state (active)
 - pinctrl-n: the "sleep" pinctrl state
-- port: DSI controller output port, containing one endpoint subnode.
+- ports: contains DSI controller input and output ports as children, each
+  containing one endpoint subnode.
 
   DSI Endpoint properties:
-  - remote-endpoint: set to phandle of the connected panel's endpoint.
-    See Documentation/devicetree/bindings/graph.txt for device graph info.
-  - qcom,data-lane-map: this describes how the logical DSI lanes are mapped
-    to the physical lanes on the given platform. The value contained in
-    index n describes what logical data lane is mapped to the physical data
-    lane n (DATAn, where n lies between 0 and 3).
+  - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
+    input endpoint. For port@1, set to the MDP interface output. See [2] for
+    device graph info.
+
+  - data-lanes: this describes how the physical DSI data lanes are mapped
+    to the logical lanes on the given platform. The value contained in
+    index n describes what physical lane is mapped to the logical lane n
+    (DATAn, where n lies between 0 and 3). The clock lane position is fixed
+    and can't be changed. Hence, they aren't a part of the DT bindings. See
+    [3] for more info on the data-lanes property.
 
     For example:
 
-    qcom,data-lane-map = <3 0 1 2>;
+    data-lanes = <3 0 1 2>;
 
-    The above mapping describes that the logical data lane DATA3 is mapped to
-    the physical data lane DATA0, logical DATA0 to physical DATA1, logic DATA1
-    to phys DATA2 and logic DATA2 to phys DATA3.
+    The above mapping describes that the logical data lane DATA0 is mapped to
+    the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
+    to phys DATA1 and logic DATA3 to phys DATA2.
 
     There are only a limited number of physical to logical mappings possible:
-
-    "0123": Logic 0->Phys 0; Logic 1->Phys 1; Logic 2->Phys 2; Logic 3->Phys 3;
-    "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
-    "2301": Logic 2->Phys 0; Logic 3->Phys 1; Logic 0->Phys 2; Logic 1->Phys 3;
-    "1230": Logic 1->Phys 0; Logic 2->Phys 1; Logic 3->Phys 2; Logic 0->Phys 3;
-    "0321": Logic 0->Phys 0; Logic 3->Phys 1; Logic 2->Phys 2; Logic 1->Phys 3;
-    "1032": Logic 1->Phys 0; Logic 0->Phys 1; Logic 3->Phys 2; Logic 2->Phys 3;
-    "2103": Logic 2->Phys 0; Logic 1->Phys 1; Logic 0->Phys 2; Logic 3->Phys 3;
-    "3210": Logic 3->Phys 0; Logic 2->Phys 1; Logic 1->Phys 2; Logic 0->Phys 3;
+    <0 1 2 3>
+    <1 2 3 0>
+    <2 3 0 1>
+    <3 0 1 2>
+    <0 3 2 1>
+    <1 0 3 2>
+    <2 1 0 3>
+    <3 2 1 0>
 
 DSI PHY:
 Required properties:
@@ -86,11 +94,12 @@ Required properties:
   * "dsi_pll"
   * "dsi_phy"
   * "dsi_phy_regulator"
+- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
+  2 clocks: A byte clock (index 0), and a pixel clock (index 1).
 - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
   be 0 or 1, since we have 2 DSI PHYs at most for now.
 - power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
+- clocks: Phandles to device clocks. See [1] for details on clock bindings.
 - clock-names: the following clocks are required:
   * "iface_clk"
 - vddio-supply: phandle to vdd-io regulator device node
@@ -99,11 +108,16 @@ Optional properties:
 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
   regulator is wanted.
 
+[1] Documentation/devicetree/bindings/clocks/clock-bindings.txt
+[2] Documentation/devicetree/bindings/graph.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/display/panel/
+
 Example:
-        mdss_dsi0: qcom,mdss_dsi@fd922800 {
+        dsi0: dsi@fd922800 {
                 compatible = "qcom,mdss-dsi-ctrl";
                 qcom,dsi-host-index = <0>;
-                interrupt-parent = <&mdss_mdp>;
+                interrupt-parent = <&mdp>;
                 interrupts = <4 0>;
                 reg-names = "dsi_ctrl";
                 reg = <0xfd922800 0x200>;
@@ -124,19 +138,48 @@ Example:
                         <&mmcc MDSS_AHB_CLK>,
                         <&mmcc MDSS_MDP_CLK>,
                         <&mmcc MDSS_PCLK0_CLK>;
+
+                assigned-clocks =
+                                 <&mmcc BYTE0_CLK_SRC>,
+                                 <&mmcc PCLK0_CLK_SRC>;
+                assigned-clock-parents =
+                                 <&dsi_phy0 0>,
+                                 <&dsi_phy0 1>;
+
                 vdda-supply = <&pma8084_l2>;
                 vdd-supply = <&pma8084_l22>;
                 vddio-supply = <&pma8084_l12>;
 
-                qcom,dsi-phy = <&mdss_dsi_phy0>;
+                phys = <&dsi_phy0>;
+                phy-names ="dsi-phy";
 
                 qcom,dual-dsi-mode;
                 qcom,master-dsi;
                 qcom,sync-dual-dsi;
 
                 pinctrl-names = "default", "sleep";
-                pinctrl-0 = <&mdss_dsi_active>;
-                pinctrl-1 = <&mdss_dsi_suspend>;
+                pinctrl-0 = <&dsi_active>;
+                pinctrl-1 = <&dsi_suspend>;
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                dsi0_in: endpoint {
+                                        remote-endpoint = <&mdp_intf1_out>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                dsi0_out: endpoint {
+                                        remote-endpoint = <&panel_in>;
+                                        data-lanes = <0 1 2 3>;
+                                };
+                        };
+                };
 
                 panel: panel@0 {
                         compatible = "sharp,lq101r1sx01";
@@ -152,16 +195,9 @@ Example:
                                 };
                         };
                 };
-
-                port {
-                        dsi0_out: endpoint {
-                                remote-endpoint = <&panel_in>;
-                                lanes = <0 1 2 3>;
-                        };
-                };
         };
 
-        mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
+        dsi_phy0: dsi-phy@fd922a00 {
                 compatible = "qcom,dsi-phy-28nm-hpm";
                 qcom,dsi-phy-index = <0>;
                 reg-names =
@@ -173,6 +209,7 @@ Example:
                         <0xfd922d80 0x7b>;
                 clock-names = "iface_clk";
                 clocks = <&mmcc MDSS_AHB_CLK>;
+                #clock-cells = <1>;
                 vddio-supply = <&pma8084_l12>;
 
                 qcom,dsi-phy-regulator-ldo-mode;