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diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
new file mode 100644
index 000000000000..7337005ef5e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -0,0 +1,119 @@
+* Gated Clock bindings for Marvell Orion SoCs
+Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
+some power. The clock consumer should specify the desired clock by having
+the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
+the corresponding clock gating control bit in HW to ease manual clock lookup
+in datasheet.
+The following is a list of provided IDs for Armada 370:
+ID      Clock   Peripheral
+-----------------------------------
+0       Audio   AC97 Cntrl
+1       pex0_en PCIe 0 Clock out
+2       pex1_en PCIe 1 Clock out
+3       ge1     Gigabit Ethernet 1
+4       ge0     Gigabit Ethernet 0
+5       pex0    PCIe Cntrl 0
+9       pex1    PCIe Cntrl 1
+15      sata0   SATA Host 0
+17      sdio    SDHCI Host
+25      tdm     Time Division Mplx
+28      ddr     DDR Cntrl
+30      sata1   SATA Host 0
+The following is a list of provided IDs for Armada XP:
+ID      Clock   Peripheral
+-----------------------------------
+0       audio   Audio Cntrl
+1       ge3     Gigabit Ethernet 3
+2       ge2     Gigabit Ethernet 2
+3       ge1     Gigabit Ethernet 1
+4       ge0     Gigabit Ethernet 0
+5       pex0    PCIe Cntrl 0
+6       pex1    PCIe Cntrl 1
+7       pex2    PCIe Cntrl 2
+8       pex3    PCIe Cntrl 3
+13      bp
+14      sata0lnk
+15      sata0   SATA Host 0
+16      lcd     LCD Cntrl
+17      sdio    SDHCI Host
+18      usb0    USB Host 0
+19      usb1    USB Host 1
+20      usb2    USB Host 2
+22      xor0    XOR DMA 0
+23      crypto  CESA engine
+25      tdm     Time Division Mplx
+28      xor1    XOR DMA 1
+29      sata1lnk
+30      sata1   SATA Host 0
+The following is a list of provided IDs for Dove:
+ID      Clock   Peripheral
+-----------------------------------
+0       usb0    USB Host 0
+1       usb1    USB Host 1
+2       ge      Gigabit Ethernet
+3       sata    SATA Host
+4       pex0    PCIe Cntrl 0
+5       pex1    PCIe Cntrl 1
+8       sdio0   SDHCI Host 0
+9       sdio1   SDHCI Host 1
+10      nand    NAND Cntrl
+11      camera  Camera Cntrl
+12      i2s0    I2S Cntrl 0
+13      i2s1    I2S Cntrl 1
+15      crypto  CESA engine
+21      ac97    AC97 Cntrl
+22      pdma    Peripheral DMA
+23      xor0    XOR DMA 0
+24      xor1    XOR DMA 1
+30      gephy   Gigabit Ethernel PHY
+Note: gephy(30) is implemented as a parent clock of ge(2)
+The following is a list of provided IDs for Kirkwood:
+ID      Clock   Peripheral
+-----------------------------------
+0       ge0     Gigabit Ethernet 0
+2       pex0    PCIe Cntrl 0
+3       usb0    USB Host 0
+4       sdio    SDIO Cntrl
+5       tsu     Transp. Stream Unit
+6       dunit   SDRAM Cntrl
+7       runit   Runit
+8       xor0    XOR DMA 0
+9       audio   I2S Cntrl 0
+14      sata0   SATA Host 0
+15      sata1   SATA Host 1
+16      xor1    XOR DMA 1
+17      crypto  CESA engine
+18      pex1    PCIe Cntrl 1
+19      ge1     Gigabit Ethernet 0
+20      tdm     Time Division Mplx
+Required properties:
+- compatible : shall be one of the following:
+        "marvell,dove-gating-clock" - for Dove SoC clock gating
+        "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
+- reg : shall be the register address of the Clock Gating Control register
+- #clock-cells : from common clock binding; shall be set to 1
+Optional properties:
+- clocks : default parent clock phandle (e.g. tclk)
+Example:
+gate_clk: clock-gating-control@d0038 {
+        compatible = "marvell,dove-gating-clock";
+        reg = <0xd0038 0x4>;
+        /* default parent clock is tclk */
+        clocks = <&core_clk 0>;
+        #clock-cells = <1>;
+};
+sdio0: sdio@92000 {
+        compatible = "marvell,dove-sdhci";
+        /* get clk gate bit 8 (sdio0) */
+        clocks = <&gate_clk 8>;
+};

diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt new file mode 100644 index 000000000000..7337005ef5e1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -0,0 +1,119 @@
	1	* Gated Clock bindings for Marvell Orion SoCs
	2
	3	Marvell Dove and Kirkwood allow some peripheral clocks to be gated to save
	4	some power. The clock consumer should specify the desired clock by having
	5	the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
	6	the corresponding clock gating control bit in HW to ease manual clock lookup
	7	in datasheet.
	8
	9	The following is a list of provided IDs for Armada 370:
	10	ID Clock Peripheral
	11	-----------------------------------
	12	0 Audio AC97 Cntrl
	13	1 pex0_en PCIe 0 Clock out
	14	2 pex1_en PCIe 1 Clock out
	15	3 ge1 Gigabit Ethernet 1
	16	4 ge0 Gigabit Ethernet 0
	17	5 pex0 PCIe Cntrl 0
	18	9 pex1 PCIe Cntrl 1
	19	15 sata0 SATA Host 0
	20	17 sdio SDHCI Host
	21	25 tdm Time Division Mplx
	22	28 ddr DDR Cntrl
	23	30 sata1 SATA Host 0
	24
	25	The following is a list of provided IDs for Armada XP:
	26	ID Clock Peripheral
	27	-----------------------------------
	28	0 audio Audio Cntrl
	29	1 ge3 Gigabit Ethernet 3
	30	2 ge2 Gigabit Ethernet 2
	31	3 ge1 Gigabit Ethernet 1
	32	4 ge0 Gigabit Ethernet 0
	33	5 pex0 PCIe Cntrl 0
	34	6 pex1 PCIe Cntrl 1
	35	7 pex2 PCIe Cntrl 2
	36	8 pex3 PCIe Cntrl 3
	37	13 bp
	38	14 sata0lnk
	39	15 sata0 SATA Host 0
	40	16 lcd LCD Cntrl
	41	17 sdio SDHCI Host
	42	18 usb0 USB Host 0
	43	19 usb1 USB Host 1
	44	20 usb2 USB Host 2
	45	22 xor0 XOR DMA 0
	46	23 crypto CESA engine
	47	25 tdm Time Division Mplx
	48	28 xor1 XOR DMA 1
	49	29 sata1lnk
	50	30 sata1 SATA Host 0
	51
	52	The following is a list of provided IDs for Dove:
	53	ID Clock Peripheral
	54	-----------------------------------
	55	0 usb0 USB Host 0
	56	1 usb1 USB Host 1
	57	2 ge Gigabit Ethernet
	58	3 sata SATA Host
	59	4 pex0 PCIe Cntrl 0
	60	5 pex1 PCIe Cntrl 1
	61	8 sdio0 SDHCI Host 0
	62	9 sdio1 SDHCI Host 1
	63	10 nand NAND Cntrl
	64	11 camera Camera Cntrl
	65	12 i2s0 I2S Cntrl 0
	66	13 i2s1 I2S Cntrl 1
	67	15 crypto CESA engine
	68	21 ac97 AC97 Cntrl
	69	22 pdma Peripheral DMA
	70	23 xor0 XOR DMA 0
	71	24 xor1 XOR DMA 1
	72	30 gephy Gigabit Ethernel PHY
	73	Note: gephy(30) is implemented as a parent clock of ge(2)
	74
	75	The following is a list of provided IDs for Kirkwood:
	76	ID Clock Peripheral
	77	-----------------------------------
	78	0 ge0 Gigabit Ethernet 0
	79	2 pex0 PCIe Cntrl 0
	80	3 usb0 USB Host 0
	81	4 sdio SDIO Cntrl
	82	5 tsu Transp. Stream Unit
	83	6 dunit SDRAM Cntrl
	84	7 runit Runit
	85	8 xor0 XOR DMA 0
	86	9 audio I2S Cntrl 0
	87	14 sata0 SATA Host 0
	88	15 sata1 SATA Host 1
	89	16 xor1 XOR DMA 1
	90	17 crypto CESA engine
	91	18 pex1 PCIe Cntrl 1
	92	19 ge1 Gigabit Ethernet 0
	93	20 tdm Time Division Mplx
	94
	95	Required properties:
	96	- compatible : shall be one of the following:
	97	"marvell,dove-gating-clock" - for Dove SoC clock gating
	98	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
	99	- reg : shall be the register address of the Clock Gating Control register
	100	- #clock-cells : from common clock binding; shall be set to 1
	101
	102	Optional properties:
	103	- clocks : default parent clock phandle (e.g. tclk)
	104
	105	Example:
	106
	107	gate_clk: clock-gating-control@d0038 {
	108	compatible = "marvell,dove-gating-clock";
	109	reg = <0xd0038 0x4>;
	110	/* default parent clock is tclk */
	111	clocks = <&core_clk 0>;
	112	#clock-cells = <1>;
	113	};
	114
	115	sdio0: sdio@92000 {
	116	compatible = "marvell,dove-sdhci";
	117	/* get clk gate bit 8 (sdio0) */
	118	clocks = <&gate_clk 8>;
	119	};