18 files changed, 457 insertions, 77 deletions

diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 85a0633c1eac..8504d9c6f03a 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -10,6 +10,7 @@ lib-$(CONFIG_SUNXI_CCU)		+= ccu_gate.o
 lib-$(CONFIG_SUNXI_CCU)         += ccu_mux.o
 lib-$(CONFIG_SUNXI_CCU)         += ccu_mult.o
 lib-$(CONFIG_SUNXI_CCU)         += ccu_phase.o
+lib-$(CONFIG_SUNXI_CCU)         += ccu_sdm.o
 
 # Multi-factor clocks
 lib-$(CONFIG_SUNXI_CCU)         += ccu_nk.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 286b0049b7b6..ffa5dac221e4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -28,6 +28,7 @@
 #include "ccu_nkmp.h"
 #include "ccu_nm.h"
 #include "ccu_phase.h"
+#include "ccu_sdm.h"
 
 #include "ccu-sun4i-a10.h"
 
@@ -51,16 +52,29 @@ static struct ccu_nkmp pll_core_clk = {
  * the base (2x, 4x and 8x), and one variable divider (the one true
  * pll audio).
  *
- * We don't have any need for the variable divider for now, so we just
- * hardcode it to match with the clock names.
+ * With sigma-delta modulation for fractional-N on the audio PLL,
+ * we have to use specific dividers. This means the variable divider
+ * can no longer be used, as the audio codec requests the exact clock
+ * rates we support through this mechanism. So we now hard code the
+ * variable divider to 1. This means the clock rates will no longer
+ * match the clock names.
  */
 #define SUN4I_PLL_AUDIO_REG     0x008
+
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+        { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+        { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
+};
+
 static struct ccu_nm pll_audio_base_clk = {
         .enable         = BIT(31),
         .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
         .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+        .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
+                                         0x00c, BIT(31)),
         .common         = {
                 .reg            = 0x008,
+                .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
                 .hw.init        = CLK_HW_INIT("pll-audio-base",
                                               "hosc",
                                               &ccu_nm_ops,
@@ -223,7 +237,7 @@ static struct ccu_mux cpu_clk = {
                 .hw.init        = CLK_HW_INIT_PARENTS("cpu",
                                                       cpu_parents,
                                                       &ccu_mux_ops,
-                                                      CLK_IS_CRITICAL),
+                                                      CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
         }
 };
 
@@ -1021,9 +1035,9 @@ static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
         &out_b_clk.common
 };
 
-/* Post-divider for pll-audio is hardcoded to 4 */
+/* Post-divider for pll-audio is hardcoded to 1 */
 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
-                        "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
+                        "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -1420,10 +1434,10 @@ static void __init sun4i_ccu_init(struct device_node *node,
                 return;
         }
 
-        /* Force the PLL-Audio-1x divider to 4 */
+        /* Force the PLL-Audio-1x divider to 1 */
         val = readl(reg + SUN4I_PLL_AUDIO_REG);
         val &= ~GENMASK(29, 26);
-        writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG);
+        writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
 
         /*
          * Use the peripheral PLL6 as the AHB parent, instead of CPU /
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
index c5947c7c050e..23c908ad509f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
@@ -29,7 +29,7 @@
 #define CLK_PLL_AUDIO_4X        6
 #define CLK_PLL_AUDIO_8X        7
 #define CLK_PLL_VIDEO0          8
-#define CLK_PLL_VIDEO0_2X       9
+/* The PLL_VIDEO0_2X clock is exported */
 #define CLK_PLL_VE              10
 #define CLK_PLL_DDR_BASE        11
 #define CLK_PLL_DDR             12
@@ -38,7 +38,7 @@
 #define CLK_PLL_PERIPH          15
 #define CLK_PLL_PERIPH_SATA     16
 #define CLK_PLL_VIDEO1          17
-#define CLK_PLL_VIDEO1_2X       18
+/* The PLL_VIDEO1_2X clock is exported */
 #define CLK_PLL_GPU             19
 
 /* The CPU clock is exported */
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index ab9e850b3707..fa2c2dd77102 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -26,6 +26,7 @@
 #include "ccu_nkmp.h"
 #include "ccu_nm.h"
 #include "ccu_phase.h"
+#include "ccu_sdm.h"
 
 #include "ccu-sun5i.h"
 
@@ -49,11 +50,20 @@ static struct ccu_nkmp pll_core_clk = {
  * the base (2x, 4x and 8x), and one variable divider (the one true
  * pll audio).
  *
- * We don't have any need for the variable divider for now, so we just
- * hardcode it to match with the clock names
+ * With sigma-delta modulation for fractional-N on the audio PLL,
+ * we have to use specific dividers. This means the variable divider
+ * can no longer be used, as the audio codec requests the exact clock
+ * rates we support through this mechanism. So we now hard code the
+ * variable divider to 1. This means the clock rates will no longer
+ * match the clock names.
  */
 #define SUN5I_PLL_AUDIO_REG     0x008
 
+static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+        { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+        { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
+};
+
 static struct ccu_nm pll_audio_base_clk = {
         .enable         = BIT(31),
         .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
@@ -63,8 +73,11 @@ static struct ccu_nm pll_audio_base_clk = {
          * offset
          */
         .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+        .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
+                                         0x00c, BIT(31)),