diff options
| -rw-r--r-- | drivers/pci/host/pci-aardvark.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-aardvark.c b/drivers/pci/host/pci-aardvark.c index 7a0ddb709052..9abf549631b4 100644 --- a/drivers/pci/host/pci-aardvark.c +++ b/drivers/pci/host/pci-aardvark.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 | 29 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 |
| 30 | #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) | 30 | #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) |
| 31 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 | 31 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 |
| 32 | #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 | ||
| 32 | #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 | 33 | #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 |
| 33 | #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) | 34 | #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) |
| 34 | #define PCIE_CORE_LINK_TRAINING BIT(5) | 35 | #define PCIE_CORE_LINK_TRAINING BIT(5) |
| @@ -295,7 +296,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) | |||
| 295 | reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | | 296 | reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | |
| 296 | (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | | 297 | (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | |
| 297 | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | | 298 | PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | |
| 298 | PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT; | 299 | (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << |
| 300 | PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); | ||
| 299 | advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); | 301 | advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); |
| 300 | 302 | ||
| 301 | /* Program PCIe Control 2 to disable strict ordering */ | 303 | /* Program PCIe Control 2 to disable strict ordering */ |