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-rw-r--r--Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt266
-rw-r--r--sound/soc/codecs/max98927.c1
-rw-r--r--sound/soc/codecs/mc13783.c9
-rw-r--r--sound/soc/codecs/msm8916-wcd-analog.c8
-rw-r--r--sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c552
-rw-r--r--sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h15
-rw-r--r--sound/soc/mediatek/mt2701/mt2701-afe-common.h87
-rw-r--r--sound/soc/mediatek/mt2701/mt2701-afe-pcm.c182
-rw-r--r--sound/soc/mediatek/mt2701/mt2701-reg.h42
-rw-r--r--sound/soc/mediatek/mt8173/mt8173-afe-pcm.c6
-rw-r--r--sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c2
-rw-r--r--sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c2
-rw-r--r--sound/soc/mediatek/mt8173/mt8173-rt5650.c2
13 files changed, 406 insertions, 768 deletions
diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
index 77a57f84bed4..6df87b97f7cb 100644
--- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
+++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
@@ -2,153 +2,143 @@ Mediatek AFE PCM controller for mt2701
2 2
3Required properties: 3Required properties:
4- compatible = "mediatek,mt2701-audio"; 4- compatible = "mediatek,mt2701-audio";
5- reg: register location and size
6- interrupts: should contain AFE and ASYS interrupts 5- interrupts: should contain AFE and ASYS interrupts
7- interrupt-names: should be "afe" and "asys" 6- interrupt-names: should be "afe" and "asys"
8- power-domains: should define the power domain 7- power-domains: should define the power domain
8- clocks: Must contain an entry for each entry in clock-names
9 See ../clocks/clock-bindings.txt for details
9- clock-names: should have these clock names: 10- clock-names: should have these clock names:
10 "infra_sys_audio_clk", 11 "infra_sys_audio_clk",
11 "top_audio_mux1_sel", 12 "top_audio_mux1_sel",
12 "top_audio_mux2_sel", 13 "top_audio_mux2_sel",
13 "top_audio_mux1_div", 14 "top_audio_a1sys_hp",
14 "top_audio_mux2_div", 15 "top_audio_a2sys_hp",
15 "top_audio_48k_timing", 16 "i2s0_src_sel",
16 "top_audio_44k_timing", 17 "i2s1_src_sel",
17 "top_audpll_mux_sel", 18 "i2s2_src_sel",
18 "top_apll_sel", 19 "i2s3_src_sel",
19 "top_aud1_pll_98M", 20 "i2s0_src_div",
20 "top_aud2_pll_90M", 21 "i2s1_src_div",
21 "top_hadds2_pll_98M", 22 "i2s2_src_div",
22 "top_hadds2_pll_294M", 23 "i2s3_src_div",
23 "top_audpll", 24 "i2s0_mclk_en",
24 "top_audpll_d4", 25 "i2s1_mclk_en",
25 "top_audpll_d8", 26 "i2s2_mclk_en",
26 "top_audpll_d16", 27 "i2s3_mclk_en",
27 "top_audpll_d24", 28 "i2so0_hop_ck",
28 "top_audintbus_sel", 29 "i2so1_hop_ck",
29 "clk_26m", 30 "i2so2_hop_ck",
30 "top_syspll1_d4", 31 "i2so3_hop_ck",
31 "top_aud_k1_src_sel", 32 "i2si0_hop_ck",
32 "top_aud_k2_src_sel", 33 "i2si1_hop_ck",
33 "top_aud_k3_src_sel", 34 "i2si2_hop_ck",
34 "top_aud_k4_src_sel", 35 "i2si3_hop_ck",
35 "top_aud_k5_src_sel", 36 "asrc0_out_ck",
36 "top_aud_k6_src_sel", 37 "asrc1_out_ck",
37 "top_aud_k1_src_div", 38 "asrc2_out_ck",
38 "top_aud_k2_src_div", 39 "asrc3_out_ck",
39 "top_aud_k3_src_div", 40 "audio_afe_pd",
40 "top_aud_k4_src_div", 41 "audio_afe_conn_pd",
41 "top_aud_k5_src_div", 42 "audio_a1sys_pd",
42 "top_aud_k6_src_div", 43 "audio_a2sys_pd",
43 "top_aud_i2s1_mclk", 44 "audio_mrgif_pd";
44 "top_aud_i2s2_mclk", 45- assigned-clocks: list of input clocks and dividers for the audio system.
45 "top_aud_i2s3_mclk", 46 See ../clocks/clock-bindings.txt for details.
46 "top_aud_i2s4_mclk", 47- assigned-clocks-parents: parent of input clocks of assigned clocks.
47 "top_aud_i2s5_mclk", 48- assigned-clock-rates: list of clock frequencies of assigned clocks.
48 "top_aud_i2s6_mclk", 49
49 "top_asm_m_sel", 50Must be a subnode of MediaTek audsys device tree node.
50 "top_asm_h_sel", 51See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
51 "top_univpll2_d4",
52 "top_univpll2_d2",
53 "top_syspll_d5";
54 52
55Example: 53Example:
56 54
57 afe: mt2701-afe-pcm@11220000 { 55 audsys: audio-subsystem@11220000 {
58 compatible = "mediatek,mt2701-audio"; 56 compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
59 reg = <0 0x11220000 0 0x2000>, 57 ...
60 <0 0x112A0000 0 0x20000>; 58
61 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 59 afe: audio-controller {
62 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 60 compatible = "mediatek,mt2701-audio";
63 interrupt-names = "afe", "asys"; 61 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
64 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 62 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
65 clocks = <&infracfg CLK_INFRA_AUDIO>, 63 interrupt-names = "afe", "asys";
66 <&topckgen CLK_TOP_AUD_MUX1_SEL>, 64 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
67 <&topckgen CLK_TOP_AUD_MUX2_SEL>, 65
68 <&topckgen CLK_TOP_AUD_MUX1_DIV>, 66 clocks = <&infracfg CLK_INFRA_AUDIO>,
69 <&topckgen CLK_TOP_AUD_MUX2_DIV>, 67 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_48K_TIMING>, 68 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_44K_TIMING>, 69 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>, 70 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_APLL_SEL>, 71 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD1PLL_98M>, 72 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD2PLL_90M>, 73 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_HADDS2PLL_98M>, 74 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_HADDS2PLL_294M>, 75 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUDPLL>, 76 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
79 <&topckgen CLK_TOP_AUDPLL_D4>, 77 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
80 <&topckgen CLK_TOP_AUDPLL_D8>, 78 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
81 <&topckgen CLK_TOP_AUDPLL_D16>, 79 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
82 <&topckgen CLK_TOP_AUDPLL_D24>, 80 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
83 <&topckgen CLK_TOP_AUDINTBUS_SEL>, 81 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
84 <&clk26m>, 82 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
85 <&topckgen CLK_TOP_SYSPLL1_D4>, 83 <&audsys CLK_AUD_I2SO1>,
86 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, 84 <&audsys CLK_AUD_I2SO2>,
87 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, 85 <&audsys CLK_AUD_I2SO3>,
88 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, 86 <&audsys CLK_AUD_I2SO4>,
89 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, 87 <&audsys CLK_AUD_I2SIN1>,
90 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>, 88 <&audsys CLK_AUD_I2SIN2>,
91 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>, 89 <&audsys CLK_AUD_I2SIN3>,
92 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, 90 <&audsys CLK_AUD_I2SIN4>,
93 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, 91 <&audsys CLK_AUD_ASRCO1>,
94 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, 92 <&audsys CLK_AUD_ASRCO2>,
95 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, 93 <&audsys CLK_AUD_ASRCO3>,
96 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>, 94 <&audsys CLK_AUD_ASRCO4>,
97 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>, 95 <&audsys CLK_AUD_AFE>,
98 <&topckgen CLK_TOP_AUD_I2S1_MCLK>, 96 <&audsys CLK_AUD_AFE_CONN>,
99 <&topckgen CLK_TOP_AUD_I2S2_MCLK>, 97 <&audsys CLK_AUD_A1SYS>,
100 <&topckgen CLK_TOP_AUD_I2S3_MCLK>, 98 <&audsys CLK_AUD_A2SYS>,
101 <&topckgen CLK_TOP_AUD_I2S4_MCLK>, 99 <&audsys CLK_AUD_AFE_MRGIF>;
102 <&topckgen CLK_TOP_AUD_I2S5_MCLK>, 100
103 <&topckgen CLK_TOP_AUD_I2S6_MCLK>, 101 clock-names = "infra_sys_audio_clk",
104 <&topckgen CLK_TOP_ASM_M_SEL>, 102 "top_audio_mux1_sel",
105 <&topckgen CLK_TOP_ASM_H_SEL>, 103 "top_audio_mux2_sel",
106 <&topckgen CLK_TOP_UNIVPLL2_D4>, 104 "top_audio_a1sys_hp",
107 <&topckgen CLK_TOP_UNIVPLL2_D2>, 105 "top_audio_a2sys_hp",
108 <&topckgen CLK_TOP_SYSPLL_D5>; 106 "i2s0_src_sel",
107 "i2s1_src_sel",
108 "i2s2_src_sel",
109 "i2s3_src_sel",
110 "i2s0_src_div",
111 "i2s1_src_div",
112 "i2s2_src_div",
113 "i2s3_src_div",
114 "i2s0_mclk_en",
115 "i2s1_mclk_en",
116 "i2s2_mclk_en",
117 "i2s3_mclk_en",
118 "i2so0_hop_ck",
119 "i2so1_hop_ck",
120 "i2so2_hop_ck",
121 "i2so3_hop_ck",
122 "i2si0_hop_ck",
123 "i2si1_hop_ck",
124 "i2si2_hop_ck",
125 "i2si3_hop_ck",
126 "asrc0_out_ck",
127 "asrc1_out_ck",
128 "asrc2_out_ck",
129 "asrc3_out_ck",
130 "audio_afe_pd",
131 "audio_afe_conn_pd",
132 "audio_a1sys_pd",
133 "audio_a2sys_pd",
134 "audio_mrgif_pd";
109 135
110 clock-names = "infra_sys_audio_clk", 136 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
111 "top_audio_mux1_sel", 137 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
112 "top_audio_mux2_sel", 138 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
113 "top_audio_mux1_div", 139 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
114 "top_audio_mux2_div", 140 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
115 "top_audio_48k_timing", 141 <&topckgen CLK_TOP_AUD2PLL_90M>;
116 "top_audio_44k_timing", 142 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
117 "top_audpll_mux_sel", 143 };
118 "top_apll_sel",
119 "top_aud1_pll_98M",
120 "top_aud2_pll_90M",
121 "top_hadds2_pll_98M",
122 "top_hadds2_pll_294M",
123 "top_audpll",
124 "top_audpll_d4",
125 "top_audpll_d8",
126 "top_audpll_d16",
127 "top_audpll_d24",
128 "top_audintbus_sel",
129 "clk_26m",
130 "top_syspll1_d4",
131 "top_aud_k1_src_sel",
132 "top_aud_k2_src_sel",
133 "top_aud_k3_src_sel",
134 "top_aud_k4_src_sel",
135 "top_aud_k5_src_sel",
136 "top_aud_k6_src_sel",
137 "top_aud_k1_src_div",
138 "top_aud_k2_src_div",
139 "top_aud_k3_src_div",
140 "top_aud_k4_src_div",
141 "top_aud_k5_src_div",
142 "top_aud_k6_src_div",
143 "top_aud_i2s1_mclk",
144 "top_aud_i2s2_mclk",
145 "top_aud_i2s3_mclk",
146 "top_aud_i2s4_mclk",
147 "top_aud_i2s5_mclk",
148 "top_aud_i2s6_mclk",
149 "top_asm_m_sel",
150 "top_asm_h_sel",
151 "top_univpll2_d4",
152 "top_univpll2_d2",
153 "top_syspll_d5";
154 }; 144 };
diff --git a/sound/soc/codecs/max98927.c b/sound/soc/codecs/max98927.c
index a1d39353719d..f701fdc81175 100644
--- a/sound/soc/codecs/max98927.c
+++ b/sound/soc/codecs/max98927.c
@@ -682,7 +682,6 @@ static int max98927_probe(struct snd_soc_codec *codec)
682 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); 682 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
683 683
684 max98927->codec = codec; 684 max98927->codec = codec;
685 codec->control_data = max98927->regmap;
686 685
687 /* Software Reset */ 686 /* Software Reset */
688 regmap_write(max98927->regmap, 687 regmap_write(max98927->regmap,
diff --git a/sound/soc/codecs/mc13783.c b/sound/soc/codecs/mc13783.c
index 4fd8d1dc4eef..be7a45f05bbf 100644
--- a/sound/soc/codecs/mc13783.c
+++ b/sound/soc/codecs/mc13783.c
@@ -610,6 +610,9 @@ static int mc13783_probe(struct snd_soc_codec *codec)
610{ 610{
611 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec); 611 struct mc13783_priv *priv = snd_soc_codec_get_drvdata(codec);
612 612
613 snd_soc_codec_init_regmap(codec,
614 dev_get_regmap(codec->dev->parent, NULL));
615
613 /* these are the reset values */ 616 /* these are the reset values */
614 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893); 617 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX0, 0x25893);
615 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A); 618 mc13xxx_reg_write(priv->mc13xxx, MC13783_AUDIO_RX1, 0x00d35A);
@@ -728,15 +731,9 @@ static struct snd_soc_dai_driver mc13783_dai_sync[] = {
728 } 731 }
729}; 732};
730 733
731static struct regmap *mc13783_get_regmap(struct device *dev)
732{
733 return dev_get_regmap(dev->parent, NULL);
734}
735
736static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = { 734static const struct snd_soc_codec_driver soc_codec_dev_mc13783 = {
737 .probe = mc13783_probe, 735 .probe = mc13783_probe,
738 .remove = mc13783_remove, 736 .remove = mc13783_remove,
739 .get_regmap = mc13783_get_regmap,
740 .component_driver = { 737 .component_driver = {
741 .controls = mc13783_control_list, 738 .controls = mc13783_control_list,
742 .num_controls = ARRAY_SIZE(mc13783_control_list), 739 .num_controls = ARRAY_SIZE(mc13783_control_list),
diff --git a/sound/soc/codecs/msm8916-wcd-analog.c b/sound/soc/codecs/msm8916-wcd-analog.c
index 066ea2f4ce7b..44062bb7bf2f 100644
--- a/sound/soc/codecs/msm8916-wcd-analog.c
+++ b/sound/soc/codecs/msm8916-wcd-analog.c
@@ -712,6 +712,8 @@ static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec)
712 return err; 712 return err;
713 } 713 }
714 714
715 snd_soc_codec_init_regmap(codec,
716 dev_get_regmap(codec->dev->parent, NULL));
715 snd_soc_codec_set_drvdata(codec, priv); 717 snd_soc_codec_set_drvdata(codec, priv);
716 priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1); 718 priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1);
717 priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE); 719 priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE);
@@ -943,11 +945,6 @@ static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec,
943 return 0; 945 return 0;
944} 946}
945 947
946static struct regmap *pm8916_get_regmap(struct device *dev)
947{
948 return dev_get_regmap(dev->parent, NULL);
949}
950
951static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) 948static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg)
952{ 949{
953 struct pm8916_wcd_analog_priv *priv = arg; 950 struct pm8916_wcd_analog_priv *priv = arg;
@@ -1082,7 +1079,6 @@ static const struct snd_soc_codec_driver pm8916_wcd_analog = {
1082 .probe = pm8916_wcd_analog_probe, 1079 .probe = pm8916_wcd_analog_probe,
1083 .remove = pm8916_wcd_analog_remove, 1080 .remove = pm8916_wcd_analog_remove,
1084 .set_jack = pm8916_wcd_analog_set_jack, 1081 .set_jack = pm8916_wcd_analog_set_jack,
1085 .get_regmap = pm8916_get_regmap,
1086 .component_driver = { 1082 .component_driver = {
1087 .controls = pm8916_wcd_analog_snd_controls, 1083 .controls = pm8916_wcd_analog_snd_controls,
1088 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), 1084 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls),
diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
index affa7fb25dd9..949fc3a1d025 100644
--- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.c
@@ -14,451 +14,285 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <sound/soc.h>
18#include <linux/regmap.h>
19#include <linux/pm_runtime.h>
20
21#include "mt2701-afe-common.h" 17#include "mt2701-afe-common.h"
22#include "mt2701-afe-clock-ctrl.h" 18#include "mt2701-afe-clock-ctrl.h"
23 19
24static const char *aud_clks[MT2701_CLOCK_NUM] = { 20static const char *const base_clks[] = {
25 [MT2701_AUD_INFRA_SYS_AUDIO] = "infra_sys_audio_clk", 21 [MT2701_INFRA_SYS_AUDIO] = "infra_sys_audio_clk",
26 [MT2701_AUD_AUD_MUX1_SEL] = "top_audio_mux1_sel", 22 [MT2701_TOP_AUD_MCLK_SRC0] = "top_audio_mux1_sel",
27 [MT2701_AUD_AUD_MUX2_SEL] = "top_audio_mux2_sel", 23 [MT2701_TOP_AUD_MCLK_SRC1] = "top_audio_mux2_sel",
28 [MT2701_AUD_AUD_MUX1_DIV] = "top_audio_mux1_div", 24 [MT2701_TOP_AUD_A1SYS] = "top_audio_a1sys_hp",
29 [MT2701_AUD_AUD_MUX2_DIV] = "top_audio_mux2_div", 25 [MT2701_TOP_AUD_A2SYS] = "top_audio_a2sys_hp",
30 [MT2701_AUD_AUD_48K_TIMING] = "top_audio_48k_timing", 26 [MT2701_AUDSYS_AFE] = "audio_afe_pd",
31 [MT2701_AUD_AUD_44K_TIMING] = "top_audio_44k_timing", 27 [MT2701_AUDSYS_AFE_CONN] = "audio_afe_conn_pd",
32 [MT2701_AUD_AUDPLL_MUX_SEL] = "top_audpll_mux_sel", 28 [MT2701_AUDSYS_A1SYS] = "audio_a1sys_pd",
33 [MT2701_AUD_APLL_SEL] = "top_apll_sel", 29 [MT2701_AUDSYS_A2SYS] = "audio_a2sys_pd",
34 [MT2701_AUD_AUD1PLL_98M] = "top_aud1_pll_98M",
35 [MT2701_AUD_AUD2PLL_90M] = "top_aud2_pll_90M",
36 [MT2701_AUD_HADDS2PLL_98M] = "top_hadds2_pll_98M",
37 [MT2701_AUD_HADDS2PLL_294M] = "top_hadds2_pll_294M",
38 [MT2701_AUD_AUDPLL] = "top_audpll",
39 [MT2701_AUD_AUDPLL_D4] = "top_audpll_d4",
40 [MT2701_AUD_AUDPLL_D8] = "top_audpll_d8",
41 [MT2701_AUD_AUDPLL_D16] = "top_audpll_d16",
42 [MT2701_AUD_AUDPLL_D24] = "top_audpll_d24",
43 [MT2701_AUD_AUDINTBUS] = "top_audintbus_sel",
44 [MT2701_AUD_CLK_26M] = "clk_26m",
45 [MT2701_AUD_SYSPLL1_D4] = "top_syspll1_d4",
46 [MT2701_AUD_AUD_K1_SRC_SEL] = "top_aud_k1_src_sel",
47 [MT2701_AUD_AUD_K2_SRC_SEL] = "top_aud_k2_src_sel",
48 [MT2701_AUD_AUD_K3_SRC_SEL] = "top_aud_k3_src_sel",
49 [MT2701_AUD_AUD_K4_SRC_SEL] = "top_aud_k4_src_sel",
50 [MT2701_AUD_AUD_K5_SRC_SEL] = "top_aud_k5_src_sel",
51 [MT2701_AUD_AUD_K6_SRC_SEL] = "top_aud_k6_src_sel",
52 [MT2701_AUD_AUD_K1_SRC_DIV] = "top_aud_k1_src_div",
53 [MT2701_AUD_AUD_K2_SRC_DIV] = "top_aud_k2_src_div",
54 [MT2701_AUD_AUD_K3_SRC_DIV] = "top_aud_k3_src_div",
55 [MT2701_AUD_AUD_K4_SRC_DIV] = "top_aud_k4_src_div",
56 [MT2701_AUD_AUD_K5_SRC_DIV] = "top_aud_k5_src_div",
57 [MT2701_AUD_AUD_K6_SRC_DIV] = "top_aud_k6_src_div",
58 [MT2701_AUD_AUD_I2S1_MCLK] = "top_aud_i2s1_mclk",
59 [MT2701_AUD_AUD_I2S2_MCLK] = "top_aud_i2s2_mclk",
60 [MT2701_AUD_AUD_I2S3_MCLK] = "top_aud_i2s3_mclk",
61 [MT2701_AUD_AUD_I2S4_MCLK] = "top_aud_i2s4_mclk",
62 [MT2701_AUD_AUD_I2S5_MCLK] = "top_aud_i2s5_mclk",
63 [MT2701_AUD_AUD_I2S6_MCLK] = "top_aud_i2s6_mclk",
64 [MT2701_AUD_ASM_M_SEL] = "top_asm_m_sel",
65 [MT2701_AUD_ASM_H_SEL] = "top_asm_h_sel",
66 [MT2701_AUD_UNIVPLL2_D4] = "top_univpll2_d4",
67 [MT2701_AUD_UNIVPLL2_D2] = "top_univpll2_d2",
68 [MT2701_AUD_SYSPLL_D5] = "top_syspll_d5",
69}; 30};
70 31
71int mt2701_init_clock(struct mtk_base_afe *afe) 32int mt2701_init_clock(struct mtk_base_afe *afe)
72{ 33{
73 struct mt2701_afe_private *afe_priv = afe->platform_priv; 34 struct mt2701_afe_private *afe_priv = afe->platform_priv;
74 int i = 0; 35 int i;
75 36
76 for (i = 0; i < MT2701_CLOCK_NUM; i++) { 37 for (i = 0; i < MT2701_BASE_CLK_NUM; i++) {
77 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); 38 afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
78 if (IS_ERR(afe_priv->clocks[i])) { 39 if (IS_ERR(afe_priv->base_ck[i])) {
79 dev_warn(afe->dev, "%s devm_clk_get %s fail\n", 40 dev_err(afe->dev, "failed to get %s\n", base_clks[i]);
80 __func__, aud_clks[i]); 41 return PTR_ERR(afe_priv->base_ck[i]);
81 return PTR_ERR(aud_clks[i]); 42 }
43 }
44
45 /* Get I2S related clocks */
46 for (i = 0; i < MT2701_I2S_NUM; i++) {
47 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i];
48 char name[13];
49
50 snprintf(name, sizeof(name), "i2s%d_src_sel", i);
51 i2s_path->sel_ck = devm_clk_get(afe->dev, name);
52 if (IS_ERR(i2s_path->sel_ck)) {
53 dev_err(afe->dev, "failed to get %s\n", name);
54 return PTR_ERR(i2s_path->sel_ck);
55 }
56
57 snprintf(name, sizeof(name), "i2s%d_src_div", i);
58 i2s_path->div_ck = devm_clk_get(afe->dev, name);
59 if (IS_ERR(i2s_path->div_ck)) {
60 dev_err(afe->dev, "failed to get %s\n", name);
61 return PTR_ERR(i2s_path->div_ck);
62 }
63
64 snprintf(name, sizeof(name), "i2s%d_mclk_en", i);
65 i2s_path->mclk_ck = devm_clk_get(afe->dev, name);
66 if (IS_ERR(i2s_path->mclk_ck)) {
67 dev_err(afe->dev, "failed to get %s\n", name);
68 return PTR_ERR(i2s_path->mclk_ck);
69 }
70
71 snprintf(name, sizeof(name), "i2so%d_hop_ck", i);
72 i2s_path->hop_ck[I2S_OUT] = devm_clk_get(afe->dev, name);
73 if (IS_ERR(i2s_path->hop_ck[I2S_OUT])) {
74 dev_err(afe->dev, "failed to get %s\n", name);
75 return PTR_ERR(i2s_path->hop_ck[I2S_OUT]);
76 }
77
78 snprintf(name, sizeof(name), "i2si%d_hop_ck", i);
79 i2s_path->hop_ck[I2S_IN] = devm_clk_get(afe->dev, name);
80 if (IS_ERR(i2s_path->hop_ck[I2S_IN])) {
81 dev_err(afe->dev, "failed to get %s\n", name);
82 return PTR_ERR(i2s_path->hop_ck[I2S_IN]);
83 }
84
85 snprintf(name, sizeof(name), "asrc%d_out_ck", i);
86 i2s_path->asrco_ck = devm_clk_get(afe->dev, name);
87 if (IS_ERR(i2s_path->asrco_ck)) {
88 dev_err(afe->dev, "failed to get %s\n", name);
89 return PTR_ERR(i2s_path->asrco_ck);
82 } 90 }
83 } 91 }
84 92
93 /* Some platforms may support BT path */
94 afe_priv->mrgif_ck = devm_clk_get(afe->dev, "audio_mrgif_pd");
95 if (IS_ERR(afe_priv->mrgif_ck)) {
96 if (PTR_ERR(afe_priv->mrgif_ck) == -EPROBE_DEFER)
97 return -EPROBE_DEFER;
98
99 afe_priv->mrgif_ck = NULL;
100 }
101
85 return 0; 102 return 0;
86} 103}
87 104
88int mt2701_afe_enable_clock(struct mtk_base_afe *afe) 105int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir)
89{ 106{
90 int ret = 0; 107 struct mt2701_afe_private *afe_priv = afe->platform_priv;
108 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
109 int ret;
91 110
92 ret = mt2701_turn_on_a1sys_clock(afe); 111 ret = clk_prepare_enable(i2s_path->asrco_ck);
93 if (ret) { 112 if (ret) {
94 dev_err(afe->dev, "%s turn_on_a1sys_clock fail %d\n", 113 dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
95 __func__, ret);
96 return ret; 114 return ret;
97 } 115 }
98 116
99 ret = mt2701_turn_on_a2sys_clock(afe); 117 ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
100 if (ret) { 118 if (ret) {
101 dev_err(afe->dev, "%s turn_on_a2sys_clock fail %d\n", 119 dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
102 __func__, ret); 120 goto err_hop_ck;
103 mt2701_turn_off_a1sys_clock(afe);
104 return ret;
105 } 121 }
106 122
107 ret = mt2701_turn_on_afe_clock(afe); 123 return 0;
108 if (ret) {
109 dev_err(afe->dev, "%s turn_on_afe_clock fail %d\n",
110 __func__, ret);
111 mt2701_turn_off_a1sys_clock(afe);
112 mt2701_turn_off_a2sys_clock(afe);
113 return ret;
114 }
115 124
116 regmap_update_bits(afe->regmap, ASYS_TOP_CON, 125err_hop_ck:
117 AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 126 clk_disable_unprepare(i2s_path->asrco_ck);
118 AUDIO_TOP_CON0_A1SYS_A2SYS_ON);
119 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
120 AFE_DAC_CON0_AFE_ON,
121 AFE_DAC_CON0_AFE_ON);
122 regmap_write(afe->regmap, PWR2_TOP_CON,
123 PWR2_TOP_CON_INIT_VAL);
124 regmap_write(afe->regmap, PWR1_ASM_CON1,
125 PWR1_ASM_CON1_INIT_VAL);
126 regmap_write(afe->regmap, PWR2_ASM_CON1,
127 PWR2_ASM_CON1_INIT_VAL);
128 127
129 return 0; 128 return ret;
130} 129}
131 130
132void mt2701_afe_disable_clock(struct mtk_base_afe *afe) 131void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir)
133{ 132{
134 mt2701_turn_off_afe_clock(afe); 133 struct mt2701_afe_private *afe_priv = afe->platform_priv;
135 mt2701_turn_off_a1sys_clock(afe); 134 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
136 mt2701_turn_off_a2sys_clock(afe); 135
137 regmap_update_bits(afe->regmap, ASYS_TOP_CON, 136 clk_disable_unprepare(i2s_path->hop_ck[dir]);
138 AUDIO_TOP_CON0_A1SYS_A2SYS_ON, 0); 137 clk_disable_unprepare(i2s_path->asrco_ck);
139 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
140 AFE_DAC_CON0_AFE_ON, 0);
141} 138}
142 139
143int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe) 140int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id)
144{ 141{
145 struct mt2701_afe_private *afe_priv = afe->platform_priv; 142 struct mt2701_afe_private *afe_priv = afe->platform_priv;
146 int ret = 0; 143 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
147
148 /* Set Mux */
149 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
150 if (ret) {
151 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
152 __func__, aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
153 goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
154 }
155
156 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL],
157 afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]);
158 if (ret) {
159 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
160 aud_clks[MT2701_AUD_AUD_MUX1_SEL],
161 aud_clks[MT2701_AUD_AUD1PLL_98M], ret);
162 goto A1SYS_CLK_AUD_MUX1_SEL_ERR;
163 }
164
165 /* Set Divider */
166 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
167 if (ret) {
168 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
169 __func__,
170 aud_clks[MT2701_AUD_AUD_MUX1_DIV],
171 ret);
172 goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
173 }
174
175 ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV],
176 MT2701_AUD_AUD_MUX1_DIV_RATE);
177 if (ret) {
178 dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__,
179 aud_clks[MT2701_AUD_AUD_MUX1_DIV],
180 MT2701_AUD_AUD_MUX1_DIV_RATE, ret);
181 goto A1SYS_CLK_AUD_MUX1_DIV_ERR;
182 }
183 144
184 /* Enable clock gate */ 145 return clk_prepare_enable(i2s_path->mclk_ck);
185 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); 146}
186 if (ret) {
187 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
188 __func__, aud_clks[MT2701_AUD_AUD_48K_TIMING], ret);
189 goto A1SYS_CLK_AUD_48K_ERR;
190 }
191 147
192 /* Enable infra audio */ 148void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id)
193 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 149{
194 if (ret) { 150 struct mt2701_afe_private *afe_priv = afe->platform_priv;
195 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 151 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[id];
196 __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
197 goto A1SYS_CLK_INFRA_ERR;
198 }
199 152
200 return 0; 153 clk_disable_unprepare(i2s_path->mclk_ck);
154}
201 155
202A1SYS_CLK_INFRA_ERR: 156int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe)
203 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 157{
204A1SYS_CLK_AUD_48K_ERR: 158 struct mt2701_afe_private *afe_priv = afe->platform_priv;
205 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
206A1SYS_CLK_AUD_MUX1_DIV_ERR:
207 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
208A1SYS_CLK_AUD_MUX1_SEL_ERR:
209 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
210 159
211 return ret; 160 return clk_prepare_enable(afe_priv->mrgif_ck);
212} 161}
213 162
214void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe) 163void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe)
215{ 164{
216 struct mt2701_afe_private *afe_priv = afe->platform_priv; 165 struct mt2701_afe_private *afe_priv = afe->platform_priv;
217 166
218 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 167 clk_disable_unprepare(afe_priv->mrgif_ck);
219 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]);
220 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]);
221 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
222} 168}
223 169
224int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe) 170static int mt2701_afe_enable_audsys(struct mtk_base_afe *afe)
225{ 171{
226 struct mt2701_afe_private *afe_priv = afe->platform_priv; 172 struct mt2701_afe_private *afe_priv = afe->platform_priv;
227 int ret = 0; 173 int ret;
228 174
229 /* Set Mux */ 175 /* Enable infra clock gate */
230 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); 176 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
231 if (ret) { 177 if (ret)
232 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 178 return ret;
233 __func__, aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
234 goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
235 }
236 179
237 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL], 180 /* Enable top a1sys clock gate */
238 afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]); 181 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
239 if (ret) { 182 if (ret)
240 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, 183 goto err_a1sys;
241 aud_clks[MT2701_AUD_AUD_MUX2_SEL],
242 aud_clks[MT2701_AUD_AUD2PLL_90M], ret);
243 goto A2SYS_CLK_AUD_MUX2_SEL_ERR;
244 }
245 184
246 /* Set Divider */ 185 /* Enable top a2sys clock gate */
247 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); 186 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
248 if (ret) { 187 if (ret)
249 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 188 goto err_a2sys;
250 __func__, aud_clks[MT2701_AUD_AUD_MUX2_DIV], ret);
251 goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
252 }
253 189
254 ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV], 190 /* Internal clock gates */
255 MT2701_AUD_AUD_MUX2_DIV_RATE); 191 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
256 if (ret) { 192 if (ret)
257 dev_err(afe->dev, "%s clk_set_parent %s-%d fail %d\n", __func__, 193 goto err_afe;
258 aud_clks[MT2701_AUD_AUD_MUX2_DIV],
259 MT2701_AUD_AUD_MUX2_DIV_RATE, ret);
260 goto A2SYS_CLK_AUD_MUX2_DIV_ERR;
261 }
262 194
263 /* Enable clock gate */ 195 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
264 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); 196 if (ret)
265 if (ret) { 197 goto err_audio_a1sys;
266 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
267 __func__, aud_clks[MT2701_AUD_AUD_44K_TIMING], ret);
268 goto A2SYS_CLK_AUD_44K_ERR;
269 }
270 198
271 /* Enable infra audio */ 199 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
272 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 200 if (ret)
273 if (ret) { 201 goto err_audio_a2sys;
274 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 202
275 __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret); 203 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
276 goto A2SYS_CLK_INFRA_ERR; 204 if (ret)
277 } 205 goto err_afe_conn;
278 206
279 return 0; 207 return 0;
280 208
281A2SYS_CLK_INFRA_ERR: 209err_afe_conn:
282 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 210 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
283A2SYS_CLK_AUD_44K_ERR: 211err_audio_a2sys:
284 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); 212 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
285A2SYS_CLK_AUD_MUX2_DIV_ERR: 213err_audio_a1sys:
286 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); 214 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
287A2SYS_CLK_AUD_MUX2_SEL_ERR: 215err_afe:
288 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); 216 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
217err_a2sys:
218 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
219err_a1sys:
220 clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
289 221
290 return ret; 222 return ret;
291} 223}
292 224
293void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe) 225static void mt2701_afe_disable_audsys(struct mtk_base_afe *afe)
294{ 226{
295 struct mt2701_afe_private *afe_priv = afe->platform_priv; 227 struct mt2701_afe_private *afe_priv = afe->platform_priv;
296 228
297 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 229 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
298 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); 230 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
299 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); 231 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
300 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); 232 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
233 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
234 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
235 clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
301} 236}
302 237
303int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe) 238int mt2701_afe_enable_clock(struct mtk_base_afe *afe)
304{ 239{
305 struct mt2701_afe_private *afe_priv = afe->platform_priv;
306 int ret; 240 int ret;
307 241
308 /* enable INFRA_SYS */ 242 /* Enable audio system */
309 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 243 ret = mt2701_afe_enable_audsys(afe);
310 if (ret) {
311 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
312 __func__, aud_clks[MT2701_AUD_INFRA_SYS_AUDIO], ret);
313 goto AFE_AUD_INFRA_ERR;
314 }
315
316 /* Set MT2701_AUD_AUDINTBUS to MT2701_AUD_SYSPLL1_D4 */
317 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
318 if (ret) {
319 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
320 __func__, aud_clks[MT2701_AUD_AUDINTBUS], ret);
321 goto AFE_AUD_AUDINTBUS_ERR;
322 }
323
324 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS],
325 afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]);
326 if (ret) {
327 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
328 aud_clks[MT2701_AUD_AUDINTBUS],
329 aud_clks[MT2701_AUD_SYSPLL1_D4], ret);
330 goto AFE_AUD_AUDINTBUS_ERR;
331 }
332
333 /* Set MT2701_AUD_ASM_H_SEL to MT2701_AUD_UNIVPLL2_D2 */
334 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
335 if (ret) { 244 if (ret) {
336 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 245 dev_err(afe->dev, "failed to enable audio system %d\n", ret);
337 __func__, aud_clks[MT2701_AUD_ASM_H_SEL], ret); 246 return ret;
338 goto AFE_AUD_ASM_H_ERR;
339 }
340
341 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL],
342 afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]);
343 if (ret) {
344 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__,
345 aud_clks[MT2701_AUD_ASM_H_SEL],
346 aud_clks[MT2701_AUD_UNIVPLL2_D2], ret);
347 goto AFE_AUD_ASM_H_ERR;
348 }
349
350 /* Set MT2701_AUD_ASM_M_SEL to MT2701_AUD_UNIVPLL2_D4 */
351 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
352 if (ret) {
353 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
354 __func__, aud_clks[MT2701_AUD_ASM_M_SEL], ret);
355 goto AFE_AUD_ASM_M_ERR;
356 } 247 }
357 248
358 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL], 249 regmap_update_bits(afe->regmap, ASYS_TOP_CON,
359 afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]); 250 ASYS_TOP_CON_ASYS_TIMING_ON,
360 if (ret) { 251 ASYS_TOP_CON_ASYS_TIMING_ON);
361 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n", __func__, 252 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
362 aud_clks[MT2701_AUD_ASM_M_SEL], 253 AFE_DAC_CON0_AFE_ON,
363 aud_clks[MT2701_AUD_UNIVPLL2_D4], ret); 254 AFE_DAC_CON0_AFE_ON);
364 goto AFE_AUD_ASM_M_ERR;
365 }
366 255
367 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 256 /* Configure ASRC */
368 AUDIO_TOP_CON0_PDN_AFE, 0); 257 regmap_write(afe->regmap, PWR1_ASM_CON1, PWR1_ASM_CON1_INIT_VAL);
369 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 258 regmap_write(afe->regmap, PWR2_ASM_CON1, PWR2_ASM_CON1_INIT_VAL);
370 AUDIO_TOP_CON0_PDN_APLL_CK, 0);
371 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
372 AUDIO_TOP_CON4_PDN_A1SYS, 0);
373 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
374 AUDIO_TOP_CON4_PDN_A2SYS, 0);
375 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
376 AUDIO_TOP_CON4_PDN_AFE_CONN, 0);
377 259
378 return 0; 260 return 0;
379
380AFE_AUD_ASM_M_ERR:
381 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
382AFE_AUD_ASM_H_ERR:
383 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
384AFE_AUD_AUDINTBUS_ERR:
385 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
386AFE_AUD_INFRA_ERR:
387 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]);
388
389 return ret;
390} 261}
391 262
392void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe) 263int mt2701_afe_disable_clock(struct mtk_base_afe *afe)
393{ 264{
394 struct mt2701_afe_private *afe_priv = afe->platform_priv; 265 regmap_update_bits(afe->regmap, ASYS_TOP_CON,
266 ASYS_TOP_CON_ASYS_TIMING_ON, 0);
267 regmap_update_bits(afe->regmap, AFE_DAC_CON0,
268 AFE_DAC_CON0_AFE_ON, 0);
269
270 mt2701_afe_disable_audsys(afe);
395 271
396 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); 272 return 0;
397
398 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]);
399 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]);
400 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]);
401
402 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
403 AUDIO_TOP_CON0_PDN_AFE, AUDIO_TOP_CON0_PDN_AFE);
404 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
405 AUDIO_TOP_CON0_PDN_APLL_CK,
406 AUDIO_TOP_CON0_PDN_APLL_CK);
407 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
408 AUDIO_TOP_CON4_PDN_A1SYS,
409 AUDIO_TOP_CON4_PDN_A1SYS);
410 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
411 AUDIO_TOP_CON4_PDN_A2SYS,
412 AUDIO_TOP_CON4_PDN_A2SYS);
413 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4,
414 AUDIO_TOP_CON4_PDN_AFE_CONN,
415 AUDIO_TOP_CON4_PDN_AFE_CONN);
416} 273}
417 274
418void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, 275void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
419 int mclk) 276 int mclk)
420{ 277{
421 struct mt2701_afe_private *afe_priv = afe->platform_priv; 278 struct mt2701_afe_private *priv = afe->platform_priv;
279 struct mt2701_i2s_path *i2s_path = &priv->i2s_path[id];
422 int ret; 280 int ret;
423 int aud_src_div_id = MT2701_AUD_AUD_K1_SRC_DIV + id;
424 int aud_src_clk_id = MT2701_AUD_AUD_K1_SRC_SEL + id;
425 281
426 /* Set MCLK Kx_SRC_SEL(domain) */ 282 /* Set mclk source */
427 ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]); 283 if (domain == 0)
428 if (ret) 284 ret = clk_set_parent(i2s_path->sel_ck,
429 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 285 priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
430 __func__, aud_clks[aud_src_clk_id], ret); 286 else
431 287 ret = clk_set_parent(i2s_path->sel_ck,
432 if (domain == 0) { 288 priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);
433 ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
434 afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]);
435 if (ret)
436 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
437 __func__, aud_clks[aud_src_clk_id],
438 aud_clks[MT2701_AUD_AUD_MUX1_SEL], ret);
439 } else {
440 ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id],
441 afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]);
442 if (ret)
443 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
444 __func__, aud_clks[aud_src_clk_id],
445 aud_clks[MT2701_AUD_AUD_MUX2_SEL], ret);
446 }
447 clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]);
448 289
449 /* Set MCLK Kx_SRC_DIV(divider) */
450 ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]);
451 if (ret) 290 if (ret)
452 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n", 291 dev_err(afe->dev, "failed to set domain%d mclk source %d\n",
453 __func__, aud_clks[aud_src_div_id], ret); 292 domain, ret);
454 293
455 ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk); 294 /* Set mclk divider */
295 ret = clk_set_rate(i2s_path->div_ck, mclk);
456 if (ret) 296 if (ret)
457 dev_err(afe->dev, "%s clk_set_rate %s-%d fail %d\n", __func__, 297 dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
458 aud_clks[aud_src_div_id], mclk, ret);
459 clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]);
460} 298}
461
462MODULE_DESCRIPTION("MT2701 afe clock control");
463MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
464MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
index 6497d570cf09..15417d9d6597 100644
--- a/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-clock-ctrl.h
@@ -21,16 +21,15 @@ struct mtk_base_afe;
21 21
22int mt2701_init_clock(struct mtk_base_afe *afe); 22int mt2701_init_clock(struct mtk_base_afe *afe);
23int mt2701_afe_enable_clock(struct mtk_base_afe *afe); 23int mt2701_afe_enable_clock(struct mtk_base_afe *afe);
24void mt2701_afe_disable_clock(struct mtk_base_afe *afe); 24int mt2701_afe_disable_clock(struct mtk_base_afe *afe);
25 25
26int mt2701_turn_on_a1sys_clock(struct mtk_base_afe *afe); 26int mt2701_afe_enable_i2s(struct mtk_base_afe *afe, int id, int dir);
27void mt2701_turn_off_a1sys_clock(struct mtk_base_afe *afe); 27void mt2701_afe_disable_i2s(struct mtk_base_afe *afe, int id, int dir);
28int mt2701_afe_enable_mclk(struct mtk_base_afe *afe, int id);
29void mt2701_afe_disable_mclk(struct mtk_base_afe *afe, int id);
28 30
29int mt2701_turn_on_a2sys_clock(struct mtk_base_afe *afe); 31int mt2701_enable_btmrg_clk(struct mtk_base_afe *afe);
30void mt2701_turn_off_a2sys_clock(struct mtk_base_afe *afe); 32void mt2701_disable_btmrg_clk(struct mtk_base_afe *afe);
31
32int mt2701_turn_on_afe_clock(struct mtk_base_afe *afe);
33void mt2701_turn_off_afe_clock(struct mtk_base_afe *afe);
34 33
35void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain, 34void mt2701_mclk_configuration(struct mtk_base_afe *afe, int id, int domain,
36 int mclk); 35 int mclk);
diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-common.h b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
index c19430e98adf..ae8ddeacfbfe 100644
--- a/sound/soc/mediatek/mt2701/mt2701-afe-common.h
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-common.h
@@ -16,6 +16,7 @@
16 16
17#ifndef _MT_2701_AFE_COMMON_H_ 17#ifndef _MT_2701_AFE_COMMON_H_
18#define _MT_2701_AFE_COMMON_H_ 18#define _MT_2701_AFE_COMMON_H_
19
19#include <sound/soc.h> 20#include <sound/soc.h>
20#include <linux/clk.h> 21#include <linux/clk.h>
21#include <linux/regmap.h> 22#include <linux/regmap.h>
@@ -25,16 +26,7 @@
25#define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1) 26#define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
26#define MT2701_PLL_DOMAIN_0_RATE 98304000 27#define MT2701_PLL_DOMAIN_0_RATE 98304000
27#define MT2701_PLL_DOMAIN_1_RATE 90316800 28#define MT2701_PLL_DOMAIN_1_RATE 90316800
28#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2) 29#define MT2701_I2S_NUM 4
29#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
30
31enum {
32 MT2701_I2S_1,
33 MT2701_I2S_2,
34 MT2701_I2S_3,
35 MT2701_I2S_4,
36 MT2701_I2S_NUM,
37};
38 30
39enum { 31enum {
40 MT2701_MEMIF_DL1, 32 MT2701_MEMIF_DL1,
@@ -62,60 +54,23 @@ enum {
62}; 54};
63 55
64enum { 56enum {
65 MT2701_IRQ_ASYS_START, 57 MT2701_IRQ_ASYS_IRQ1,
66 MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
67 MT2701_IRQ_ASYS_IRQ2, 58 MT2701_IRQ_ASYS_IRQ2,
68 MT2701_IRQ_ASYS_IRQ3, 59 MT2701_IRQ_ASYS_IRQ3,
69 MT2701_IRQ_ASYS_END, 60 MT2701_IRQ_ASYS_END,
70}; 61};
71 62
72/* 2701 clock def */ 63enum audio_base_clock {
73enum audio_system_clock_type { 64 MT2701_INFRA_SYS_AUDIO,
74 MT2701_AUD_INFRA_SYS_AUDIO, 65 MT2701_TOP_AUD_MCLK_SRC0,
75 MT2701_AUD_AUD_MUX1_SEL, 66 MT2701_TOP_AUD_MCLK_SRC1,
76 MT2701_AUD_AUD_MUX2_SEL, 67 MT2701_TOP_AUD_A1SYS,
77 MT2701_AUD_AUD_MUX1_DIV, 68 MT2701_TOP_AUD_A2SYS,
78 MT2701_AUD_AUD_MUX2_DIV, 69 MT2701_AUDSYS_AFE,
79 MT2701_AUD_AUD_48K_TIMING, 70 MT2701_AUDSYS_AFE_CONN,
80 MT2701_AUD_AUD_44K_TIMING, 71 MT2701_AUDSYS_A1SYS,
81 MT2701_AUD_AUDPLL_MUX_SEL, 72 MT2701_AUDSYS_A2SYS,
82 MT2701_AUD_APLL_SEL, 73 MT2701_BASE_CLK_NUM,
83 MT2701_AUD_AUD1PLL_98M,
84 MT2701_AUD_AUD2PLL_90M,
85 MT2701_AUD_HADDS2PLL_98M,
86 MT2701_AUD_HADDS2PLL_294M,
87 MT2701_AUD_AUDPLL,
88 MT2701_AUD_AUDPLL_D4,
89 MT2701_AUD_AUDPLL_D8,
90 MT2701_AUD_AUDPLL_D16,
91 MT2701_AUD_AUDPLL_D24,
92 MT2701_AUD_AUDINTBUS,
93 MT2701_AUD_CLK_26M,
94 MT2701_AUD_SYSPLL1_D4,
95 MT2701_AUD_AUD_K1_SRC_SEL,
96 MT2701_AUD_AUD_K2_SRC_SEL,
97 MT2701_AUD_AUD_K3_SRC_SEL,
98 MT2701_AUD_AUD_K4_SRC_SEL,
99 MT2701_AUD_AUD_K5_SRC_SEL,
100 MT2701_AUD_AUD_K6_SRC_SEL,
101 MT2701_AUD_AUD_K1_SRC_DIV,
102 MT2701_AUD_AUD_K2_SRC_DIV,
103 MT2701_AUD_AUD_K3_SRC_DIV,
104 MT2701_AUD_AUD_K4_SRC_DIV,
105 MT2701_AUD_AUD_K5_SRC_DIV,
106 MT2701_AUD_AUD_K6_SRC_DIV,
107 MT2701_AUD_AUD_I2S1_MCLK,
108 MT2701_AUD_AUD_I2S2_MCLK,
109 MT2701_AUD_AUD_I2S3_MCLK,
110 MT2701_AUD_AUD_I2S4_MCLK,
111 MT2701_AUD_AUD_I2S5_MCLK,
112 MT2701_AUD_AUD_I2S6_MCLK,
113 MT2701_AUD_ASM_M_SEL,
114 MT2701_AUD_ASM_H_SEL,
115 MT2701_AUD_UNIVPLL2_D4,
116 MT2701_AUD_UNIVPLL2_D2,
117 MT2701_AUD_SYSPLL_D5,
118 MT2701_CLOCK_NUM
119}; 74};
120 75
121static const unsigned int mt2701_afe_backup_list[] = { 76static const unsigned int mt2701_afe_backup_list[] = {
@@ -139,12 +94,8 @@ static const unsigned int mt2701_afe_backup_list[] = {
139 AFE_MEMIF_PBUF_SIZE, 94 AFE_MEMIF_PBUF_SIZE,
140}; 95};
141 96
142struct snd_pcm_substream;
143struct mtk_base_irq_data;
144
145struct mt2701_i2s_data { 97struct mt2701_i2s_data {
146 int i2s_ctrl_reg; 98 int i2s_ctrl_reg;
147 int i2s_pwn_shift;
148 int i2s_asrc_fs_shift; 99 int i2s_asrc_fs_shift;
149 int i2s_asrc_fs_mask; 100 int i2s_asrc_fs_mask;
150}; 101};
@@ -160,12 +111,18 @@ struct mt2701_i2s_path {
160 int mclk_rate; 111 int mclk_rate;
161 int on[I2S_DIR_NUM]; 112 int on[I2S_DIR_NUM];
162 int occupied[I2S_DIR_NUM]; 113 int occupied[I2S_DIR_NUM];
163 const struct mt2701_i2s_data *i2s_data[2]; 114 const struct mt2701_i2s_data *i2s_data[I2S_DIR_NUM];
115 struct clk *hop_ck[I2S_DIR_NUM];
116 struct clk *sel_ck;
117 struct clk *div_ck;
118 struct clk *mclk_ck;
119 struct clk *asrco_ck;
164}; 120};
165 121
166struct mt2701_afe_private { 122struct mt2701_afe_private {
167 struct clk *clocks[MT2701_CLOCK_NUM];
168 struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM]; 123 struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
124 struct clk *base_ck[MT2701_BASE_CLK_NUM];
125 struct clk *mrgif_ck;
169 bool mrg_enable[MT2701_STREAM_DIR_NUM]; 126 bool mrg_enable[MT2701_STREAM_DIR_NUM];
170}; 127};
171 128
diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
index a7362d1cda1b..5bc4e00a4a29 100644
--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
@@ -17,19 +17,16 @@
17 17
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/mfd/syscon.h>
20#include <linux/of.h> 21#include <linux/of.h>
21#include <linux/of_address.h> 22#include <linux/of_address.h>
22#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
23#include <sound/soc.h>
24 24
25#include "mt2701-afe-common.h" 25#include "mt2701-afe-common.h"
26
27#include "mt2701-afe-clock-ctrl.h" 26#include "mt2701-afe-clock-ctrl.h"
28#include "../common/mtk-afe-platform-driver.h" 27#include "../common/mtk-afe-platform-driver.h"
29#include "../common/mtk-afe-fe-dai.h" 28#include "../common/mtk-afe-fe-dai.h"
30 29
31#define AFE_IRQ_STATUS_BITS 0xff
32
33static const struct snd_pcm_hardware mt2701_afe_hardware = { 30static const struct snd_pcm_hardware mt2701_afe_hardware = {
34 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED 31 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED
35 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID, 32 | SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID,
@@ -97,40 +94,26 @@ static int mt2701_afe_i2s_startup(struct snd_pcm_substream *substream,
97{ 94{
98 struct snd_soc_pcm_runtime *rtd = substream->private_data; 95 struct snd_soc_pcm_runtime *rtd = substream->private_data;
99 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 96 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
100 struct mt2701_afe_private *afe_priv = afe->platform_priv;
101 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 97 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
102 int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
103 int ret = 0;
104 98
105 if (i2s_num < 0) 99 if (i2s_num < 0)
106 return i2s_num; 100 return i2s_num;
107 101
108 /* enable mclk */ 102 return mt2701_afe_enable_mclk(afe, i2s_num);
109 ret = clk_prepare_enable(afe_priv->clocks[clk_num]);
110 if (ret)
111 dev_err(afe->dev, "Failed to enable mclk for I2S: %d\n",
112 i2s_num);
113
114 return ret;
115} 103}
116 104
117static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream, 105static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
118 struct snd_soc_dai *dai, 106 struct snd_soc_dai *dai,
107 int i2s_num,
119 int dir_invert) 108 int dir_invert)
120{ 109{
121 struct snd_soc_pcm_runtime *rtd = substream->private_data; 110 struct snd_soc_pcm_runtime *rtd = substream->private_data;
122 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 111 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
123 struct mt2701_afe_private *afe_priv = afe->platform_priv; 112 struct mt2701_afe_private *afe_priv = afe->platform_priv;
124 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 113 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
125 struct mt2701_i2s_path *i2s_path;
126 const struct mt2701_i2s_data *i2s_data; 114 const struct mt2701_i2s_data *i2s_data;
127 int stream_dir = substream->stream; 115 int stream_dir = substream->stream;
128 116
129 if (i2s_num < 0)
130 return i2s_num;
131
132 i2s_path = &afe_priv->i2s_path[i2s_num];
133
134 if (dir_invert) { 117 if (dir_invert) {
135 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) 118 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
136 stream_dir = SNDRV_PCM_STREAM_CAPTURE; 119 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
@@ -151,9 +134,9 @@ static int mt2701_afe_i2s_path_shutdown(struct snd_pcm_substream *substream,
151 /* disable i2s */ 134 /* disable i2s */
152 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, 135 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
153 ASYS_I2S_CON_I2S_EN, 0); 136 ASYS_I2S_CON_I2S_EN, 0);
154 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 137
155 1 << i2s_data->i2s_pwn_shift, 138 mt2701_afe_disable_i2s(afe, i2s_num, stream_dir);
156 1 << i2s_data->i2s_pwn_shift); 139
157 return 0; 140 return 0;
158} 141}
159 142
@@ -165,7 +148,6 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
165 struct mt2701_afe_private *afe_priv = afe->platform_priv; 148 struct mt2701_afe_private *afe_priv = afe->platform_priv;
166 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 149 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id);
167 struct mt2701_i2s_path *i2s_path; 150 struct mt2701_i2s_path *i2s_path;
168 int clk_num = MT2701_AUD_AUD_I2S1_MCLK + i2s_num;
169 151
170 if (i2s_num < 0) 152 if (i2s_num < 0)
171 return; 153 return;
@@ -177,37 +159,32 @@ static void mt2701_afe_i2s_shutdown(struct snd_pcm_substream *substream,
177 else 159 else
178 goto I2S_UNSTART; 160 goto I2S_UNSTART;
179 161
180 mt2701_afe_i2s_path_shutdown(substream, dai, 0); 162 mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 0);
181 163
182 /* need to disable i2s-out path when disable i2s-in */ 164 /* need to disable i2s-out path when disable i2s-in */
183 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 165 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
184 mt2701_afe_i2s_path_shutdown(substream, dai, 1); 166 mt2701_afe_i2s_path_shutdown(substream, dai, i2s_num, 1);
185 167
186I2S_UNSTART: 168I2S_UNSTART:
187 /* disable mclk */ 169 /* disable mclk */
188 clk_disable_unprepare(afe_priv->clocks[clk_num]); 170 mt2701_afe_disable_mclk(afe, i2s_num);
189} 171}
190 172
191static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream, 173static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
192 struct snd_soc_dai *dai, 174 struct snd_soc_dai *dai,
175 int i2s_num,
193 int dir_invert) 176 int dir_invert)
194{ 177{
195 struct snd_soc_pcm_runtime *rtd = substream->private_data; 178 struct snd_soc_pcm_runtime *rtd = substream->private_data;
196 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 179 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
197 struct mt2701_afe_private *afe_priv = afe->platform_priv; 180 struct mt2701_afe_private *afe_priv = afe->platform_priv;
198 int i2s_num = mt2701_dai_num_to_i2s(afe, dai->id); 181 struct mt2701_i2s_path *i2s_path = &afe_priv->i2s_path[i2s_num];
199 struct mt2701_i2s_path *i2s_path;
200 const struct mt2701_i2s_data *i2s_data; 182 const struct mt2701_i2s_data *i2s_data;
201 struct snd_pcm_runtime * const runtime = substream->runtime; 183 struct snd_pcm_runtime * const runtime = substream->runtime;
202 int reg, fs, w_len = 1; /* now we support bck 64bits only */ 184 int reg, fs, w_len = 1; /* now we support bck 64bits only */
203 int stream_dir = substream->stream; 185 int stream_dir = substream->stream;
204 unsigned int mask = 0, val = 0; 186 unsigned int mask = 0, val = 0;
205 187
206 if (i2s_num < 0)
207 return i2s_num;
208
209 i2s_path = &afe_priv->i2s_path[i2s_num];
210
211 if (dir_invert) { 188 if (dir_invert) {
212 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK) 189 if (stream_dir == SNDRV_PCM_STREAM_PLAYBACK)
213 stream_dir = SNDRV_PCM_STREAM_CAPTURE; 190 stream_dir = SNDRV_PCM_STREAM_CAPTURE;
@@ -251,9 +228,7 @@ static int mt2701_i2s_path_prepare_enable(struct snd_pcm_substream *substream,
251 fs << i2s_data->i2s_asrc_fs_shift); 228 fs << i2s_data->i2s_asrc_fs_shift);
252 229
253 /* enable i2s */ 230 /* enable i2s */
254 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 231 mt2701_afe_enable_i2s(afe, i2s_num, stream_dir);
255 1 << i2s_data->i2s_pwn_shift,
256 0 << i2s_data->i2s_pwn_shift);
257 232
258 /* reset i2s hw status before enable */ 233 /* reset i2s hw status before enable */
259 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg, 234 regmap_update_bits(afe->regmap, i2s_data->i2s_ctrl_reg,
@@ -300,13 +275,13 @@ static int mt2701_afe_i2s_prepare(struct snd_pcm_substream *substream,
300 mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate); 275 mt2701_mclk_configuration(afe, i2s_num, clk_domain, mclk_rate);
301 276
302 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 277 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
303 mt2701_i2s_path_prepare_enable(substream, dai, 0); 278 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
304 } else { 279 } else {
305 /* need to enable i2s-out path when enable i2s-in */ 280 /* need to enable i2s-out path when enable i2s-in */
306 /* prepare for another direction "out" */ 281 /* prepare for another direction "out" */
307 mt2701_i2s_path_prepare_enable(substream, dai, 1); 282 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 1);
308 /* prepare for "in" */ 283 /* prepare for "in" */
309 mt2701_i2s_path_prepare_enable(substream, dai, 0); 284 mt2701_i2s_path_prepare_enable(substream, dai, i2s_num, 0);
310 } 285 }
311 286
312 return 0; 287 return 0;
@@ -339,9 +314,11 @@ static int mt2701_btmrg_startup(struct snd_pcm_substream *substream,
339 struct snd_soc_pcm_runtime *rtd = substream->private_data; 314 struct snd_soc_pcm_runtime *rtd = substream->private_data;
340 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform); 315 struct mtk_base_afe *afe = snd_soc_platform_get_drvdata(rtd->platform);
341 struct mt2701_afe_private *afe_priv = afe->platform_priv; 316 struct mt2701_afe_private *afe_priv = afe->platform_priv;
317 int ret;
342 318
343 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 319 ret = mt2701_enable_btmrg_clk(afe);
344 AUDIO_TOP_CON4_PDN_MRGIF, 0); 320 if (ret)
321 return ret;
345 322
346 afe_priv->mrg_enable[substream->stream] = 1; 323 afe_priv->mrg_enable[substream->stream] = 1;
347 return 0; 324 return 0;
@@ -406,9 +383,7 @@ static void mt2701_btmrg_shutdown(struct snd_pcm_substream *substream,
406 AFE_MRGIF_CON_MRG_EN, 0); 383 AFE_MRGIF_CON_MRG_EN, 0);
407 regmap_update_bits(afe->regmap, AFE_MRGIF_CON, 384 regmap_update_bits(afe->regmap, AFE_MRGIF_CON,
408 AFE_MRGIF_CON_MRG_I2S_EN, 0); 385 AFE_MRGIF_CON_MRG_I2S_EN, 0);
409 regmap_update_bits(afe->regmap, AUDIO_TOP_CON4, 386 mt2701_disable_btmrg_clk(afe);
410 AUDIO_TOP_CON4_PDN_MRGIF,
411 AUDIO_TOP_CON4_PDN_MRGIF);
412 } 387 }
413 afe_priv->mrg_enable[substream->stream] = 0; 388 afe_priv->mrg_enable[substream->stream] = 0;
414} 389}
@@ -574,7 +549,6 @@ static const struct snd_soc_dai_ops mt2701_single_memif_dai_ops = {
574 .hw_free = mtk_afe_fe_hw_free, 549 .hw_free = mtk_afe_fe_hw_free,
575 .prepare = mtk_afe_fe_prepare, 550 .prepare = mtk_afe_fe_prepare,
576 .trigger = mtk_afe_fe_trigger, 551 .trigger = mtk_afe_fe_trigger,
577
578}; 552};
579 553
580static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = { 554static const struct snd_soc_dai_ops mt2701_dlm_memif_dai_ops = {
@@ -915,31 +889,6 @@ static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_i2s4[] = {
915 PWR2_TOP_CON, 19, 1, 0), 889 PWR2_TOP_CON, 19, 1, 0),
916}; 890};
917 891
918static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc0[] = {
919 SOC_DAPM_SINGLE_AUTODISABLE("Asrc0 out Switch", AUDIO_TOP_CON4, 14, 1,
920 1),
921};
922
923static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc1[] = {
924 SOC_DAPM_SINGLE_AUTODISABLE("Asrc1 out Switch", AUDIO_TOP_CON4, 15, 1,
925 1),
926};
927
928static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc2[] = {
929 SOC_DAPM_SINGLE_AUTODISABLE("Asrc2 out Switch", PWR2_TOP_CON, 6, 1,
930 1),
931};
932
933static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc3[] = {
934 SOC_DAPM_SINGLE_AUTODISABLE("Asrc3 out Switch", PWR2_TOP_CON, 7, 1,
935 1),
936};
937
938static const struct snd_kcontrol_new mt2701_afe_multi_ch_out_asrc4[] = {
939 SOC_DAPM_SINGLE_AUTODISABLE("Asrc4 out Switch", PWR2_TOP_CON, 8, 1,
940 1),
941};
942
943static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = { 892static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
944 /* inter-connections */ 893 /* inter-connections */
945 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0), 894 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -999,19 +948,6 @@ static const struct snd_soc_dapm_widget mt2701_afe_pcm_widgets[] = {
999 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0, 948 SND_SOC_DAPM_MIXER("I18I19", SND_SOC_NOPM, 0, 0,
1000 mt2701_afe_multi_ch_out_i2s3, 949 mt2701_afe_multi_ch_out_i2s3,
1001 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)), 950 ARRAY_SIZE(mt2701_afe_multi_ch_out_i2s3)),
1002
1003 SND_SOC_DAPM_MIXER("ASRC_O0", SND_SOC_NOPM, 0, 0,
1004 mt2701_afe_multi_ch_out_asrc0,
1005 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc0)),
1006 SND_SOC_DAPM_MIXER("ASRC_O1", SND_SOC_NOPM, 0, 0,
1007 mt2701_afe_multi_ch_out_asrc1,
1008 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc1)),
1009 SND_SOC_DAPM_MIXER("ASRC_O2", SND_SOC_NOPM, 0, 0,
1010 mt2701_afe_multi_ch_out_asrc2,
1011 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc2)),
1012 SND_SOC_DAPM_MIXER("ASRC_O3", SND_SOC_NOPM, 0, 0,
1013 mt2701_afe_multi_ch_out_asrc3,
1014 ARRAY_SIZE(mt2701_afe_multi_ch_out_asrc3)),
1015}; 951};
1016 952
1017static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = { 953static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
@@ -1021,7 +957,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
1021 957
1022 {"I2S0 Playback", NULL, "O15"}, 958 {"I2S0 Playback", NULL, "O15"},
1023 {"I2S0 Playback", NULL, "O16"}, 959 {"I2S0 Playback", NULL, "O16"},
1024
1025 {"I2S1 Playback", NULL, "O17"}, 960 {"I2S1 Playback", NULL, "O17"},
1026 {"I2S1 Playback", NULL, "O18"}, 961 {"I2S1 Playback", NULL, "O18"},
1027 {"I2S2 Playback", NULL, "O19"}, 962 {"I2S2 Playback", NULL, "O19"},
@@ -1038,7 +973,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
1038 973
1039 {"I00", NULL, "I2S0 Capture"}, 974 {"I00", NULL, "I2S0 Capture"},
1040 {"I01", NULL, "I2S0 Capture"}, 975 {"I01", NULL, "I2S0 Capture"},
1041
1042 {"I02", NULL, "I2S1 Capture"}, 976 {"I02", NULL, "I2S1 Capture"},
1043 {"I03", NULL, "I2S1 Capture"}, 977 {"I03", NULL, "I2S1 Capture"},
1044 /* I02,03 link to UL2, also need to open I2S0 */ 978 /* I02,03 link to UL2, also need to open I2S0 */
@@ -1046,15 +980,10 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
1046 980
1047 {"I26", NULL, "BT Capture"}, 981 {"I26", NULL, "BT Capture"},
1048 982
1049 {"ASRC_O0", "Asrc0 out Switch", "DLM"}, 983 {"I12I13", "Multich I2S0 Out Switch", "DLM"},
1050 {"ASRC_O1", "Asrc1 out Switch", "DLM"}, 984 {"I14I15", "Multich I2S1 Out Switch", "DLM"},
1051 {"ASRC_O2", "Asrc2 out Switch", "DLM"}, 985 {"I16I17", "Multich I2S2 Out Switch", "DLM"},
1052 {"ASRC_O3", "Asrc3 out Switch", "DLM"}, 986 {"I18I19", "Multich I2S3 Out Switch", "DLM"},
1053
1054 {"I12I13", "Multich I2S0 Out Switch", "ASRC_O0"},
1055 {"I14I15", "Multich I2S1 Out Switch", "ASRC_O1"},
1056 {"I16I17", "Multich I2S2 Out Switch", "ASRC_O2"},
1057 {"I18I19", "Multich I2S3 Out Switch", "ASRC_O3"},
1058 987
1059 { "I12", NULL, "I12I13" }, 988 { "I12", NULL, "I12I13" },
1060 { "I13", NULL, "I12I13" }, 989 { "I13", NULL, "I12I13" },
@@ -1079,7 +1008,6 @@ static const struct snd_soc_dapm_route mt2701_afe_pcm_routes[] = {
1079 { "O21", "I18 Switch", "I18" }, 1008 { "O21", "I18 Switch", "I18" },
1080 { "O22", "I19 Switch", "I19" }, 1009 { "O22", "I19 Switch", "I19" },
1081 { "O31", "I35 Switch", "I35" }, 1010 { "O31", "I35 Switch", "I35" },
1082
1083}; 1011};
1084 1012
1085static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = { 1013static const struct snd_soc_component_driver mt2701_afe_pcm_dai_component = {
@@ -1386,14 +1314,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1386 { 1314 {
1387 { 1315 {
1388 .i2s_ctrl_reg = ASYS_I2SO1_CON, 1316 .i2s_ctrl_reg = ASYS_I2SO1_CON,
1389 .i2s_pwn_shift = 6,
1390 .i2s_asrc_fs_shift = 0, 1317 .i2s_asrc_fs_shift = 0,
1391 .i2s_asrc_fs_mask = 0x1f, 1318 .i2s_asrc_fs_mask = 0x1f,
1392 1319
1393 }, 1320 },
1394 { 1321 {
1395 .i2s_ctrl_reg = ASYS_I2SIN1_CON, 1322 .i2s_ctrl_reg = ASYS_I2SIN1_CON,
1396 .i2s_pwn_shift = 0,
1397 .i2s_asrc_fs_shift = 0, 1323 .i2s_asrc_fs_shift = 0,
1398 .i2s_asrc_fs_mask = 0x1f, 1324 .i2s_asrc_fs_mask = 0x1f,
1399 1325
@@ -1402,14 +1328,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1402 { 1328 {
1403 { 1329 {
1404 .i2s_ctrl_reg = ASYS_I2SO2_CON, 1330 .i2s_ctrl_reg = ASYS_I2SO2_CON,
1405 .i2s_pwn_shift = 7,
1406 .i2s_asrc_fs_shift = 5, 1331 .i2s_asrc_fs_shift = 5,
1407 .i2s_asrc_fs_mask = 0x1f, 1332 .i2s_asrc_fs_mask = 0x1f,
1408 1333
1409 }, 1334 },
1410 { 1335 {
1411 .i2s_ctrl_reg = ASYS_I2SIN2_CON, 1336 .i2s_ctrl_reg = ASYS_I2SIN2_CON,
1412 .i2s_pwn_shift = 1,
1413 .i2s_asrc_fs_shift = 5, 1337 .i2s_asrc_fs_shift = 5,
1414 .i2s_asrc_fs_mask = 0x1f, 1338 .i2s_asrc_fs_mask = 0x1f,
1415 1339
@@ -1418,14 +1342,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1418 { 1342 {
1419 { 1343 {
1420 .i2s_ctrl_reg = ASYS_I2SO3_CON, 1344 .i2s_ctrl_reg = ASYS_I2SO3_CON,
1421 .i2s_pwn_shift = 8,
1422 .i2s_asrc_fs_shift = 10, 1345 .i2s_asrc_fs_shift = 10,
1423 .i2s_asrc_fs_mask = 0x1f, 1346 .i2s_asrc_fs_mask = 0x1f,
1424 1347
1425 }, 1348 },
1426 { 1349 {
1427 .i2s_ctrl_reg = ASYS_I2SIN3_CON, 1350 .i2s_ctrl_reg = ASYS_I2SIN3_CON,
1428 .i2s_pwn_shift = 2,
1429 .i2s_asrc_fs_shift = 10, 1351 .i2s_asrc_fs_shift = 10,
1430 .i2s_asrc_fs_mask = 0x1f, 1352 .i2s_asrc_fs_mask = 0x1f,
1431 1353
@@ -1434,14 +1356,12 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1434 { 1356 {
1435 { 1357 {
1436 .i2s_ctrl_reg = ASYS_I2SO4_CON, 1358 .i2s_ctrl_reg = ASYS_I2SO4_CON,
1437 .i2s_pwn_shift = 9,
1438 .i2s_asrc_fs_shift = 15, 1359 .i2s_asrc_fs_shift = 15,
1439 .i2s_asrc_fs_mask = 0x1f, 1360 .i2s_asrc_fs_mask = 0x1f,
1440 1361
1441 }, 1362 },
1442 { 1363 {
1443 .i2s_ctrl_reg = ASYS_I2SIN4_CON, 1364 .i2s_ctrl_reg = ASYS_I2SIN4_CON,
1444 .i2s_pwn_shift = 3,
1445 .i2s_asrc_fs_shift = 15, 1365 .i2s_asrc_fs_shift = 15,
1446 .i2s_asrc_fs_mask = 0x1f, 1366 .i2s_asrc_fs_mask = 0x1f,
1447 1367
@@ -1449,14 +1369,6 @@ static const struct mt2701_i2s_data mt2701_i2s_data[MT2701_I2S_NUM][2] = {
1449 }, 1369 },
1450}; 1370};
1451 1371
1452static const struct regmap_config mt2701_afe_regmap_config = {
1453 .reg_bits = 32,
1454 .reg_stride = 4,
1455 .val_bits = 32,
1456 .max_register = AFE_END_ADDR,
1457 .cache_type = REGCACHE_NONE,
1458};
1459
1460static irqreturn_t mt2701_asys_isr(int irq_id, void *dev) 1372static irqreturn_t mt2701_asys_isr(int irq_id, void *dev)
1461{ 1373{
1462 int id; 1374 int id;
@@ -1483,8 +1395,7 @@ static int mt2701_afe_runtime_suspend(struct device *dev)
1483{ 1395{
1484 struct mtk_base_afe *afe = dev_get_drvdata(dev); 1396 struct mtk_base_afe *afe = dev_get_drvdata(dev);
1485 1397
1486 mt2701_afe_disable_clock(afe); 1398 return mt2701_afe_disable_clock(afe);
1487 return 0;
1488} 1399}
1489 1400
1490static int mt2701_afe_runtime_resume(struct device *dev) 1401static int mt2701_afe_runtime_resume(struct device *dev)
@@ -1496,21 +1407,22 @@ static int mt2701_afe_runtime_resume(struct device *dev)
1496 1407
1497static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev) 1408static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1498{ 1409{
1410 struct snd_soc_component *component;
1499 struct mtk_base_afe *afe; 1411 struct mtk_base_afe *afe;
1500 struct mt2701_afe_private *afe_priv; 1412 struct mt2701_afe_private *afe_priv;
1501 struct resource *res;
1502 struct device *dev; 1413 struct device *dev;
1503 int i, irq_id, ret; 1414 int i, irq_id, ret;
1504 1415
1505 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1416 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1506 if (!afe) 1417 if (!afe)
1507 return -ENOMEM; 1418 return -ENOMEM;
1419
1508 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1420 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1509 GFP_KERNEL); 1421 GFP_KERNEL);
1510 if (!afe->platform_priv) 1422 if (!afe->platform_priv)
1511 return -ENOMEM; 1423 return -ENOMEM;
1512 afe_priv = afe->platform_priv;
1513 1424
1425 afe_priv = afe->platform_priv;
1514 afe->dev = &pdev->dev; 1426 afe->dev = &pdev->dev;
1515 dev = afe->dev; 1427 dev = afe->dev;
1516 1428
@@ -1527,17 +1439,11 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1527 return ret; 1439 return ret;
1528 } 1440 }
1529 1441
1530 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1442 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1531 1443 if (IS_ERR(afe->regmap)) {
1532 afe->base_addr = devm_ioremap_resource(&pdev->dev, res); 1444 dev_err(dev, "could not get regmap from parent\n");
1533
1534 if (IS_ERR(afe->base_addr))
1535 return PTR_ERR(afe->base_addr);
1536
1537 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr,
1538 &mt2701_afe_regmap_config);
1539 if (IS_ERR(afe->regmap))
1540 return PTR_ERR(afe->regmap); 1445 return PTR_ERR(afe->regmap);
1446 }
1541 1447
1542 mutex_init(&afe->irq_alloc_lock); 1448 mutex_init(&afe->irq_alloc_lock);
1543 1449
@@ -1545,7 +1451,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1545 afe->memif_size = MT2701_MEMIF_NUM; 1451 afe->memif_size = MT2701_MEMIF_NUM;
1546 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 1452 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1547 GFP_KERNEL); 1453 GFP_KERNEL);
1548
1549 if (!afe->memif) 1454 if (!afe->memif)
1550 return -ENOMEM; 1455 return -ENOMEM;
1551 1456
@@ -1558,7 +1463,6 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1558 afe->irqs_size = MT2701_IRQ_ASYS_END; 1463 afe->irqs_size = MT2701_IRQ_ASYS_END;
1559 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 1464 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1560 GFP_KERNEL); 1465 GFP_KERNEL);
1561
1562 if (!afe->irqs) 1466 if (!afe->irqs)
1563 return -ENOMEM; 1467 return -ENOMEM;
1564 1468
@@ -1573,10 +1477,15 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1573 = &mt2701_i2s_data[i][I2S_IN]; 1477 = &mt2701_i2s_data[i][I2S_IN];
1574 } 1478 }
1575 1479
1480 component = kzalloc(sizeof(*component), GFP_KERNEL);
1481 if (!component)
1482 return -ENOMEM;
1483
1484 component->regmap = afe->regmap;
1485
1576 afe->mtk_afe_hardware = &mt2701_afe_hardware; 1486 afe->mtk_afe_hardware = &mt2701_afe_hardware;
1577 afe->memif_fs = mt2701_memif_fs; 1487 afe->memif_fs = mt2701_memif_fs;
1578 afe->irq_fs = mt2701_irq_fs; 1488 afe->irq_fs = mt2701_irq_fs;
1579
1580 afe->reg_back_up_list = mt2701_afe_backup_list; 1489 afe->reg_back_up_list = mt2701_afe_backup_list;
1581 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list); 1490 afe->reg_back_up_list_num = ARRAY_SIZE(mt2701_afe_backup_list);
1582 afe->runtime_resume = mt2701_afe_runtime_resume; 1491 afe->runtime_resume = mt2701_afe_runtime_resume;
@@ -1586,7 +1495,7 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1586 ret = mt2701_init_clock(afe); 1495 ret = mt2701_init_clock(afe);
1587 if (ret) { 1496 if (ret) {
1588 dev_err(dev, "init clock error\n"); 1497 dev_err(dev, "init clock error\n");
1589 return ret; 1498 goto err_init_clock;
1590 } 1499 }
1591 1500
1592 platform_set_drvdata(pdev, afe); 1501 platform_set_drvdata(pdev, afe);
@@ -1605,10 +1514,10 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
1605 goto err_platform; 1514 goto err_platform;
1606 } 1515 }
1607 1516
1608 ret = snd_soc_register_component(&pdev->dev, 1517 ret = snd_soc_add_component(dev, component,
1609 &mt2701_afe_pcm_dai_component, 1518 &mt2701_afe_pcm_dai_component,
1610 mt2701_afe_pcm_dais, 1519 mt2701_afe_pcm_dais,
1611 ARRAY_SIZE(mt2701_afe_pcm_dais)); 1520 ARRAY_SIZE(mt2701_afe_pcm_dais));
1612 if (ret) { 1521 if (ret) {
1613 dev_warn(dev, "err_dai_component\n"); 1522 dev_warn(dev, "err_dai_component\n");
1614 goto err_dai_component; 1523 goto err_dai_component;
@@ -1622,6 +1531,8 @@ err_platform:
1622 pm_runtime_put_sync(dev); 1531 pm_runtime_put_sync(dev);
1623err_pm_disable: 1532err_pm_disable:
1624 pm_runtime_disable(dev); 1533 pm_runtime_disable(dev);
1534err_init_clock:
1535 kfree(component);
1625 1536
1626 return ret; 1537 return ret;
1627} 1538}
@@ -1667,4 +1578,3 @@ module_platform_driver(mt2701_afe_pcm_driver);
1667MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701"); 1578MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 2701");
1668MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>"); 1579MODULE_AUTHOR("Garlic Tseng <garlic.tseng@mediatek.com>");
1669MODULE_LICENSE("GPL v2"); 1580MODULE_LICENSE("GPL v2");
1670
diff --git a/sound/soc/mediatek/mt2701/mt2701-reg.h b/sound/soc/mediatek/mt2701/mt2701-reg.h
index bb62b1c55957..18e676974f22 100644
--- a/sound/soc/mediatek/mt2701/mt2701-reg.h
+++ b/sound/soc/mediatek/mt2701/mt2701-reg.h
@@ -17,17 +17,6 @@
17#ifndef _MT2701_REG_H_ 17#ifndef _MT2701_REG_H_
18#define _MT2701_REG_H_ 18#define _MT2701_REG_H_
19 19
20#include <linux/delay.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/pm_runtime.h>
25#include <sound/soc.h>
26#include "mt2701-afe-common.h"
27
28/*****************************************************************************
29 * R E G I S T E R D E F I N I T I O N
30 *****************************************************************************/
31#define AUDIO_TOP_CON0 0x0000 20#define AUDIO_TOP_CON0 0x0000
32#define AUDIO_TOP_CON4 0x0010 21#define AUDIO_TOP_CON4 0x0010
33#define AUDIO_TOP_CON5 0x0014 22#define AUDIO_TOP_CON5 0x0014
@@ -109,18 +98,6 @@
109#define AFE_DAI_BASE 0x1370 98#define AFE_DAI_BASE 0x1370
110#define AFE_DAI_CUR 0x137c 99#define AFE_DAI_CUR 0x137c
111 100
112/* AUDIO_TOP_CON0 (0x0000) */
113#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
114#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
115#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
116
117/* AUDIO_TOP_CON4 (0x0010) */
118#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
119#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
120#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
121#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
122#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
123
124/* AFE_DAIBT_CON0 (0x001c) */ 101/* AFE_DAIBT_CON0 (0x001c) */
125#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0) 102#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
126#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1) 103#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
@@ -137,22 +114,8 @@
137#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20) 114#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
138#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20) 115#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
139 116
140/* ASYS_I2SO1_CON (0x061c) */ 117/* ASYS_TOP_CON (0x0600) */
141#define ASYS_I2SO1_CON_FS (0x1f << 8) 118#define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
142#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
143#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
144#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
145#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
146/* 0:EIAJ 1:I2S */
147#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
148#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
149#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
150
151/* PWR2_TOP_CON (0x0634) */
152#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
153
154/* ASYS_IRQ_CLR (0x07c0) */
155#define ASYS_IRQ_CLR_ALL (0xffffffff)
156 119
157/* PWR2_ASM_CON1 (0x1070) */ 120/* PWR2_ASM_CON1 (0x1070) */
158#define PWR2_ASM_CON1_INIT_VAL (0x492492) 121#define PWR2_ASM_CON1_INIT_VAL (0x492492)
@@ -182,5 +145,4 @@
182#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1) 145#define ASYS_I2S_CON_WIDE_MODE_SET(x) ((x) << 1)
183#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31) 146#define ASYS_I2S_IN_PHASE_FIX (0x1 << 31)
184 147
185#define AFE_END_ADDR 0x15e0
186#endif 148#endif
diff --git a/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c b/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
index 8a643a35d3d4..c7f7f8add5d9 100644
--- a/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
+++ b/sound/soc/mediatek/mt8173/mt8173-afe-pcm.c
@@ -1083,7 +1083,7 @@ static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe)
1083static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) 1083static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1084{ 1084{
1085 int ret, i; 1085 int ret, i;
1086 unsigned int irq_id; 1086 int irq_id;
1087 struct mtk_base_afe *afe; 1087 struct mtk_base_afe *afe;
1088 struct mt8173_afe_private *afe_priv; 1088 struct mt8173_afe_private *afe_priv;
1089 struct resource *res; 1089 struct resource *res;
@@ -1105,9 +1105,9 @@ static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev)
1105 afe->dev = &pdev->dev; 1105 afe->dev = &pdev->dev;
1106 1106
1107 irq_id = platform_get_irq(pdev, 0); 1107 irq_id = platform_get_irq(pdev, 0);
1108 if (!irq_id) { 1108 if (irq_id <= 0) {
1109 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name); 1109 dev_err(afe->dev, "np %s no irq\n", afe->dev->of_node->name);
1110 return -ENXIO; 1110 return irq_id < 0 ? irq_id : -ENXIO;
1111 } 1111 }
1112 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler, 1112 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler,
1113 0, "Afe_ISR_Handle", (void *)afe); 1113 0, "Afe_ISR_Handle", (void *)afe);
diff --git a/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c b/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
index 99c15219dbc8..5a9a5482976e 100644
--- a/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
+++ b/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5514.c
@@ -37,8 +37,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5514_routes[] = {
37 {"Sub DMIC1R", NULL, "Int Mic"}, 37 {"Sub DMIC1R", NULL, "Int Mic"},
38 {"Headphone", NULL, "HPOL"}, 38 {"Headphone", NULL, "HPOL"},
39 {"Headphone", NULL, "HPOR"}, 39 {"Headphone", NULL, "HPOR"},
40 {"Headset Mic", NULL, "micbias1"},
41 {"Headset Mic", NULL, "micbias2"},
42 {"IN1P", NULL, "Headset Mic"}, 40 {"IN1P", NULL, "Headset Mic"},
43 {"IN1N", NULL, "Headset Mic"}, 41 {"IN1N", NULL, "Headset Mic"},
44}; 42};
diff --git a/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c b/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
index 42de84ca8c84..b7248085ca04 100644
--- a/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
+++ b/sound/soc/mediatek/mt8173/mt8173-rt5650-rt5676.c
@@ -40,8 +40,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_rt5676_routes[] = {
40 {"Headphone", NULL, "HPOL"}, 40 {"Headphone", NULL, "HPOL"},
41 {"Headphone", NULL, "HPOR"}, 41 {"Headphone", NULL, "HPOR"},
42 {"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */ 42 {"Headphone", NULL, "Sub AIF2TX"}, /* IF2 ADC to 5650 */
43 {"Headset Mic", NULL, "micbias1"},
44 {"Headset Mic", NULL, "micbias2"},
45 {"IN1P", NULL, "Headset Mic"}, 43 {"IN1P", NULL, "Headset Mic"},
46 {"IN1N", NULL, "Headset Mic"}, 44 {"IN1N", NULL, "Headset Mic"},
47 {"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */ 45 {"Sub AIF2RX", NULL, "Headset Mic"}, /* IF2 DAC from 5650 */
diff --git a/sound/soc/mediatek/mt8173/mt8173-rt5650.c b/sound/soc/mediatek/mt8173/mt8173-rt5650.c
index e69c141d8ed4..40ebefd625c1 100644
--- a/sound/soc/mediatek/mt8173/mt8173-rt5650.c
+++ b/sound/soc/mediatek/mt8173/mt8173-rt5650.c
@@ -51,8 +51,6 @@ static const struct snd_soc_dapm_route mt8173_rt5650_routes[] = {
51 {"DMIC R1", NULL, "Int Mic"}, 51 {"DMIC R1", NULL, "Int Mic"},
52 {"Headphone", NULL, "HPOL"}, 52 {"Headphone", NULL, "HPOL"},
53 {"Headphone", NULL, "HPOR"}, 53 {"Headphone", NULL, "HPOR"},
54 {"Headset Mic", NULL, "micbias1"},
55 {"Headset Mic", NULL, "micbias2"},
56 {"IN1P", NULL, "Headset Mic"}, 54 {"IN1P", NULL, "Headset Mic"},
57 {"IN1N", NULL, "Headset Mic"}, 55 {"IN1N", NULL, "Headset Mic"},
58}; 56};
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-05 16:09:45 -0400