diff options
| -rw-r--r-- | drivers/gpu/drm/tegra/hdmi.c | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 81ea934214f1..e060c7e6434d 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c | |||
| @@ -149,7 +149,7 @@ struct tmds_config { | |||
| 149 | }; | 149 | }; |
| 150 | 150 | ||
| 151 | static const struct tmds_config tegra2_tmds_config[] = { | 151 | static const struct tmds_config tegra2_tmds_config[] = { |
| 152 | { /* 480p modes */ | 152 | { /* slow pixel clock modes */ |
| 153 | .pclk = 27000000, | 153 | .pclk = 27000000, |
| 154 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | 154 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 155 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | | 155 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | |
| @@ -163,21 +163,8 @@ static const struct tmds_config tegra2_tmds_config[] = { | |||
| 163 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | | 163 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | |
| 164 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | | 164 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | |
| 165 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), | 165 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), |
| 166 | }, { /* 720p modes */ | 166 | }, |
| 167 | .pclk = 74250000, | 167 | { /* high pixel clock modes */ |
| 168 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | ||
| 169 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | | ||
| 170 | SOR_PLL_TX_REG_LOAD(3), | ||
| 171 | .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, | ||
| 172 | .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | | ||
| 173 | PE_CURRENT1(PE_CURRENT_6_0_mA) | | ||
| 174 | PE_CURRENT2(PE_CURRENT_6_0_mA) | | ||
| 175 | PE_CURRENT3(PE_CURRENT_6_0_mA), | ||
| 176 | .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | | ||
| 177 | DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | | ||
| 178 | DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | | ||
| 179 | DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), | ||
| 180 | }, { /* 1080p modes */ | ||
| 181 | .pclk = UINT_MAX, | 168 | .pclk = UINT_MAX, |
| 182 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | | 169 | .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | |
| 183 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | | 170 | SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | |
