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-rw-r--r--Documentation/devicetree/bindings/arm/armadeus.txt6
-rw-r--r--Documentation/devicetree/bindings/arm/fsl.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/imx5-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/w1/fsl-imx-owire.txt19
-rw-r--r--arch/arm/boot/dts/Makefile10
-rw-r--r--arch/arm/boot/dts/imx25-karo-tx25.dts30
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts36
-rw-r--r--arch/arm/boot/dts/imx25.dtsi2
-rw-r--r--arch/arm/boot/dts/imx27-apf27.dts82
-rw-r--r--arch/arm/boot/dts/imx27-pdk.dts (renamed from arch/arm/boot/dts/imx27-3ds.dts)24
-rw-r--r--arch/arm/boot/dts/imx31-bug.dts12
-rw-r--r--arch/arm/boot/dts/imx51-apf51.dts52
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts478
-rw-r--r--arch/arm/boot/dts/imx51.dtsi53
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts126
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts194
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts130
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts380
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts294
-rw-r--r--arch/arm/boot/dts/imx53-tqma53.dtsi172
-rw-r--r--arch/arm/boot/dts/imx53.dtsi68
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi59
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts124
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts64
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts216
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts102
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi796
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi800
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c4
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c26
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c65
-rw-r--r--drivers/w1/masters/mxc_w1.c9
33 files changed, 2560 insertions, 1884 deletions
diff --git a/Documentation/devicetree/bindings/arm/armadeus.txt b/Documentation/devicetree/bindings/arm/armadeus.txt
new file mode 100644
index 000000000000..9821283ff516
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armadeus.txt
@@ -0,0 +1,6 @@
1Armadeus i.MX Platforms Device Tree Bindings
2-----------------------------------------------
3
4APF51: i.MX51 based module.
5Required root node properties:
6 - compatible = "armadeus,imx51-apf51", "fsl,imx51";
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index f79818711e83..e935d7d4ac43 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -5,6 +5,14 @@ i.MX23 Evaluation Kit
5Required root node properties: 5Required root node properties:
6 - compatible = "fsl,imx23-evk", "fsl,imx23"; 6 - compatible = "fsl,imx23-evk", "fsl,imx23";
7 7
8i.MX25 Product Development Kit
9Required root node properties:
10 - compatible = "fsl,imx25-pdk", "fsl,imx25";
11
12i.MX27 Product Development Kit
13Required root node properties:
14 - compatible = "fsl,imx27-pdk", "fsl,imx27";
15
8i.MX28 Evaluation Kit 16i.MX28 Evaluation Kit
9Required root node properties: 17Required root node properties:
10 - compatible = "fsl,imx28-evk", "fsl,imx28"; 18 - compatible = "fsl,imx28-evk", "fsl,imx28";
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index 04ad47876be0..2a0c904c46ae 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -171,6 +171,7 @@ clocks and IDs.
171 can_sel 156 171 can_sel 156
172 can1_serial_gate 157 172 can1_serial_gate 157
173 can1_ipg_gate 158 173 can1_ipg_gate 158
174 owire_gate 159
174 175
175Examples (for mx53): 176Examples (for mx53):
176 177
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index f73fdf595568..969b38e06ad3 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -203,6 +203,8 @@ clocks and IDs.
203 pcie_ref 188 203 pcie_ref 188
204 pcie_ref_125m 189 204 pcie_ref_125m 189
205 enet_ref 190 205 enet_ref 190
206 usbphy1_gate 191
207 usbphy2_gate 192
206 208
207Examples: 209Examples:
208 210
diff --git a/Documentation/devicetree/bindings/w1/fsl-imx-owire.txt b/Documentation/devicetree/bindings/w1/fsl-imx-owire.txt
new file mode 100644
index 000000000000..ecf42c07684d
--- /dev/null
+++ b/Documentation/devicetree/bindings/w1/fsl-imx-owire.txt
@@ -0,0 +1,19 @@
1* Freescale i.MX One wire bus master controller
2
3Required properties:
4- compatible : should be "fsl,imx21-owire"
5- reg : Address and length of the register set for the device
6
7Optional properties:
8- clocks : phandle of clock that supplies the module (required if platform
9 clock bindings use device tree)
10
11Example:
12
13- From imx53.dtsi:
14owire: owire@63fa4000 {
15 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
16 reg = <0x63fa4000 0x4000>;
17 clocks = <&clks 159>;
18 status = "disabled";
19};
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 411ab1614a0e..e007134cc2ca 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -80,9 +80,17 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
80 armada-370-mirabox.dtb \ 80 armada-370-mirabox.dtb \
81 armada-xp-db.dtb \ 81 armada-xp-db.dtb \
82 armada-xp-openblocks-ax3-4.dtb 82 armada-xp-openblocks-ax3-4.dtb
83dtb-$(CONFIG_ARCH_MXC) += imx51-babbage.dtb \ 83dtb-$(CONFIG_ARCH_MXC) += \
84 imx25-karo-tx25.dtb \
85 imx25-pdk.dtb \
86 imx27-apf27.dtb \
87 imx27-pdk.dtb \
88 imx31-bug.dtb \
89 imx51-apf51.dtb \
90 imx51-babbage.dtb \
84 imx53-ard.dtb \ 91 imx53-ard.dtb \
85 imx53-evk.dtb \ 92 imx53-evk.dtb \
93 imx53-mba53.dtb \
86 imx53-qsb.dtb \ 94 imx53-qsb.dtb \
87 imx53-smd.dtb \ 95 imx53-smd.dtb \
88 imx6q-arm2.dtb \ 96 imx6q-arm2.dtb \
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index d81f8a0b9794..1a9d0491cdce 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -19,26 +19,18 @@
19 memory { 19 memory {
20 reg = <0x80000000 0x02000000 0x90000000 0x02000000>; 20 reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
21 }; 21 };
22};
22 23
23 soc { 24&uart1 {
24 aips@43f00000 { 25 status = "okay";
25 uart1: serial@43f90000 { 26};
26 status = "okay";
27 };
28 };
29 27
30 spba@50000000 { 28&fec {
31 fec: ethernet@50038000 { 29 phy-mode = "rmii";
32 status = "okay"; 30 status = "okay";
33 phy-mode = "rmii"; 31};
34 };
35 };
36 32
37 emi@80000000 { 33&nfc {
38 nand@bb000000 { 34 nand-on-flash-bbt;
39 nand-on-flash-bbt; 35 status = "okay";
40 status = "okay";
41 };
42 };
43 };
44}; 36};
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
new file mode 100644
index 000000000000..a02a860afd18
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -0,0 +1,36 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "imx25.dtsi"
14
15/ {
16 model = "Freescale i.MX25 Product Development Kit";
17 compatible = "fsl,imx25-pdk", "fsl,imx25";
18
19 memory {
20 reg = <0x80000000 0x4000000>;
21 };
22};
23
24&uart1 {
25 status = "okay";
26};
27
28&fec {
29 phy-mode = "rmii";
30 status = "okay";
31};
32
33&nfc {
34 nand-on-flash-bbt;
35 status = "okay";
36};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index e1b13ebc96d6..94f33059158a 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -499,7 +499,7 @@
499 reg = <0x80000000 0x3b002000>; 499 reg = <0x80000000 0x3b002000>;
500 ranges; 500 ranges;
501 501
502 nand@bb000000 { 502 nfc: nand@bb000000 {
503 #address-cells = <1>; 503 #address-cells = <1>;
504 #size-cells = <1>; 504 #size-cells = <1>;
505 505
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index c0327c054de2..b464c807d8d9 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -32,58 +32,54 @@
32 clock-frequency = <0>; 32 clock-frequency = <0>;
33 }; 33 };
34 }; 34 };
35};
35 36
36 soc { 37&uart1 {
37 aipi@10000000 { 38 status = "okay";
38 serial@1000a000 { 39};
39 status = "okay";
40 };
41 40
42 ethernet@1002b000 { 41&fec {
43 status = "okay"; 42 status = "okay";
44 }; 43};
45 };
46 44
47 nand@d8000000 { 45&nfc {
48 status = "okay"; 46 status = "okay";
49 nand-bus-width = <16>; 47 nand-bus-width = <16>;
50 nand-ecc-mode = "hw"; 48 nand-ecc-mode = "hw";
51 nand-on-flash-bbt; 49 nand-on-flash-bbt;
52 50
53 partition@0 { 51 partition@0 {
54 label = "u-boot"; 52 label = "u-boot";
55 reg = <0x0 0x100000>; 53 reg = <0x0 0x100000>;
56 }; 54 };
57 55
58 partition@100000 { 56 partition@100000 {
59 label = "env"; 57 label = "env";
60 reg = <0x100000 0x80000>; 58 reg = <0x100000 0x80000>;
61 }; 59 };
62 60
63 partition@180000 { 61 partition@180000 {
64 label = "env2"; 62 label = "env2";
65 reg = <0x180000 0x80000>; 63 reg = <0x180000 0x80000>;
66 }; 64 };
67 65
68 partition@200000 { 66 partition@200000 {
69 label = "firmware"; 67 label = "firmware";
70 reg = <0x200000 0x80000>; 68 reg = <0x200000 0x80000>;
71 }; 69 };
72 70
73 partition@280000 { 71 partition@280000 {
74 label = "dtb"; 72 label = "dtb";
75 reg = <0x280000 0x80000>; 73 reg = <0x280000 0x80000>;
76 }; 74 };
77 75
78 partition@300000 { 76 partition@300000 {
79 label = "kernel"; 77 label = "kernel";
80 reg = <0x300000 0x500000>; 78 reg = <0x300000 0x500000>;
81 }; 79 };
82 80
83 partition@800000 { 81 partition@800000 {
84 label = "rootfs"; 82 label = "rootfs";
85 reg = <0x800000 0xf800000>; 83 reg = <0x800000 0xf800000>;
86 };
87 };
88 }; 84 };
89}; 85};
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-pdk.dts
index fa04c7b18bcb..41cd1105608e 100644
--- a/arch/arm/boot/dts/imx27-3ds.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -13,25 +13,19 @@
13/include/ "imx27.dtsi" 13/include/ "imx27.dtsi"
14 14
15/ { 15/ {
16 model = "mx27_3ds"; 16 model = "Freescale i.MX27 Product Development Kit";
17 compatible = "freescale,imx27-3ds", "fsl,imx27"; 17 compatible = "fsl,imx27-pdk", "fsl,imx27";
18 18
19 memory { 19 memory {
20 reg = <0x0 0x0>; 20 reg = <0x0 0x0>;
21 }; 21 };
22};
22 23
23 soc { 24&uart1 {
24 aipi@10000000 { /* aipi1 */ 25 fsl,uart-has-rtscts;
25 uart1: serial@1000a000 { 26 status = "okay";
26 fsl,uart-has-rtscts; 27};
27 status = "okay";
28 };
29 };
30 28
31 aipi@10020000 { /* aipi2 */ 29&fec {
32 ethernet@1002b000 { 30 status = "okay";
33 status = "okay";
34 };
35 };
36 };
37}; 31};
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index 7f67402328d3..9ac6f6ba1d64 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -19,13 +19,9 @@
19 memory { 19 memory {
20 reg = <0x80000000 0x8000000>; /* 128M */ 20 reg = <0x80000000 0x8000000>; /* 128M */
21 }; 21 };
22};
22 23
23 soc { 24&uart5 {
24 aips@43f00000 { /* AIPS1 */ 25 fsl,uart-has-rtscts;
25 uart5: serial@43fb4000 { 26 status = "okay";
26 fsl,uart-has-rtscts;
27 status = "okay";
28 };
29 };
30 };
31}; 27};
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
new file mode 100644
index 000000000000..92d3a66a69e2
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2012 Armadeus Systems - <support@armadeus.com>
3 * Copyright 2012 Laurent Cans <laurent.cans@gmail.com>
4 *
5 * Based on mx51-babbage.dts
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 * Copyright 2011 Linaro Ltd.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17/dts-v1/;
18/include/ "imx51.dtsi"
19
20/ {
21 model = "Armadeus Systems APF51 module";
22 compatible = "armadeus,imx51-apf51", "fsl,imx51";
23
24 memory {
25 reg = <0x90000000 0x20000000>;
26 };
27
28 clocks {
29 ckih1 {
30 clock-frequency = <0>;
31 };
32
33 osc {
34 clock-frequency = <33554432>;
35 };
36 };
37};
38
39&fec {
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_fec_2>;
42 phy-mode = "mii";
43 phy-reset-gpios = <&gpio3 0 0>;
44 phy-reset-duration = <1>;
45 status = "okay";
46};
47
48&uart3 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_uart3_2>;
51 status = "okay";
52};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 567e7ee72f91..aab6e43219af 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,239 +21,20 @@
21 reg = <0x90000000 0x20000000>; 21 reg = <0x90000000 0x20000000>;
22 }; 22 };
23 23
24 soc { 24 display@di0 {
25 display@di0 { 25 compatible = "fsl,imx-parallel-display";
26 compatible = "fsl,imx-parallel-display"; 26 crtcs = <&ipu 0>;
27 crtcs = <&ipu 0>; 27 interface-pix-fmt = "rgb24";
28 interface-pix-fmt = "rgb24"; 28 pinctrl-names = "default";
29 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_ipu_disp1_1>;
30 pinctrl-0 = <&pinctrl_ipu_disp1_1>; 30 };
31 };
32
33 display@di1 {
34 compatible = "fsl,imx-parallel-display";
35 crtcs = <&ipu 1>;
36 interface-pix-fmt = "rgb565";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
39 };
40
41 aips@70000000 { /* aips-1 */
42 spba@70000000 {
43 esdhc@70004000 { /* ESDHC1 */
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_esdhc1_1>;
46 fsl,cd-controller;
47 fsl,wp-controller;
48 status = "okay";
49 };
50
51 esdhc@70008000 { /* ESDHC2 */
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_esdhc2_1>;
54 cd-gpios = <&gpio1 6 0>;
55 wp-gpios = <&gpio1 5 0>;
56 status = "okay";
57 };
58
59 uart3: serial@7000c000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_uart3_1>;
62 fsl,uart-has-rtscts;
63 status = "okay";
64 };
65
66 ecspi@70010000 { /* ECSPI1 */
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_ecspi1_1>;
69 fsl,spi-num-chipselects = <2>;
70 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
71 status = "okay";
72
73 pmic: mc13892@0 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "fsl,mc13892";
77 spi-max-frequency = <6000000>;
78 reg = <0>;
79 interrupt-parent = <&gpio1>;
80 interrupts = <8 0x4>;
81
82 regulators {
83 sw1_reg: sw1 {
84 regulator-min-microvolt = <600000>;
85 regulator-max-microvolt = <1375000>;
86 regulator-boot-on;
87 regulator-always-on;
88 };
89
90 sw2_reg: sw2 {
91 regulator-min-microvolt = <900000>;
92 regulator-max-microvolt = <1850000>;
93 regulator-boot-on;
94 regulator-always-on;
95 };
96
97 sw3_reg: sw3 {
98 regulator-min-microvolt = <1100000>;
99 regulator-max-microvolt = <1850000>;
100 regulator-boot-on;
101 regulator-always-on;
102 };
103
104 sw4_reg: sw4 {
105 regulator-min-microvolt = <1100000>;
106 regulator-max-microvolt = <1850000>;
107 regulator-boot-on;
108 regulator-always-on;
109 };
110
111 vpll_reg: vpll {
112 regulator-min-microvolt = <1050000>;
113 regulator-max-microvolt = <1800000>;
114 regulator-boot-on;
115 regulator-always-on;
116 };
117
118 vdig_reg: vdig {
119 regulator-min-microvolt = <1650000>;
120 regulator-max-microvolt = <1650000>;
121 regulator-boot-on;
122 };
123
124 vsd_reg: vsd {
125 regulator-min-microvolt = <1800000>;
126 regulator-max-microvolt = <3150000>;
127 };
128
129 vusb2_reg: vusb2 {
130 regulator-min-microvolt = <2400000>;
131 regulator-max-microvolt = <2775000>;
132 regulator-boot-on;
133 regulator-always-on;
134 };
135
136 vvideo_reg: vvideo {
137 regulator-min-microvolt = <2775000>;
138 regulator-max-microvolt = <2775000>;
139 };
140
141 vaudio_reg: vaudio {
142 regulator-min-microvolt = <2300000>;
143 regulator-max-microvolt = <3000000>;
144 };
145
146 vcam_reg: vcam {
147 regulator-min-microvolt = <2500000>;
148 regulator-max-microvolt = <3000000>;
149 };
150
151 vgen1_reg: vgen1 {
152 regulator-min-microvolt = <1200000>;
153 regulator-max-microvolt = <1200000>;
154 };
155
156 vgen2_reg: vgen2 {
157 regulator-min-microvolt = <1200000>;
158 regulator-max-microvolt = <3150000>;
159 regulator-always-on;
160 };
161
162 vgen3_reg: vgen3 {
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <2900000>;
165 regulator-always-on;
166 };
167 };
168 };
169
170 flash: at45db321d@1 {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
174 spi-max-frequency = <25000000>;
175 reg = <1>;
176
177 partition@0 {
178 label = "U-Boot";
179 reg = <0x0 0x40000>;
180 read-only;
181 };
182
183 partition@40000 {
184 label = "Kernel";
185 reg = <0x40000 0x3c0000>;
186 };
187 };
188 };
189
190 ssi2: ssi@70014000 {
191 fsl,mode = "i2s-slave";
192 status = "okay";
193 };
194 };
195
196 iomuxc@73fa8000 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_hog>;
199
200 hog {
201 pinctrl_hog: hoggrp {
202 fsl,pins = <
203 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
204 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
205 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
206 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
207 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
208 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
209 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
210 >;
211 };
212 };
213 };
214
215 uart1: serial@73fbc000 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart1_1>;
218 fsl,uart-has-rtscts;
219 status = "okay";
220 };
221
222 uart2: serial@73fc0000 {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pinctrl_uart2_1>;
225 status = "okay";
226 };
227 };
228
229 aips@80000000 { /* aips-2 */
230 i2c@83fc4000 { /* I2C2 */
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c2_1>;
233 status = "okay";
234
235 sgtl5000: codec@0a {
236 compatible = "fsl,sgtl5000";
237 reg = <0x0a>;
238 clock-frequency = <26000000>;
239 VDDA-supply = <&vdig_reg>;
240 VDDIO-supply = <&vvideo_reg>;
241 };
242 };
243
244 audmux@83fd0000 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_audmux_1>;
247 status = "okay";
248 };
249 31
250 ethernet@83fec000 { 32 display@di1 {
251 pinctrl-names = "default"; 33 compatible = "fsl,imx-parallel-display";
252 pinctrl-0 = <&pinctrl_fec_1>; 34 crtcs = <&ipu 1>;
253 phy-mode = "mii"; 35 interface-pix-fmt = "rgb565";
254 status = "okay"; 36 pinctrl-names = "default";
255 }; 37 pinctrl-0 = <&pinctrl_ipu_disp2_1>;
256 };
257 }; 38 };
258 39
259 gpio-keys { 40 gpio-keys {
@@ -281,3 +62,236 @@
281 mux-ext-port = <3>; 62 mux-ext-port = <3>;
282 }; 63 };
283}; 64};
65
66&esdhc1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_esdhc1_1>;
69 fsl,cd-controller;
70 fsl,wp-controller;
71 status = "okay";
72};
73
74&esdhc2 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_esdhc2_1>;
77 cd-gpios = <&gpio1 6 0>;
78 wp-gpios = <&gpio1 5 0>;
79 status = "okay";
80};
81
82&uart3 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart3_1>;
85 fsl,uart-has-rtscts;
86 status = "okay";
87};
88
89&ecspi1 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_ecspi1_1>;
92 fsl,spi-num-chipselects = <2>;
93 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
94 status = "okay";
95
96 pmic: mc13892@0 {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,mc13892";
100 spi-max-frequency = <6000000>;
101 reg = <0>;
102 interrupt-parent = <&gpio1>;
103 interrupts = <8 0x4>;
104
105 regulators {
106 sw1_reg: sw1 {
107 regulator-min-microvolt = <600000>;
108 regulator-max-microvolt = <1375000>;
109 regulator-boot-on;
110 regulator-always-on;
111 };
112
113 sw2_reg: sw2 {
114 regulator-min-microvolt = <900000>;
115 regulator-max-microvolt = <1850000>;
116 regulator-boot-on;
117 regulator-always-on;
118 };
119
120 sw3_reg: sw3 {
121 regulator-min-microvolt = <1100000>;
122 regulator-max-microvolt = <1850000>;
123 regulator-boot-on;
124 regulator-always-on;
125 };
126
127 sw4_reg: sw4 {
128 regulator-min-microvolt = <1100000>;
129 regulator-max-microvolt = <1850000>;
130 regulator-boot-on;
131 regulator-always-on;
132 };
133
134 vpll_reg: vpll {
135 regulator-min-microvolt = <1050000>;
136 regulator-max-microvolt = <1800000>;
137 regulator-boot-on;
138 regulator-always-on;
139 };
140
141 vdig_reg: vdig {
142 regulator-min-microvolt = <1650000>;
143 regulator-max-microvolt = <1650000>;
144 regulator-boot-on;
145 };
146
147 vsd_reg: vsd {
148 regulator-min-microvolt = <1800000>;
149 regulator-max-microvolt = <3150000>;
150 };
151
152 vusb2_reg: vusb2 {
153 regulator-min-microvolt = <2400000>;
154 regulator-max-microvolt = <2775000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 vvideo_reg: vvideo {
160 regulator-min-microvolt = <2775000>;
161 regulator-max-microvolt = <2775000>;
162 };
163
164 vaudio_reg: vaudio {
165 regulator-min-microvolt = <2300000>;
166 regulator-max-microvolt = <3000000>;
167 };
168
169 vcam_reg: vcam {
170 regulator-min-microvolt = <2500000>;
171 regulator-max-microvolt = <3000000>;
172 };
173
174 vgen1_reg: vgen1 {
175 regulator-min-microvolt = <1200000>;
176 regulator-max-microvolt = <1200000>;
177 };
178
179 vgen2_reg: vgen2 {
180 regulator-min-microvolt = <1200000>;
181 regulator-max-microvolt = <3150000>;
182 regulator-always-on;
183 };
184
185 vgen3_reg: vgen3 {
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <2900000>;
188 regulator-always-on;
189 };
190 };
191 };
192
193 flash: at45db321d@1 {
194 #address-cells = <1>;
195 #size-cells = <1>;
196 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
197 spi-max-frequency = <25000000>;
198 reg = <1>;
199
200 partition@0 {
201 label = "U-Boot";
202 reg = <0x0 0x40000>;
203 read-only;
204 };
205
206 partition@40000 {
207 label = "Kernel";
208 reg = <0x40000 0x3c0000>;
209 };
210 };
211};
212
213&ssi2 {
214 fsl,mode = "i2s-slave";
215 status = "okay";
216};
217
218&iomuxc {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_hog>;
221
222 hog {
223 pinctrl_hog: hoggrp {
224 fsl,pins = <
225 694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
226 697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
227 737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
228 740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
229 121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
230 402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
231 405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
232 >;
233 };
234 };
235};
236
237&uart1 {
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_uart1_1>;
240 fsl,uart-has-rtscts;
241 status = "okay";
242};
243
244&uart2 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_uart2_1>;
247 status = "okay";
248};
249
250&i2c2 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c2_1>;
253 status = "okay";
254
255 sgtl5000: codec@0a {
256 compatible = "fsl,sgtl5000";
257 reg = <0x0a>;
258 clock-frequency = <26000000>;
259 VDDA-supply = <&vdig_reg>;
260 VDDIO-supply = <&vvideo_reg>;
261 };
262};
263
264&audmux {
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_audmux_1>;
267 status = "okay";
268};
269
270&fec {
271 pinctrl-names = "default";
272 pinctrl-0 = <&pinctrl_fec_1>;
273 phy-mode = "mii";
274 status = "okay";
275};
276
277&kpp {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_kpp_1>;
280 linux,keymap = <0x00000067 /* KEY_UP */
281 0x0001006c /* KEY_DOWN */
282 0x00020072 /* KEY_VOLUMEDOWN */
283 0x00030066 /* KEY_HOME */
284 0x0100006a /* KEY_RIGHT */
285 0x01010069 /* KEY_LEFT */
286 0x0102001c /* KEY_ENTER */
287 0x01030073 /* KEY_VOLUMEUP */
288 0x02000040 /* KEY_F6 */
289 0x02010042 /* KEY_F8 */
290 0x02020043 /* KEY_F9 */
291 0x02030044 /* KEY_F10 */
292 0x0300003b /* KEY_F1 */
293 0x0301003c /* KEY_F2 */
294 0x0302003d /* KEY_F3 */
295 0x03030074>; /* KEY_POWER */
296 status = "okay";
297};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 1f5d45eff45e..fcf035bf7c5a 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -221,6 +221,14 @@
221 #interrupt-cells = <2>; 221 #interrupt-cells = <2>;
222 }; 222 };
223 223
224 kpp: kpp@73f94000 {
225 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
226 reg = <0x73f94000 0x4000>;
227 interrupts = <60>;
228 clocks = <&clks 0>;
229 status = "disabled";
230 };
231
224 wdog1: wdog@73f98000 { 232 wdog1: wdog@73f98000 {
225 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 233 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
226 reg = <0x73f98000 0x4000>; 234 reg = <0x73f98000 0x4000>;
@@ -273,6 +281,29 @@
273 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ 281 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
274 >; 282 >;
275 }; 283 };
284
285 pinctrl_fec_2: fecgrp-2 {
286 fsl,pins = <
287 589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
288 592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
289 594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
290 596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
291 598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
292 602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
293 604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
294 609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
295 618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
296 623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
297 628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
298 634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
299 639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
300 644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
301 649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
302 653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
303 657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
304 662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
305 >;
306 };
276 }; 307 };
277 308
278 ecspi1 { 309 ecspi1 {
@@ -409,6 +440,28 @@
409 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ 440 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
410 >; 441 >;
411 }; 442 };
443
444 pinctrl_uart3_2: uart3grp-2 {
445 fsl,pins = <
446 434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
447 430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
448 >;
449 };
450 };
451
452 kpp {
453 pinctrl_kpp_1: kppgrp-1 {
454 fsl,pins = <
455 438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
456 439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
457 440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
458 441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
459 442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */
460 444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */
461 446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */
462 448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */
463 >;
464 };
412 }; 465 };
413 }; 466 };
414 467
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 4be76f223526..e049fd0319e8 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -21,72 +21,6 @@
21 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
22 }; 22 };
23 23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_2>;
30 cd-gpios = <&gpio1 1 0>;
31 wp-gpios = <&gpio1 9 0>;
32 status = "okay";
33 };
34 };
35
36 iomuxc@53fa8000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_hog>;
39
40 hog {
41 pinctrl_hog: hoggrp {
42 fsl,pins = <
43 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
44 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
45 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
46 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
47 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
48 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
49 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
50 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
51 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
52 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
53 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
54 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
55 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
56 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
57 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
58 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
59 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
60 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
61 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
62 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
63 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
64 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
65 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
66 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
67 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
68 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
69 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
70 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
71 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
72 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
73 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
74 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
75 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
76 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
77 >;
78 };
79 };
80 };
81
82 uart1: serial@53fbc000 {
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart1_2>;
85 status = "okay";
86 };
87 };
88 };
89
90 eim-cs1@f4000000 { 24 eim-cs1@f4000000 {
91 #address-cells = <1>; 25 #address-cells = <1>;
92 #size-cells = <1>; 26 #size-cells = <1>;
@@ -162,3 +96,63 @@
162 }; 96 };
163 }; 97 };
164}; 98};
99
100&esdhc1 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_esdhc1_2>;
103 cd-gpios = <&gpio1 1 0>;
104 wp-gpios = <&gpio1 9 0>;
105 status = "okay";
106};
107
108&iomuxc {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_hog>;
111
112 hog {
113 pinctrl_hog: hoggrp {
114 fsl,pins = <
115 1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
116 1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
117 486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
118 739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
119 218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
120 226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
121 233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
122 241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
123 429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
124 435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
125 441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
126 448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
127 456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
128 464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
129 471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
130 477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
131 492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
132 500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
133 508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
134 516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
135 524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
136 532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
137 540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
138 548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
139 637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
140 642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
141 647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
142 652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
143 657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
144 662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
145 667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
146 611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
147 616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
148 607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
149 >;
150 };
151 };
152};
153
154&uart1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_uart1_2>;
157 status = "okay";
158};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index a124d1e25258..85a89b52f9b8 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -21,107 +21,6 @@
21 reg = <0x70000000 0x80000000>; 21 reg = <0x70000000 0x80000000>;
22 }; 22 };
23 23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
30 cd-gpios = <&gpio3 13 0>;
31 wp-gpios = <&gpio3 14 0>;
32 status = "okay";
33 };
34
35 ecspi@50010000 { /* ECSPI1 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_ecspi1_1>;
38 fsl,spi-num-chipselects = <2>;
39 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
40 status = "okay";
41
42 flash: at45db321d@1 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
46 spi-max-frequency = <25000000>;
47 reg = <1>;
48
49 partition@0 {
50 label = "U-Boot";
51 reg = <0x0 0x40000>;
52 read-only;
53 };
54
55 partition@40000 {
56 label = "Kernel";
57 reg = <0x40000 0x3c0000>;
58 };
59 };
60 };
61
62 esdhc@50020000 { /* ESDHC3 */
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_esdhc3_1>;
65 cd-gpios = <&gpio3 11 0>;
66 wp-gpios = <&gpio3 12 0>;
67 status = "okay";
68 };
69 };
70
71 iomuxc@53fa8000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_hog>;
74
75 hog {
76 pinctrl_hog: hoggrp {
77 fsl,pins = <
78 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
79 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
80 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
81 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
82 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
83 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
84 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
85 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
86 >;
87 };
88 };
89 };
90
91 uart1: serial@53fbc000 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart1_1>;
94 status = "okay";
95 };
96 };
97
98 aips@60000000 { /* AIPS2 */
99 i2c@63fc4000 { /* I2C2 */
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_i2c2_1>;
102 status = "okay";
103
104 pmic: mc13892@08 {
105 compatible = "fsl,mc13892", "fsl,mc13xxx";
106 reg = <0x08>;
107 };
108
109 codec: sgtl5000@0a {
110 compatible = "fsl,sgtl5000";
111 reg = <0x0a>;
112 };
113 };
114
115 ethernet@63fec000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_fec_1>;
118 phy-mode = "rmii";
119 phy-reset-gpios = <&gpio7 6 0>;
120 status = "okay";
121 };
122 };
123 };
124
125 leds { 24 leds {
126 compatible = "gpio-leds"; 25 compatible = "gpio-leds";
127 26
@@ -132,3 +31,96 @@
132 }; 31 };
133 }; 32 };
134}; 33};
34
35&esdhc1 {
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc1_1>;
38 cd-gpios = <&gpio3 13 0>;
39 wp-gpios = <&gpio3 14 0>;
40 status = "okay";
41};
42
43&ecspi1 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_ecspi1_1>;
46 fsl,spi-num-chipselects = <2>;
47 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
48 status = "okay";
49
50 flash: at45db321d@1 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
54 spi-max-frequency = <25000000>;
55 reg = <1>;
56
57 partition@0 {
58 label = "U-Boot";
59 reg = <0x0 0x40000>;
60 read-only;
61 };
62
63 partition@40000 {
64 label = "Kernel";
65 reg = <0x40000 0x3c0000>;
66 };
67 };
68};
69
70&esdhc3 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_esdhc3_1>;
73 cd-gpios = <&gpio3 11 0>;
74 wp-gpios = <&gpio3 12 0>;
75 status = "okay";
76};
77
78&iomuxc {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_hog>;
81
82 hog {
83 pinctrl_hog: hoggrp {
84 fsl,pins = <
85 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
86 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
87 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
88 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
89 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
90 705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
91 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
92 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
93 >;
94 };
95 };
96};
97
98&uart1 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_uart1_1>;
101 status = "okay";
102};
103
104&i2c2 {
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_i2c2_1>;
107 status = "okay";
108
109 pmic: mc13892@08 {
110 compatible = "fsl,mc13892", "fsl,mc13xxx";
111 reg = <0x08>;
112 };
113
114 codec: sgtl5000@0a {
115 compatible = "fsl,sgtl5000";
116 reg = <0x0a>;
117 };
118};
119
120&fec {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_fec_1>;
123 phy-mode = "rmii";
124 phy-reset-gpios = <&gpio7 6 0>;
125 status = "okay";
126};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
new file mode 100644
index 000000000000..e54fffd48369
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -0,0 +1,130 @@
1/*
2 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53-tqma53.dtsi"
15
16/ {
17 model = "TQ MBa53 starter kit";
18 compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
19};
20
21&iomuxc {
22 lvds1 {
23 pinctrl_lvds1_1: lvds1-grp1 {
24 fsl,pins = <730 0x10000 /* LVDS0_TX3 */
25 732 0x10000 /* LVDS0_CLK */
26 734 0x10000 /* LVDS0_TX2 */
27 736 0x10000 /* LVDS0_TX1 */
28 738 0x10000>; /* LVDS0_TX0 */
29 };
30
31 pinctrl_lvds1_2: lvds1-grp2 {
32 fsl,pins = <720 0x10000 /* LVDS1_TX3 */
33 722 0x10000 /* LVDS1_TX2 */
34 724 0x10000 /* LVDS1_CLK */
35 726 0x10000 /* LVDS1_TX1 */
36 728 0x10000>; /* LVDS1_TX0 */
37 };
38 };
39
40 disp1 {
41 pinctrl_disp1_1: disp1-grp1 {
42 fsl,pins = <689 0x10000 /* DISP1_DRDY */
43 482 0x10000 /* DISP1_HSYNC */
44 489 0x10000 /* DISP1_VSYNC */
45 684 0x10000 /* DISP1_DAT_0 */
46 515 0x10000 /* DISP1_DAT_22 */
47 523 0x10000 /* DISP1_DAT_23 */
48 543 0x10000 /* DISP1_DAT_21 */
49 553 0x10000 /* DISP1_DAT_20 */
50 558 0x10000 /* DISP1_DAT_19 */
51 564 0x10000 /* DISP1_DAT_18 */
52 570 0x10000 /* DISP1_DAT_17 */
53 575 0x10000 /* DISP1_DAT_16 */
54 580 0x10000 /* DISP1_DAT_15 */
55 585 0x10000 /* DISP1_DAT_14 */
56 590 0x10000 /* DISP1_DAT_13 */
57 595 0x10000 /* DISP1_DAT_12 */
58 628 0x10000 /* DISP1_DAT_11 */
59 634 0x10000 /* DISP1_DAT_10 */
60 639 0x10000 /* DISP1_DAT_9 */
61 644 0x10000 /* DISP1_DAT_8 */
62 649 0x10000 /* DISP1_DAT_7 */
63 654 0x10000 /* DISP1_DAT_6 */
64 659 0x10000 /* DISP1_DAT_5 */
65 664 0x10000 /* DISP1_DAT_4 */
66 669 0x10000 /* DISP1_DAT_3 */
67 674 0x10000 /* DISP1_DAT_2 */
68 679 0x10000 /* DISP1_DAT_1 */
69 684 0x10000>; /* DISP1_DAT_0 */
70 };
71 };
72};
73
74&cspi {
75 status = "okay";
76};
77
78&i2c2 {
79 codec: sgtl5000@a {
80 compatible = "fsl,sgtl5000";
81 reg = <0x0a>;
82 };
83
84 expander: pca9554@20 {
85 compatible = "pca9554";
86 reg = <0x20>;
87 interrupts = <109>;
88 };
89
90 sensor2: lm75@49 {
91 compatible = "lm75";
92 reg = <0x49>;
93 };
94};
95
96&fec {
97 status = "okay";
98};
99
100&esdhc2 {
101 status = "okay";
102};
103
104&uart3 {
105 status = "okay";
106};
107
108&ecspi1 {
109 status = "okay";
110};
111
112&uart1 {
113 status = "okay";
114};
115
116&uart2 {
117 status = "okay";
118};
119
120&can1 {
121 status = "okay";
122};
123
124&can2 {
125 status = "okay";
126};
127
128&i2c3 {
129 status = "okay";
130};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index b0075537195b..05cc5620436b 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -21,200 +21,6 @@
21 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
22 }; 22 };
23 23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
30 cd-gpios = <&gpio3 13 0>;
31 status = "okay";
32 };
33
34 ssi2: ssi@50014000 {
35 fsl,mode = "i2s-slave";
36 status = "okay";
37 };
38
39 esdhc@50020000 { /* ESDHC3 */
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_esdhc3_1>;
42 cd-gpios = <&gpio3 11 0>;
43 wp-gpios = <&gpio3 12 0>;
44 status = "okay";
45 };
46 };
47
48 iomuxc@53fa8000 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_hog>;
51
52 hog {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
56 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
57 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
58 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
59 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
60 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
61 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
62 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
63 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
64 >;
65 };
66
67 led_pin_gpio7_7: led_gpio7_7@0 {
68 fsl,pins = <
69 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
70 >;
71 };
72 };
73
74 };
75
76 uart1: serial@53fbc000 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_uart1_1>;
79 status = "okay";
80 };
81 };
82
83 aips@60000000 { /* AIPS2 */
84 i2c@63fc4000 { /* I2C2 */
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_i2c2_1>;
87 status = "okay";
88
89 sgtl5000: codec@0a {
90 compatible = "fsl,sgtl5000";
91 reg = <0x0a>;
92 VDDA-supply = <&reg_3p2v>;
93 VDDIO-supply = <&reg_3p2v>;
94 };
95 };
96
97 i2c@63fc8000 { /* I2C1 */
98 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_i2c1_1>;
100 status = "okay";
101
102 accelerometer: mma8450@1c {
103 compatible = "fsl,mma8450";
104 reg = <0x1c>;
105 };
106
107 pmic: dialog@48 {
108 compatible = "dlg,da9053-aa", "dlg,da9052";
109 reg = <0x48>;
110 interrupt-parent = <&gpio7>;
111 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
112
113 regulators {
114 buck1_reg: buck1 {
115 regulator-min-microvolt = <500000>;
116 regulator-max-microvolt = <2075000>;
117 regulator-always-on;
118 };
119
120 buck2_reg: buck2 {
121 regulator-min-microvolt = <500000>;
122 regulator-max-microvolt = <2075000>;
123 regulator-always-on;
124 };
125
126 buck3_reg: buck3 {
127 regulator-min-microvolt = <925000>;
128 regulator-max-microvolt = <2500000>;
129 regulator-always-on;
130 };
131
132 buck4_reg: buck4 {
133 regulator-min-microvolt = <925000>;
134 regulator-max-microvolt = <2500000>;
135 regulator-always-on;
136 };
137
138 ldo1_reg: ldo1 {
139 regulator-min-microvolt = <600000>;
140 regulator-max-microvolt = <1800000>;
141 regulator-boot-on;
142 regulator-always-on;
143 };
144
145 ldo2_reg: ldo2 {
146 regulator-min-microvolt = <600000>;
147 regulator-max-microvolt = <1800000>;
148 regulator-always-on;
149 };
150
151 ldo3_reg: ldo3 {
152 regulator-min-microvolt = <600000>;
153 regulator-max-microvolt = <1800000>;
154 regulator-always-on;
155 };
156
157 ldo4_reg: ldo4 {
158 regulator-min-microvolt = <1725000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 ldo5_reg: ldo5 {
164 regulator-min-microvolt = <1725000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168
169 ldo6_reg: ldo6 {
170 regulator-min-microvolt = <1200000>;
171 regulator-max-microvolt = <3600000>;
172 regulator-always-on;
173 };
174
175 ldo7_reg: ldo7 {
176 regulator-min-microvolt = <1200000>;
177 regulator-max-microvolt = <3600000>;
178 regulator-always-on;
179 };
180
181 ldo8_reg: ldo8 {
182 regulator-min-microvolt = <1200000>;
183 regulator-max-microvolt = <3600000>;
184 regulator-always-on;
185 };
186
187 ldo9_reg: ldo9 {
188 regulator-min-microvolt = <1200000>;
189 regulator-max-microvolt = <3600000>;
190 regulator-always-on;
191 };
192
193 ldo10_reg: ldo10 {
194 regulator-min-microvolt = <1250000>;
195 regulator-max-microvolt = <3650000>;
196 regulator-always-on;
197 };
198 };
199 };
200 };
201
202 audmux@63fd0000 {
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_audmux_1>;
205 status = "okay";
206 };
207
208 ethernet@63fec000 {
209 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_fec_1>;
211 phy-mode = "rmii";
212 phy-reset-gpios = <&gpio7 6 0>;
213 status = "okay";
214 };
215 };
216 };
217
218 gpio-keys { 24 gpio-keys {
219 compatible = "gpio-keys"; 25 compatible = "gpio-keys";
220 26
@@ -276,3 +82,189 @@
276 mux-ext-port = <5>; 82 mux-ext-port = <5>;
277 }; 83 };
278}; 84};
85
86&esdhc1 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_esdhc1_1>;
89 cd-gpios = <&gpio3 13 0>;
90 status = "okay";
91};
92
93&ssi2 {
94 fsl,mode = "i2s-slave";
95 status = "okay";
96};
97
98&esdhc3 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_esdhc3_1>;
101 cd-gpios = <&gpio3 11 0>;
102 wp-gpios = <&gpio3 12 0>;
103 status = "okay";
104};
105
106&iomuxc {
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_hog>;
109
110 hog {
111 pinctrl_hog: hoggrp {
112 fsl,pins = <
113 1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
114 1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
115 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
116 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
117 693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
118 697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
119 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
120 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
121 1149 0x80000000 /* MX53_PAD_GPIO_16__GPIO7_11 */
122 >;
123 };
124
125 led_pin_gpio7_7: led_gpio7_7@0 {
126 fsl,pins = <
127 873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
128 >;
129 };
130 };
131
132};
133
134&uart1 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_uart1_1>;
137 status = "okay";
138};
139
140&i2c2 {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_i2c2_1>;
143 status = "okay";
144
145 sgtl5000: codec@0a {
146 compatible = "fsl,sgtl5000";
147 reg = <0x0a>;
148 VDDA-supply = <&reg_3p2v>;
149 VDDIO-supply = <&reg_3p2v>;
150 };
151};
152
153&i2c1 {
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c1_1>;
156 status = "okay";
157
158 accelerometer: mma8450@1c {
159 compatible = "fsl,mma8450";
160 reg = <0x1c>;
161 };
162
163 pmic: dialog@48 {
164 compatible = "dlg,da9053-aa", "dlg,da9052";
165 reg = <0x48>;
166 interrupt-parent = <&gpio7>;
167 interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
168
169 regulators {
170 buck1_reg: buck1 {
171 regulator-min-microvolt = <500000>;
172 regulator-max-microvolt = <2075000>;
173 regulator-always-on;
174 };
175
176 buck2_reg: buck2 {
177 regulator-min-microvolt = <500000>;
178 regulator-max-microvolt = <2075000>;
179 regulator-always-on;
180 };
181
182 buck3_reg: buck3 {
183 regulator-min-microvolt = <925000>;
184 regulator-max-microvolt = <2500000>;
185 regulator-always-on;
186 };
187
188 buck4_reg: buck4 {
189 regulator-min-microvolt = <925000>;
190 regulator-max-microvolt = <2500000>;
191 regulator-always-on;
192 };
193
194 ldo1_reg: ldo1 {
195 regulator-min-microvolt = <600000>;
196 regulator-max-microvolt = <1800000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 ldo2_reg: ldo2 {
202 regulator-min-microvolt = <600000>;
203 regulator-max-microvolt = <1800000>;
204 regulator-always-on;
205 };
206
207 ldo3_reg: ldo3 {
208 regulator-min-microvolt = <600000>;
209 regulator-max-microvolt = <1800000>;
210 regulator-always-on;
211 };
212
213 ldo4_reg: ldo4 {
214 regulator-min-microvolt = <1725000>;
215 regulator-max-microvolt = <3300000>;
216 regulator-always-on;
217 };
218
219 ldo5_reg: ldo5 {
220 regulator-min-microvolt = <1725000>;
221 regulator-max-microvolt = <3300000>;
222 regulator-always-on;
223 };
224
225 ldo6_reg: ldo6 {
226 regulator-min-microvolt = <1200000>;
227 regulator-max-microvolt = <3600000>;
228 regulator-always-on;
229 };
230
231 ldo7_reg: ldo7 {
232 regulator-min-microvolt = <1200000>;
233 regulator-max-microvolt = <3600000>;
234 regulator-always-on;
235 };
236
237 ldo8_reg: ldo8 {
238 regulator-min-microvolt = <1200000>;
239 regulator-max-microvolt = <3600000>;
240 regulator-always-on;
241 };
242
243 ldo9_reg: ldo9 {
244 regulator-min-microvolt = <1200000>;
245 regulator-max-microvolt = <3600000>;
246 regulator-always-on;
247 };
248
249 ldo10_reg: ldo10 {
250 regulator-min-microvolt = <1250000>;
251 regulator-max-microvolt = <3650000>;
252 regulator-always-on;
253 };
254 };
255 };
256};
257
258&audmux {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_audmux_1>;
261 status = "okay";
262};
263
264&fec {
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_fec_1>;
267 phy-mode = "rmii";
268 phy-reset-gpios = <&gpio7 6 0>;
269 status = "okay";
270};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 06c68580c842..995554c324b8 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -21,157 +21,6 @@
21 reg = <0x70000000 0x40000000>; 21 reg = <0x70000000 0x40000000>;
22 }; 22 };
23 23
24 soc {
25 aips@50000000 { /* AIPS1 */
26 spba@50000000 {
27 esdhc@50004000 { /* ESDHC1 */
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_esdhc1_1>;
30 cd-gpios = <&gpio3 13 0>;
31 wp-gpios = <&gpio4 11 0>;
32 status = "okay";
33 };
34
35 esdhc@50008000 { /* ESDHC2 */
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_esdhc2_1>;
38 non-removable;
39 status = "okay";
40 };
41
42 uart3: serial@5000c000 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_uart3_1>;
45 fsl,uart-has-rtscts;
46 status = "okay";
47 };
48
49 ecspi@50010000 { /* ECSPI1 */
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ecspi1_1>;
52 fsl,spi-num-chipselects = <2>;
53 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
54 status = "okay";
55
56 zigbee: mc1323@0 {
57 compatible = "fsl,mc1323";
58 spi-max-frequency = <8000000>;
59 reg = <0>;
60 };
61
62 flash: m25p32@1 {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "st,m25p32", "st,m25p";
66 spi-max-frequency = <20000000>;
67 reg = <1>;
68
69 partition@0 {
70 label = "U-Boot";
71 reg = <0x0 0x40000>;
72 read-only;
73 };
74
75 partition@40000 {
76 label = "Kernel";
77 reg = <0x40000 0x3c0000>;
78 };
79 };
80 };
81
82 esdhc@50020000 { /* ESDHC3 */
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_esdhc3_1>;
85 non-removable;
86 status = "okay";
87 };
88 };
89
90 iomuxc@53fa8000 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_hog>;
93
94 hog {
95 pinctrl_hog: hoggrp {
96 fsl,pins = <
97 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
98 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
99 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
100 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
101 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
102 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
103 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
104 >;
105 };
106 };
107 };
108
109 uart1: serial@53fbc000 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_uart1_1>;
112 status = "okay";
113 };
114
115 uart2: serial@53fc0000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart2_1>;
118 status = "okay";
119 };
120 };
121
122 aips@60000000 { /* AIPS2 */
123 i2c@63fc4000 { /* I2C2 */
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c2_1>;
126 status = "okay";
127
128 codec: sgtl5000@0a {
129 compatible = "fsl,sgtl5000";
130 reg = <0x0a>;
131 };
132
133 magnetometer: mag3110@0e {
134 compatible = "fsl,mag3110";
135 reg = <0x0e>;
136 };
137
138 touchkey: mpr121@5a {
139 compatible = "fsl,mpr121";
140 reg = <0x5a>;
141 };
142 };
143
144 i2c@63fc8000 { /* I2C1 */
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1_1>;
147 status = "okay";
148
149 accelerometer: mma8450@1c {
150 compatible = "fsl,mma8450";
151 reg = <0x1c>;
152 };
153
154 camera: ov5642@3c {
155 compatible = "ovti,ov5642";
156 reg = <0x3c>;
157 };
158
159 pmic: dialog@48 {
160 compatible = "dialog,da9053", "dialog,da9052";
161 reg = <0x48>;
162 };
163 };
164
165 ethernet@63fec000 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_fec_1>;
168 phy-mode = "rmii";
169 phy-reset-gpios = <&gpio7 6 0>;
170 status = "okay";
171 };
172 };
173 };
174
175 gpio-keys { 24 gpio-keys {
176 compatible = "gpio-keys"; 25 compatible = "gpio-keys";
177 26
@@ -188,3 +37,146 @@
188 }; 37 };
189 }; 38 };
190}; 39};
40
41&esdhc1 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_esdhc1_1>;
44 cd-gpios = <&gpio3 13 0>;
45 wp-gpios = <&gpio4 11 0>;
46 status = "okay";
47};
48
49&esdhc2 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_esdhc2_1>;
52 non-removable;
53 status = "okay";
54};
55
56&uart3 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_uart3_1>;
59 fsl,uart-has-rtscts;
60 status = "okay";
61};
62
63&ecspi1 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_ecspi1_1>;
66 fsl,spi-num-chipselects = <2>;
67 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
68 status = "okay";
69
70 zigbee: mc1323@0 {
71 compatible = "fsl,mc1323";
72 spi-max-frequency = <8000000>;
73 reg = <0>;
74 };
75
76 flash: m25p32@1 {
77 #address-cells = <1>;
78 #size-cells = <1>;
79 compatible = "st,m25p32", "st,m25p";
80 spi-max-frequency = <20000000>;
81 reg = <1>;
82
83 partition@0 {
84 label = "U-Boot";
85 reg = <0x0 0x40000>;
86 read-only;
87 };
88
89 partition@40000 {
90 label = "Kernel";
91 reg = <0x40000 0x3c0000>;
92 };
93 };
94};
95
96&esdhc3 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_esdhc3_1>;
99 non-removable;
100 status = "okay";
101};
102
103&iomuxc {
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_hog>;
106
107 hog {
108 pinctrl_hog: hoggrp {
109 fsl,pins = <
110 982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
111 989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
112 424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
113 701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
114 449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
115 43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
116 868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
117 >;
118 };
119 };
120};
121
122&uart1 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart1_1>;
125 status = "okay";
126};
127
128&uart2 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart2_1>;
131 status = "okay";
132};
133
134&i2c2 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c2_1>;
137 status = "okay";
138
139 codec: sgtl5000@0a {
140 compatible = "fsl,sgtl5000";
141 reg = <0x0a>;
142 };
143
144 magnetometer: mag3110@0e {
145 compatible = "fsl,mag3110";
146 reg = <0x0e>;
147 };
148
149 touchkey: mpr121@5a {
150 compatible = "fsl,mpr121";
151 reg = <0x5a>;
152 };
153};
154
155&i2c1 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_i2c1_1>;
158 status = "okay";
159
160 accelerometer: mma8450@1c {
161 compatible = "fsl,mma8450";
162 reg = <0x1c>;
163 };
164
165 camera: ov5642@3c {
166 compatible = "ovti,ov5642";
167 reg = <0x3c>;
168 };
169
170 pmic: dialog@48 {
171 compatible = "dialog,da9053", "dialog,da9052";
172 reg = <0x48>;
173 };
174};
175
176&fec {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_fec_1>;
179 phy-mode = "rmii";
180 phy-reset-gpios = <&gpio7 6 0>;
181 status = "okay";
182};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
new file mode 100644
index 000000000000..8278ec5ec222
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -0,0 +1,172 @@
1/*
2 * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "imx53.dtsi"
14
15/ {
16 model = "TQ TQMa53";
17 compatible = "tq,tqma53", "fsl,imx53";
18
19 memory {
20 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
21 };
22
23 regulators {
24 compatible = "simple-bus";
25
26 reg_3p3v: 3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-always-on;
32 };
33 };
34};
35
36&esdhc2 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_esdhc2_1>;
39 wp-gpios = <&gpio1 2 0>;
40 cd-gpios = <&gpio1 4 0>;
41 status = "disabled";
42};
43
44&uart3 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_uart3_2>;
47 status = "disabled";
48};
49
50&ecspi1 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_ecspi1_1>;
53 fsl,spi-num-chipselects = <4>;
54 cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
55 <&gpio3 24 0>, <&gpio3 25 0>;
56 status = "disabled";
57};
58
59&esdhc3 { /* EMMC */
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_esdhc3_1>;
62 vmmc-supply = <&reg_3p3v>;
63 non-removable;
64 bus-width = <8>;
65 status = "okay";
66};
67
68&iomuxc {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_hog>;
71
72 i2s {
73 pinctrl_i2s_1: i2s-grp1 {
74 fsl,pins = <
75 1 0x10000 /* I2S_MCLK */
76 10 0x10000 /* I2S_SCLK */
77 17 0x10000 /* I2S_DOUT */
78 23 0x10000 /* I2S_LRCLK*/
79 30 0x10000 /* I2S_DIN */
80 >;
81 };
82 };
83
84 hog {
85 pinctrl_hog: hoggrp {
86 fsl,pins = <
87 610 0x10000 /* MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (VSYNC)*/
88 711 0x10000 /* MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (HSYNC)*/
89 873 0x10000 /* MX53_PAD_PATA_DA_1__GPIO7_7 (LCD_BLT_EN)*/
90 878 0x10000 /* MX53_PAD_PATA_DA_2__GPIO7_8 (LCD_RESET)*/
91 922 0x10000 /* MX53_PAD_PATA_DATA5__GPIO2_5 (LCD_POWER)*/
92 928 0x10000 /* MX53_PAD_PATA_DATA6__GPIO2_6 (PMIC_INT)*/
93 982 0x10000 /* MX53_PAD_PATA_DATA14__GPIO2_14 (CSI_RST)*/
94 989 0x10000 /* MX53_PAD_PATA_DATA15__GPIO2_15 (CSI_PWDN)*/
95 1069 0x10000 /* MX53_PAD_GPIO_0__GPIO1_0 (SYSTEM_DOWN)*/
96 1093 0x10000 /* MX53_PAD_GPIO_3__GPIO1_3 */
97 >;
98 };
99 };
100};
101
102&uart1 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_uart1_2>;
105 fsl,uart-has-rtscts;
106 status = "disabled";
107};
108
109&uart2 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_uart2_1>;
112 status = "disabled";
113};
114
115&can1 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_can1_2>;
118 status = "disabled";
119};
120
121&can2 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_can2_1>;
124 status = "disabled";
125};
126
127&i2c3 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c3_1>;
130 status = "disabled";
131};
132
133&cspi {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_cspi_1>;
136 fsl,spi-num-chipselects = <3>;
137 cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
138 <&gpio1 21 0>;
139 status = "disabled";
140};
141
142&i2c2 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_i2c2_1>;
145 status = "okay";
146
147 pmic: mc34708@8 {
148 compatible = "fsl,mc34708";
149 reg = <0x8>;
150 fsl,mc13xxx-uses-rtc;
151 interrupt-parent = <&gpio2>;
152 interrupts = <6 8>; /* PDATA_DATA6, low active */
153 };
154
155 sensor1: lm75@48 {
156 compatible = "lm75";
157 reg = <0x48>;
158 };
159
160 eeprom: 24c64@50 {
161 compatible = "at,24c64";
162 pagesize = <32>;
163 reg = <0x50>;
164 };
165};
166
167&fec {
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_fec_1>;
170 phy-mode = "rmii";
171 status = "disabled";
172};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index edc3f1eb6699..d05aa215c7f9 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -274,6 +274,44 @@
274 }; 274 };
275 }; 275 };
276 276
277 csi {
278 pinctrl_csi_1: csigrp-1 {
279 fsl,pins = <
280 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */
281 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */
282 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */
283 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
284 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */
285 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */
286 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */
287 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */
288 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */
289 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */
290 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */
291 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */
292 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */
293 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */
294 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */
295 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */
296 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */
297 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */
298 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */
299 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */
300 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */
301 >;
302 };
303 };
304
305 cspi {
306 pinctrl_cspi_1: cspigrp-1 {
307 fsl,pins = <
308 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */
309 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */
310 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */
311 >;
312 };
313 };
314
277 ecspi1 { 315 ecspi1 {
278 pinctrl_ecspi1_1: ecspi1grp-1 { 316 pinctrl_ecspi1_1: ecspi1grp-1 {
279 fsl,pins = < 317 fsl,pins = <
@@ -349,6 +387,13 @@
349 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ 387 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */
350 >; 388 >;
351 }; 389 };
390
391 pinctrl_can1_2: can1grp-2 {
392 fsl,pins = <
393 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */
394 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */
395 >;
396 };
352 }; 397 };
353 398
354 can2 { 399 can2 {
@@ -387,6 +432,14 @@
387 }; 432 };
388 }; 433 };
389 434
435 owire {
436 pinctrl_owire_1: owiregrp-1 {
437 fsl,pins = <
438 1166 0x80000000 /* MX53_PAD_GPIO_18__OWIRE_LINE */
439 >;
440 };
441 };
442
390 uart1 { 443 uart1 {
391 pinctrl_uart1_1: uart1grp-1 { 444 pinctrl_uart1_1: uart1grp-1 {
392 fsl,pins = < 445 fsl,pins = <
@@ -421,6 +474,14 @@
421 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ 474 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
422 >; 475 >;
423 }; 476 };
477
478 pinctrl_uart3_2: uart3grp-2 {
479 fsl,pins = <
480 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
481 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
482 >;
483 };
484
424 }; 485 };
425 486
426 uart4 { 487 uart4 {
@@ -570,6 +631,13 @@
570 status = "disabled"; 631 status = "disabled";
571 }; 632 };
572 633
634 owire: owire@63fa4000 {
635 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
636 reg = <0x63fa4000 0x4000>;
637 clocks = <&clks 159>;
638 status = "disabled";
639 };
640
573 ecspi2: ecspi@63fac000 { 641 ecspi2: ecspi@63fac000 {
574 #address-cells = <1>; 642 #address-cells = <1>;
575 #size-cells = <0>; 643 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
new file mode 100644
index 000000000000..63fafe2a606c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -0,0 +1,59 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10/include/ "imx6qdl.dtsi"
11
12/ {
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 compatible = "arm,cortex-a9";
19 reg = <0>;
20 next-level-cache = <&L2>;
21 };
22
23 cpu@1 {
24 compatible = "arm,cortex-a9";
25 reg = <1>;
26 next-level-cache = <&L2>;
27 };
28 };
29
30 soc {
31 aips1: aips-bus@02000000 {
32 pxp: pxp@020f0000 {
33 reg = <0x020f0000 0x4000>;
34 interrupts = <0 98 0x04>;
35 };
36
37 epdc: epdc@020f4000 {
38 reg = <0x020f4000 0x4000>;
39 interrupts = <0 97 0x04>;
40 };
41
42 lcdif: lcdif@020f8000 {
43 reg = <0x020f8000 0x4000>;
44 interrupts = <0 39 0x04>;
45 };
46 };
47
48 aips2: aips-bus@02100000 {
49 i2c4: i2c@021f8000 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 compatible = "fsl,imx1-i2c";
53 reg = <0x021f8000 0x4000>;
54 interrupts = <0 35 0x04>;
55 status = "disabled";
56 };
57 };
58 };
59};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 5bfa02a3f85c..53eb241fa5ad 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -21,71 +21,6 @@
21 reg = <0x10000000 0x80000000>; 21 reg = <0x10000000 0x80000000>;
22 }; 22 };
23 23
24 soc {
25 gpmi-nand@00112000 {
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
28 status = "disabled"; /* gpmi nand conflicts with SD */
29 };
30
31 aips-bus@02000000 { /* AIPS1 */
32 iomuxc@020e0000 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_hog>;
35
36 hog {
37 pinctrl_hog: hoggrp {
38 fsl,pins = <
39 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
40 >;
41 };
42 };
43
44 arm2 {
45 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
46 fsl,pins = <
47 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
48 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
49 >;
50 };
51 };
52 };
53 };
54
55 aips-bus@02100000 { /* AIPS2 */
56 ethernet@02188000 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_enet_2>;
59 phy-mode = "rgmii";
60 status = "okay";
61 };
62
63 usdhc@02198000 { /* uSDHC3 */
64 cd-gpios = <&gpio6 11 0>;
65 wp-gpios = <&gpio6 14 0>;
66 vmmc-supply = <&reg_3p3v>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_usdhc3_1
69 &pinctrl_usdhc3_arm2>;
70 status = "okay";
71 };
72
73 usdhc@0219c000 { /* uSDHC4 */
74 non-removable;
75 vmmc-supply = <&reg_3p3v>;
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_usdhc4_1>;
78 status = "okay";
79 };
80
81 uart4: serial@021f0000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_uart4_1>;
84 status = "okay";
85 };
86 };
87 };
88
89 regulators { 24 regulators {
90 compatible = "simple-bus"; 25 compatible = "simple-bus";
91 26
@@ -108,3 +43,62 @@
108 }; 43 };
109 }; 44 };
110}; 45};
46
47&gpmi {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpmi_nand_1>;
50 status = "disabled"; /* gpmi nand conflicts with SD */
51};
52
53&iomuxc {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_hog>;
56
57 hog {
58 pinctrl_hog: hoggrp {
59 fsl,pins = <
60 176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
61 >;
62 };
63 };
64
65 arm2 {
66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
67 fsl,pins = <
68 1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
69 1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
70 >;
71 };
72 };
73};
74
75&fec {
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_enet_2>;
78 phy-mode = "rgmii";
79 status = "okay";
80};
81
82&usdhc3 {
83 cd-gpios = <&gpio6 11 0>;
84 wp-gpios = <&gpio6 14 0>;
85 vmmc-supply = <&reg_3p3v>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_usdhc3_1
88 &pinctrl_usdhc3_arm2>;
89 status = "okay";
90};
91
92&usdhc4 {
93 non-removable;
94 vmmc-supply = <&reg_3p3v>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_usdhc4_1>;
97 status = "okay";
98};
99
100&uart4 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart4_1>;
103 status = "okay";
104};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 826e4ad1477e..656d489122fe 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -20,45 +20,39 @@
20 memory { 20 memory {
21 reg = <0x10000000 0x80000000>; 21 reg = <0x10000000 0x80000000>;
22 }; 22 };
23};
23 24
24 soc { 25&iomuxc {
25 aips-bus@02000000 { /* AIPS1 */ 26 pinctrl-names = "default";
26 iomuxc@020e0000 { 27 pinctrl-0 = <&pinctrl_hog>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_hog>;
29 28
30 hog { 29 hog {
31 pinctrl_hog: hoggrp { 30 pinctrl_hog: hoggrp {
32 fsl,pins = < 31 fsl,pins = <
33 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */ 32 1376 0x80000000 /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
34 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */ 33 13 0x80000000 /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
35 >; 34 >;
36 };
37 };
38 };
39 }; 35 };
36 };
37};
40 38
41 aips-bus@02100000 { /* AIPS2 */ 39&uart4 {
42 uart4: serial@021f0000 { 40 pinctrl-names = "default";
43 pinctrl-names = "default"; 41 pinctrl-0 = <&pinctrl_uart4_1>;
44 pinctrl-0 = <&pinctrl_uart4_1>; 42 status = "okay";
45 status = "okay"; 43};
46 };
47 44
48 ethernet@02188000 { 45&fec {
49 pinctrl-names = "default"; 46 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_enet_2>; 47 pinctrl-0 = <&pinctrl_enet_2>;
51 phy-mode = "rgmii"; 48 phy-mode = "rgmii";
52 status = "okay"; 49 status = "okay";
53 }; 50};
54 51
55 usdhc@02198000 { /* uSDHC3 */ 52&usdhc3 {
56 pinctrl-names = "default"; 53 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_usdhc3_1>; 54 pinctrl-0 = <&pinctrl_usdhc3_1>;
58 cd-gpios = <&gpio6 15 0>; 55 cd-gpios = <&gpio6 15 0>;
59 wp-gpios = <&gpio1 13 0>; 56 wp-gpios = <&gpio1 13 0>;
60 status = "okay"; 57 status = "okay";
61 };
62 };
63 };
64}; 58};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index d152328285a1..2ce355cd05e5 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -21,118 +21,6 @@
21 reg = <0x10000000 0x40000000>; 21 reg = <0x10000000 0x40000000>;
22 }; 22 };
23 23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 ecspi@02008000 { /* eCSPI1 */
28 fsl,spi-num-chipselects = <1>;
29 cs-gpios = <&gpio3 19 0>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_ecspi1_1>;
32 status = "okay";
33
34 flash: m25p80@0 {
35 compatible = "sst,sst25vf016b";
36 spi-max-frequency = <20000000>;
37 reg = <0>;
38 };
39 };
40
41 ssi1: ssi@02028000 {
42 fsl,mode = "i2s-slave";
43 status = "okay";
44 };
45 };
46
47 iomuxc@020e0000 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog>;
50
51 hog {
52 pinctrl_hog: hoggrp {
53 fsl,pins = <
54 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
55 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
56 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
57 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
58 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
59 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
60 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
61 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
62 >;
63 };
64 };
65 };
66 };
67
68 aips-bus@02100000 { /* AIPS2 */
69 usb@02184000 { /* USB OTG */
70 vbus-supply = <&reg_usb_otg_vbus>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_usbotg_1>;
73 disable-over-current;
74 status = "okay";
75 };
76
77 usb@02184200 { /* USB1 */
78 status = "okay";
79 };
80
81 ethernet@02188000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_enet_1>;
84 phy-mode = "rgmii";
85 phy-reset-gpios = <&gpio3 23 0>;
86 status = "okay";
87 };
88
89 usdhc@02198000 { /* uSDHC3 */
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usdhc3_2>;
92 cd-gpios = <&gpio7 0 0>;
93 wp-gpios = <&gpio7 1 0>;
94 vmmc-supply = <&reg_3p3v>;
95 status = "okay";
96 };
97
98 usdhc@0219c000 { /* uSDHC4 */
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_usdhc4_2>;
101 cd-gpios = <&gpio2 6 0>;
102 wp-gpios = <&gpio2 7 0>;
103 vmmc-supply = <&reg_3p3v>;
104 status = "okay";
105 };
106
107 audmux@021d8000 {
108 status = "okay";
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_audmux_1>;
111 };
112
113 uart2: serial@021e8000 {
114 status = "okay";
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_uart2_1>;
117 };
118
119 i2c@021a0000 { /* I2C1 */
120 status = "okay";
121 clock-frequency = <100000>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_i2c1_1>;
124
125 codec: sgtl5000@0a {
126 compatible = "fsl,sgtl5000";
127 reg = <0x0a>;
128 clocks = <&clks 169>;
129 VDDA-supply = <&reg_2p5v>;
130 VDDIO-supply = <&reg_3p3v>;
131 };
132 };
133 };
134 };
135
136 regulators { 24 regulators {
137 compatible = "simple-bus"; 25 compatible = "simple-bus";
138 26
@@ -176,3 +64,107 @@
176 mux-ext-port = <4>; 64 mux-ext-port = <4>;
177 }; 65 };
178}; 66};
67
68&ecspi1 {
69 fsl,spi-num-chipselects = <1>;
70 cs-gpios = <&gpio3 19 0>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ecspi1_1>;
73 status = "okay";
74
75 flash: m25p80@0 {
76 compatible = "sst,sst25vf016b";
77 spi-max-frequency = <20000000>;
78 reg = <0>;
79 };
80};
81
82&ssi1 {
83 fsl,mode = "i2s-slave";
84 status = "okay";
85};
86
87&iomuxc {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_hog>;
90
91 hog {
92 pinctrl_hog: hoggrp {
93 fsl,pins = <
94 1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
95 1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
96 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
97 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
98 152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
99 1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
100 1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
101 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
102 >;
103 };
104 };
105};
106
107&usbotg {
108 vbus-supply = <&reg_usb_otg_vbus>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_usbotg_1>;
111 disable-over-current;
112 status = "okay";
113};
114
115&usbh1 {
116 status = "okay";
117};
118
119&fec {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_enet_1>;
122 phy-mode = "rgmii";
123 phy-reset-gpios = <&gpio3 23 0>;
124 status = "okay";
125};
126
127&usdhc3 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_usdhc3_2>;
130 cd-gpios = <&gpio7 0 0>;
131 wp-gpios = <&gpio7 1 0>;
132 vmmc-supply = <&reg_3p3v>;
133 status = "okay";
134};
135
136&usdhc4 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_usdhc4_2>;
139 cd-gpios = <&gpio2 6 0>;
140 wp-gpios = <&gpio2 7 0>;
141 vmmc-supply = <&reg_3p3v>;
142 status = "okay";
143};
144
145&audmux {
146 status = "okay";
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_audmux_1>;
149};
150
151&uart2 {
152 status = "okay";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart2_1>;
155};
156
157&i2c1 {
158 status = "okay";
159 clock-frequency = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1_1>;
162
163 codec: sgtl5000@0a {
164 compatible = "fsl,sgtl5000";
165 reg = <0x0a>;
166 clocks = <&clks 169>;
167 VDDA-supply = <&reg_2p5v>;
168 VDDIO-supply = <&reg_3p3v>;
169 };
170};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index a42402562b7b..2dea304a7980 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -21,61 +21,6 @@
21 reg = <0x10000000 0x40000000>; 21 reg = <0x10000000 0x40000000>;
22 }; 22 };
23 23
24 soc {
25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 uart1: serial@02020000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_uart1_1>;
30 status = "okay";
31 };
32 };
33
34 iomuxc@020e0000 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_hog>;
37
38 hog {
39 pinctrl_hog: hoggrp {
40 fsl,pins = <
41 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
42 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
43 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
44 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
45 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
46 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
47 >;
48 };
49 };
50 };
51 };
52
53 aips-bus@02100000 { /* AIPS2 */
54 ethernet@02188000 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_enet_1>;
57 phy-mode = "rgmii";
58 status = "okay";
59 };
60
61 usdhc@02194000 { /* uSDHC2 */
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_usdhc2_1>;
64 cd-gpios = <&gpio2 2 0>;
65 wp-gpios = <&gpio2 3 0>;
66 status = "okay";
67 };
68
69 usdhc@02198000 { /* uSDHC3 */
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_usdhc3_1>;
72 cd-gpios = <&gpio2 0 0>;
73 wp-gpios = <&gpio2 1 0>;
74 status = "okay";
75 };
76 };
77 };
78
79 gpio-keys { 24 gpio-keys {
80 compatible = "gpio-keys"; 25 compatible = "gpio-keys";
81 26
@@ -92,3 +37,50 @@
92 }; 37 };
93 }; 38 };
94}; 39};
40
41&uart1 {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_uart1_1>;
44 status = "okay";
45};
46
47&iomuxc {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_hog>;
50
51 hog {
52 pinctrl_hog: hoggrp {
53 fsl,pins = <
54 1004 0x80000000 /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
55 1012 0x80000000 /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
56 1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
57 1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
58 1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
59 1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
60 >;
61 };
62 };
63};
64
65&fec {
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_enet_1>;
68 phy-mode = "rgmii";
69 status = "okay";
70};
71
72&usdhc2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_usdhc2_1>;
75 cd-gpios = <&gpio2 2 0>;
76 wp-gpios = <&gpio2 3 0>;
77 status = "okay";
78};
79
80&usdhc3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_usdhc3_1>;
83 cd-gpios = <&gpio2 0 0>;
84 wp-gpios = <&gpio2 1 0>;
85 status = "okay";
86};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ff1205ea5719..cba021eb035e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -1,33 +1,16 @@
1
1/* 2/*
2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2013 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This program is free software; you can redistribute it and/or modify
6 * License. You may obtain a copy of the GNU General Public License 6 * it under the terms of the GNU General Public License version 2 as
7 * Version 2 or later at the following locations: 7 * published by the Free Software Foundation.
8 * 8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */ 9 */
12 10
13/include/ "skeleton.dtsi" 11/include/ "imx6qdl.dtsi"
14 12
15/ { 13/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 };
30
31 cpus { 14 cpus {
32 #address-cells = <1>; 15 #address-cells = <1>;
33 #size-cells = <0>; 16 #size-cells = <0>;
@@ -38,12 +21,19 @@
38 next-level-cache = <&L2>; 21 next-level-cache = <&L2>;
39 operating-points = < 22 operating-points = <
40 /* kHz uV */ 23 /* kHz uV */
41 792000 1100000 24 1200000 1275000
25 996000 1250000
26 792000 1150000
42 396000 950000 27 396000 950000
43 198000 850000
44 >; 28 >;
45 clock-latency = <61036>; /* two CLK32 periods */ 29 clock-latency = <61036>; /* two CLK32 periods */
46 cpu0-supply = <&reg_cpu>; 30 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
31 <&clks 17>, <&clks 170>;
32 clock-names = "arm", "pll2_pfd2_396m", "step",
33 "pll1_sw", "pll1_sys";
34 arm-supply = <&reg_arm>;
35 pu-supply = <&reg_pu>;
36 soc-supply = <&reg_soc>;
47 }; 37 };
48 38
49 cpu@1 { 39 cpu@1 {
@@ -65,142 +55,9 @@
65 }; 55 };
66 }; 56 };
67 57
68 intc: interrupt-controller@00a01000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 interrupt-controller;
74 reg = <0x00a01000 0x1000>,
75 <0x00a00100 0x100>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fsl,imx-ckil", "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 ckih1 {
88 compatible = "fsl,imx-ckih1", "fixed-clock";
89 clock-frequency = <0>;
90 };
91
92 osc {
93 compatible = "fsl,imx-osc", "fixed-clock";
94 clock-frequency = <24000000>;
95 };
96 };
97
98 soc { 58 soc {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "simple-bus";
102 interrupt-parent = <&intc>;
103 ranges;
104
105 dma-apbh@00110000 {
106 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
107 reg = <0x00110000 0x2000>;
108 clocks = <&clks 106>;
109 };
110
111 nfc: gpmi-nand@00112000 {
112 compatible = "fsl,imx6q-gpmi-nand";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
116 reg-names = "gpmi-nand", "bch";
117 interrupts = <0 13 0x04>, <0 15 0x04>;
118 interrupt-names = "gpmi-dma", "bch";
119 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
120 <&clks 150>, <&clks 149>;
121 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
122 "gpmi_bch_apb", "per1_bch";
123 fsl,gpmi-dma-channel = <0>;
124 status = "disabled";
125 };
126
127 timer@00a00600 {
128 compatible = "arm,cortex-a9-twd-timer";
129 reg = <0x00a00600 0x20>;
130 interrupts = <1 13 0xf01>;
131 };
132
133 L2: l2-cache@00a02000 {
134 compatible = "arm,pl310-cache";
135 reg = <0x00a02000 0x1000>;
136 interrupts = <0 92 0x04>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
141 aips-bus@02000000 { /* AIPS1 */ 59 aips-bus@02000000 { /* AIPS1 */
142 compatible = "fsl,aips-bus", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 reg = <0x02000000 0x100000>;
146 ranges;
147
148 spba-bus@02000000 { 60 spba-bus@02000000 {
149 compatible = "fsl,spba-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x02000000 0x40000>;
153 ranges;
154
155 spdif: spdif@02004000 {
156 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 0x04>;
158 };
159
160 ecspi1: ecspi@02008000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x02008000 0x4000>;
165 interrupts = <0 31 0x04>;
166 clocks = <&clks 112>, <&clks 112>;
167 clock-names = "ipg", "per";
168 status = "disabled";
169 };
170
171 ecspi2: ecspi@0200c000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x0200c000 0x4000>;
176 interrupts = <0 32 0x04>;
177 clocks = <&clks 113>, <&clks 113>;
178 clock-names = "ipg", "per";
179 status = "disabled";
180 };
181
182 ecspi3: ecspi@02010000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <0 33 0x04>;
188 clocks = <&clks 114>, <&clks 114>;
189 clock-names = "ipg", "per";
190 status = "disabled";
191 };
192
193 ecspi4: ecspi@02014000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
197 reg = <0x02014000 0x4000>;
198 interrupts = <0 34 0x04>;
199 clocks = <&clks 115>, <&clks 115>;
200 clock-names = "ipg", "per";
201 status = "disabled";
202 };
203
204 ecspi5: ecspi@02018000 { 61 ecspi5: ecspi@02018000 {
205 #address-cells = <1>; 62 #address-cells = <1>;
206 #size-cells = <0>; 63 #size-cells = <0>;
@@ -211,361 +68,6 @@
211 clock-names = "ipg", "per"; 68 clock-names = "ipg", "per";
212 status = "disabled"; 69 status = "disabled";
213 }; 70 };
214
215 uart1: serial@02020000 {
216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
217 reg = <0x02020000 0x4000>;
218 interrupts = <0 26 0x04>;
219 clocks = <&clks 160>, <&clks 161>;
220 clock-names = "ipg", "per";
221 status = "disabled";
222 };
223
224 esai: esai@02024000 {
225 reg = <0x02024000 0x4000>;
226 interrupts = <0 51 0x04>;
227 };
228
229 ssi1: ssi@02028000 {
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
231 reg = <0x02028000 0x4000>;
232 interrupts = <0 46 0x04>;
233 clocks = <&clks 178>;
234 fsl,fifo-depth = <15>;
235 fsl,ssi-dma-events = <38 37>;
236 status = "disabled";
237 };
238
239 ssi2: ssi@0202c000 {
240 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
241 reg = <0x0202c000 0x4000>;
242 interrupts = <0 47 0x04>;
243 clocks = <&clks 179>;
244 fsl,fifo-depth = <15>;
245 fsl,ssi-dma-events = <42 41>;
246 status = "disabled";
247 };
248
249 ssi3: ssi@02030000 {
250 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
251 reg = <0x02030000 0x4000>;
252 interrupts = <0 48 0x04>;
253 clocks = <&clks 180>;
254 fsl,fifo-depth = <15>;
255 fsl,ssi-dma-events = <46 45>;
256 status = "disabled";
257 };
258
259 asrc: asrc@02034000 {
260 reg = <0x02034000 0x4000>;
261 interrupts = <0 50 0x04>;
262 };
263
264 spba@0203c000 {
265 reg = <0x0203c000 0x4000>;
266 };
267 };
268
269 vpu: vpu@02040000 {
270 reg = <0x02040000 0x3c000>;
271 interrupts = <0 3 0x04 0 12 0x04>;
272 };
273
274 aipstz@0207c000 { /* AIPSTZ1 */
275 reg = <0x0207c000 0x4000>;
276 };
277
278 pwm1: pwm@02080000 {
279 #pwm-cells = <2>;
280 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
281 reg = <0x02080000 0x4000>;
282 interrupts = <0 83 0x04>;
283 clocks = <&clks 62>, <&clks 145>;
284 clock-names = "ipg", "per";
285 };
286
287 pwm2: pwm@02084000 {
288 #pwm-cells = <2>;
289 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
290 reg = <0x02084000 0x4000>;
291 interrupts = <0 84 0x04>;
292 clocks = <&clks 62>, <&clks 146>;
293 clock-names = "ipg", "per";
294 };
295
296 pwm3: pwm@02088000 {
297 #pwm-cells = <2>;
298 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
299 reg = <0x02088000 0x4000>;
300 interrupts = <0 85 0x04>;
301 clocks = <&clks 62>, <&clks 147>;
302 clock-names = "ipg", "per";
303 };
304
305 pwm4: pwm@0208c000 {
306 #pwm-cells = <2>;
307 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
308 reg = <0x0208c000 0x4000>;
309 interrupts = <0 86 0x04>;
310 clocks = <&clks 62>, <&clks 148>;
311 clock-names = "ipg", "per";
312 };
313
314 can1: flexcan@02090000 {
315 reg = <0x02090000 0x4000>;
316 interrupts = <0 110 0x04>;
317 };
318
319 can2: flexcan@02094000 {
320 reg = <0x02094000 0x4000>;
321 interrupts = <0 111 0x04>;
322 };
323
324 gpt: gpt@02098000 {
325 compatible = "fsl,imx6q-gpt";
326 reg = <0x02098000 0x4000>;
327 interrupts = <0 55 0x04>;
328 };
329
330 gpio1: gpio@0209c000 {
331 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
332 reg = <0x0209c000 0x4000>;
333 interrupts = <0 66 0x04 0 67 0x04>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 };
339
340 gpio2: gpio@020a0000 {
341 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
342 reg = <0x020a0000 0x4000>;
343 interrupts = <0 68 0x04 0 69 0x04>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 gpio3: gpio@020a4000 {
351 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
352 reg = <0x020a4000 0x4000>;
353 interrupts = <0 70 0x04 0 71 0x04>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 };
359
360 gpio4: gpio@020a8000 {
361 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
362 reg = <0x020a8000 0x4000>;
363 interrupts = <0 72 0x04 0 73 0x04>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
367 #interrupt-cells = <2>;
368 };
369
370 gpio5: gpio@020ac000 {
371 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
372 reg = <0x020ac000 0x4000>;
373 interrupts = <0 74 0x04 0 75 0x04>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
378 };
379
380 gpio6: gpio@020b0000 {
381 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
382 reg = <0x020b0000 0x4000>;
383 interrupts = <0 76 0x04 0 77 0x04>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 };
389
390 gpio7: gpio@020b4000 {
391 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
392 reg = <0x020b4000 0x4000>;
393 interrupts = <0 78 0x04 0 79 0x04>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 };
399
400 kpp: kpp@020b8000 {
401 reg = <0x020b8000 0x4000>;
402 interrupts = <0 82 0x04>;
403 };
404
405 wdog1: wdog@020bc000 {
406 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
407 reg = <0x020bc000 0x4000>;
408 interrupts = <0 80 0x04>;
409 clocks = <&clks 0>;
410 };
411
412 wdog2: wdog@020c0000 {
413 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
414 reg = <0x020c0000 0x4000>;
415 interrupts = <0 81 0x04>;
416 clocks = <&clks 0>;
417 status = "disabled";
418 };
419
420 clks: ccm@020c4000 {
421 compatible = "fsl,imx6q-ccm";
422 reg = <0x020c4000 0x4000>;
423 interrupts = <0 87 0x04 0 88 0x04>;
424 #clock-cells = <1>;
425 };
426
427 anatop: anatop@020c8000 {
428 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
429 reg = <0x020c8000 0x1000>;
430 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
431
432 regulator-1p1@110 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "vdd1p1";
435 regulator-min-microvolt = <800000>;
436 regulator-max-microvolt = <1375000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x110>;
439 anatop-vol-bit-shift = <8>;
440 anatop-vol-bit-width = <5>;
441 anatop-min-bit-val = <4>;
442 anatop-min-voltage = <800000>;
443 anatop-max-voltage = <1375000>;
444 };
445
446 regulator-3p0@120 {
447 compatible = "fsl,anatop-regulator";
448 regulator-name = "vdd3p0";
449 regulator-min-microvolt = <2800000>;
450 regulator-max-microvolt = <3150000>;
451 regulator-always-on;
452 anatop-reg-offset = <0x120>;
453 anatop-vol-bit-shift = <8>;
454 anatop-vol-bit-width = <5>;
455 anatop-min-bit-val = <0>;
456 anatop-min-voltage = <2625000>;
457 anatop-max-voltage = <3400000>;
458 };
459
460 regulator-2p5@130 {
461 compatible = "fsl,anatop-regulator";
462 regulator-name = "vdd2p5";
463 regulator-min-microvolt = <2000000>;
464 regulator-max-microvolt = <2750000>;
465 regulator-always-on;
466 anatop-reg-offset = <0x130>;
467 anatop-vol-bit-shift = <8>;
468 anatop-vol-bit-width = <5>;
469 anatop-min-bit-val = <0>;
470 anatop-min-voltage = <2000000>;
471 anatop-max-voltage = <2750000>;
472 };
473
474 reg_cpu: regulator-vddcore@140 {
475 compatible = "fsl,anatop-regulator";
476 regulator-name = "cpu";
477 regulator-min-microvolt = <725000>;
478 regulator-max-microvolt = <1450000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x140>;
481 anatop-vol-bit-shift = <0>;
482 anatop-vol-bit-width = <5>;
483 anatop-min-bit-val = <1>;
484 anatop-min-voltage = <725000>;
485 anatop-max-voltage = <1450000>;
486 };
487
488 regulator-vddpu@140 {
489 compatible = "fsl,anatop-regulator";
490 regulator-name = "vddpu";
491 regulator-min-microvolt = <725000>;
492 regulator-max-microvolt = <1450000>;
493 regulator-always-on;
494 anatop-reg-offset = <0x140>;
495 anatop-vol-bit-shift = <9>;
496 anatop-vol-bit-width = <5>;
497 anatop-min-bit-val = <1>;
498 anatop-min-voltage = <725000>;
499 anatop-max-voltage = <1450000>;
500 };
501
502 regulator-vddsoc@140 {
503 compatible = "fsl,anatop-regulator";
504 regulator-name = "vddsoc";
505 regulator-min-microvolt = <725000>;
506 regulator-max-microvolt = <1450000>;
507 regulator-always-on;
508 anatop-reg-offset = <0x140>;
509 anatop-vol-bit-shift = <18>;
510 anatop-vol-bit-width = <5>;
511 anatop-min-bit-val = <1>;
512 anatop-min-voltage = <725000>;
513 anatop-max-voltage = <1450000>;
514 };
515 };
516
517 usbphy1: usbphy@020c9000 {
518 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
519 reg = <0x020c9000 0x1000>;
520 interrupts = <0 44 0x04>;
521 clocks = <&clks 182>;
522 };
523
524 usbphy2: usbphy@020ca000 {
525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
526 reg = <0x020ca000 0x1000>;
527 interrupts = <0 45 0x04>;
528 clocks = <&clks 183>;
529 };
530
531 snvs@020cc000 {
532 compatible = "fsl,sec-v4.0-mon", "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges = <0 0x020cc000 0x4000>;
536
537 snvs-rtc-lp@34 {
538 compatible = "fsl,sec-v4.0-mon-rtc-lp";
539 reg = <0x34 0x58>;
540 interrupts = <0 19 0x04 0 20 0x04>;
541 };
542 };
543
544 epit1: epit@020d0000 { /* EPIT1 */
545 reg = <0x020d0000 0x4000>;
546 interrupts = <0 56 0x04>;
547 };
548
549 epit2: epit@020d4000 { /* EPIT2 */
550 reg = <0x020d4000 0x4000>;
551 interrupts = <0 57 0x04>;
552 };
553
554 src: src@020d8000 {
555 compatible = "fsl,imx6q-src";
556 reg = <0x020d8000 0x4000>;
557 interrupts = <0 91 0x04 0 96 0x04>;
558 };
559
560 gpc: gpc@020dc000 {
561 compatible = "fsl,imx6q-gpc";
562 reg = <0x020dc000 0x4000>;
563 interrupts = <0 89 0x04 0 90 0x04>;
564 };
565
566 gpr: iomuxc-gpr@020e0000 {
567 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
568 reg = <0x020e0000 0x38>;
569 }; 71 };
570 72
571 iomuxc: iomuxc@020e0000 { 73 iomuxc: iomuxc@020e0000 {
@@ -780,272 +282,6 @@
780 }; 282 };
781 }; 283 };
782 }; 284 };
783
784 dcic1: dcic@020e4000 {
785 reg = <0x020e4000 0x4000>;
786 interrupts = <0 124 0x04>;
787 };
788
789 dcic2: dcic@020e8000 {
790 reg = <0x020e8000 0x4000>;
791 interrupts = <0 125 0x04>;
792 };
793
794 sdma: sdma@020ec000 {
795 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
796 reg = <0x020ec000 0x4000>;
797 interrupts = <0 2 0x04>;
798 clocks = <&clks 155>, <&clks 155>;
799 clock-names = "ipg", "ahb";
800 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
801 };
802 };
803
804 aips-bus@02100000 { /* AIPS2 */
805 compatible = "fsl,aips-bus", "simple-bus";
806 #address-cells = <1>;
807 #size-cells = <1>;
808 reg = <0x02100000 0x100000>;
809 ranges;
810
811 caam@02100000 {
812 reg = <0x02100000 0x40000>;
813 interrupts = <0 105 0x04 0 106 0x04>;
814 };
815
816 aipstz@0217c000 { /* AIPSTZ2 */
817 reg = <0x0217c000 0x4000>;
818 };
819
820 usbotg: usb@02184000 {
821 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
822 reg = <0x02184000 0x200>;
823 interrupts = <0 43 0x04>;
824 clocks = <&clks 162>;
825 fsl,usbphy = <&usbphy1>;
826 fsl,usbmisc = <&usbmisc 0>;
827 status = "disabled";
828 };
829
830 usbh1: usb@02184200 {
831 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
832 reg = <0x02184200 0x200>;
833 interrupts = <0 40 0x04>;
834 clocks = <&clks 162>;
835 fsl,usbphy = <&usbphy2>;
836 fsl,usbmisc = <&usbmisc 1>;
837 status = "disabled";
838 };
839
840 usbh2: usb@02184400 {
841 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
842 reg = <0x02184400 0x200>;
843 interrupts = <0 41 0x04>;
844 clocks = <&clks 162>;
845 fsl,usbmisc = <&usbmisc 2>;
846 status = "disabled";
847 };
848
849 usbh3: usb@02184600 {
850 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
851 reg = <0x02184600 0x200>;
852 interrupts = <0 42 0x04>;
853 clocks = <&clks 162>;
854 fsl,usbmisc = <&usbmisc 3>;
855 status = "disabled";
856 };
857
858 usbmisc: usbmisc: usbmisc@02184800 {
859 #index-cells = <1>;
860 compatible = "fsl,imx6q-usbmisc";
861 reg = <0x02184800 0x200>;
862 clocks = <&clks 162>;
863 };
864
865 fec: ethernet@02188000 {
866 compatible = "fsl,imx6q-fec";
867 reg = <0x02188000 0x4000>;
868 interrupts = <0 118 0x04 0 119 0x04>;
869 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
870 clock-names = "ipg", "ahb", "ptp";
871 status = "disabled";
872 };
873
874 mlb@0218c000 {
875 reg = <0x0218c000 0x4000>;
876 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
877 };
878
879 usdhc1: usdhc@02190000 {
880 compatible = "fsl,imx6q-usdhc";
881 reg = <0x02190000 0x4000>;
882 interrupts = <0 22 0x04>;
883 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
884 clock-names = "ipg", "ahb", "per";
885 bus-width = <4>;
886 status = "disabled";
887 };
888
889 usdhc2: usdhc@02194000 {
890 compatible = "fsl,imx6q-usdhc";
891 reg = <0x02194000 0x4000>;
892 interrupts = <0 23 0x04>;
893 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
894 clock-names = "ipg", "ahb", "per";
895 bus-width = <4>;
896 status = "disabled";
897 };
898
899 usdhc3: usdhc@02198000 {
900 compatible = "fsl,imx6q-usdhc";
901 reg = <0x02198000 0x4000>;
902 interrupts = <0 24 0x04>;
903 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
904 clock-names = "ipg", "ahb", "per";
905 bus-width = <4>;
906 status = "disabled";
907 };
908
909 usdhc4: usdhc@0219c000 {
910 compatible = "fsl,imx6q-usdhc";
911 reg = <0x0219c000 0x4000>;
912 interrupts = <0 25 0x04>;
913 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
914 clock-names = "ipg", "ahb", "per";
915 bus-width = <4>;
916 status = "disabled";
917 };
918
919 i2c1: i2c@021a0000 {
920 #address-cells = <1>;
921 #size-cells = <0>;
922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
923 reg = <0x021a0000 0x4000>;
924 interrupts = <0 36 0x04>;
925 clocks = <&clks 125>;
926 status = "disabled";
927 };
928
929 i2c2: i2c@021a4000 {
930 #address-cells = <1>;
931 #size-cells = <0>;
932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
933 reg = <0x021a4000 0x4000>;
934 interrupts = <0 37 0x04>;
935 clocks = <&clks 126>;
936 status = "disabled";
937 };
938
939 i2c3: i2c@021a8000 {
940 #address-cells = <1>;
941 #size-cells = <0>;
942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
943 reg = <0x021a8000 0x4000>;
944 interrupts = <0 38 0x04>;
945 clocks = <&clks 127>;
946 status = "disabled";
947 };
948
949 romcp@021ac000 {
950 reg = <0x021ac000 0x4000>;
951 };
952
953 mmdc0: mmdc@021b0000 { /* MMDC0 */
954 compatible = "fsl,imx6q-mmdc";
955 reg = <0x021b0000 0x4000>;
956 };
957
958 mmdc1: mmdc@021b4000 { /* MMDC1 */
959 reg = <0x021b4000 0x4000>;
960 };
961
962 weim@021b8000 {
963 reg = <0x021b8000 0x4000>;
964 interrupts = <0 14 0x04>;
965 };
966
967 ocotp@021bc000 {
968 reg = <0x021bc000 0x4000>;
969 };
970
971 ocotp@021c0000 {
972 reg = <0x021c0000 0x4000>;
973 interrupts = <0 21 0x04>;
974 };
975
976 tzasc@021d0000 { /* TZASC1 */
977 reg = <0x021d0000 0x4000>;
978 interrupts = <0 108 0x04>;
979 };
980
981 tzasc@021d4000 { /* TZASC2 */
982 reg = <0x021d4000 0x4000>;
983 interrupts = <0 109 0x04>;
984 };
985
986 audmux: audmux@021d8000 {
987 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
988 reg = <0x021d8000 0x4000>;
989 status = "disabled";
990 };
991
992 mipi@021dc000 { /* MIPI-CSI */
993 reg = <0x021dc000 0x4000>;
994 };
995
996 mipi@021e0000 { /* MIPI-DSI */
997 reg = <0x021e0000 0x4000>;
998 };
999
1000 vdoa@021e4000 {
1001 reg = <0x021e4000 0x4000>;
1002 interrupts = <0 18 0x04>;
1003 };
1004
1005 uart2: serial@021e8000 {
1006 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1007 reg = <0x021e8000 0x4000>;
1008 interrupts = <0 27 0x04>;
1009 clocks = <&clks 160>, <&clks 161>;
1010 clock-names = "ipg", "per";
1011 status = "disabled";
1012 };
1013
1014 uart3: serial@021ec000 {
1015 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1016 reg = <0x021ec000 0x4000>;
1017 interrupts = <0 28 0x04>;
1018 clocks = <&clks 160>, <&clks 161>;
1019 clock-names = "ipg", "per";
1020 status = "disabled";
1021 };
1022
1023 uart4: serial@021f0000 {
1024 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1025 reg = <0x021f0000 0x4000>;
1026 interrupts = <0 29 0x04>;
1027 clocks = <&clks 160>, <&clks 161>;
1028 clock-names = "ipg", "per";
1029 status = "disabled";
1030 };
1031
1032 uart5: serial@021f4000 {
1033 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1034 reg = <0x021f4000 0x4000>;
1035 interrupts = <0 30 0x04>;
1036 clocks = <&clks 160>, <&clks 161>;
1037 clock-names = "ipg", "per";
1038 status = "disabled";
1039 };
1040 };
1041
1042 ipu1: ipu@02400000 {
1043 #crtc-cells = <1>;
1044 compatible = "fsl,imx6q-ipu";
1045 reg = <0x02400000 0x400000>;
1046 interrupts = <0 6 0x4 0 5 0x4>;
1047 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1048 clock-names = "bus", "di0", "di1";
1049 }; 285 };
1050 286
1051 ipu2: ipu@02800000 { 287 ipu2: ipu@02800000 {
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
new file mode 100644
index 000000000000..06ec460b4581
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -0,0 +1,800 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
29 };
30
31 intc: interrupt-controller@00a01000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 #address-cells = <1>;
35 #size-cells = <1>;
36 interrupt-controller;
37 reg = <0x00a01000 0x1000>,
38 <0x00a00100 0x100>;
39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ckil {
46 compatible = "fsl,imx-ckil", "fixed-clock";
47 clock-frequency = <32768>;
48 };
49
50 ckih1 {
51 compatible = "fsl,imx-ckih1", "fixed-clock";
52 clock-frequency = <0>;
53 };
54
55 osc {
56 compatible = "fsl,imx-osc", "fixed-clock";
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";
65 interrupt-parent = <&intc>;
66 ranges;
67
68 dma-apbh@00110000 {
69 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
70 reg = <0x00110000 0x2000>;
71 clocks = <&clks 106>;
72 };
73
74 gpmi: gpmi-nand@00112000 {
75 compatible = "fsl,imx6q-gpmi-nand";
76 #address-cells = <1>;
77 #size-cells = <1>;
78 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
79 reg-names = "gpmi-nand", "bch";
80 interrupts = <0 13 0x04>, <0 15 0x04>;
81 interrupt-names = "gpmi-dma", "bch";
82 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
83 <&clks 150>, <&clks 149>;
84 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
85 "gpmi_bch_apb", "per1_bch";
86 fsl,gpmi-dma-channel = <0>;
87 status = "disabled";
88 };
89
90 timer@00a00600 {
91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x20>;
93 interrupts = <1 13 0xf01>;
94 };
95
96 L2: l2-cache@00a02000 {
97 compatible = "arm,pl310-cache";
98 reg = <0x00a02000 0x1000>;
99 interrupts = <0 92 0x04>;
100 cache-unified;
101 cache-level = <2>;
102 };
103
104 aips-bus@02000000 { /* AIPS1 */
105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x02000000 0x100000>;
109 ranges;
110
111 spba-bus@02000000 {
112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x02000000 0x40000>;
116 ranges;
117
118 spdif: spdif@02004000 {
119 reg = <0x02004000 0x4000>;
120 interrupts = <0 52 0x04>;
121 };
122
123 ecspi1: ecspi@02008000 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
127 reg = <0x02008000 0x4000>;
128 interrupts = <0 31 0x04>;
129 clocks = <&clks 112>, <&clks 112>;
130 clock-names = "ipg", "per";
131 status = "disabled";
132 };
133
134 ecspi2: ecspi@0200c000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
138 reg = <0x0200c000 0x4000>;
139 interrupts = <0 32 0x04>;
140 clocks = <&clks 113>, <&clks 113>;
141 clock-names = "ipg", "per";
142 status = "disabled";
143 };
144
145 ecspi3: ecspi@02010000 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
149 reg = <0x02010000 0x4000>;
150 interrupts = <0 33 0x04>;
151 clocks = <&clks 114>, <&clks 114>;
152 clock-names = "ipg", "per";
153 status = "disabled";
154 };
155
156 ecspi4: ecspi@02014000 {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
160 reg = <0x02014000 0x4000>;
161 interrupts = <0 34 0x04>;
162 clocks = <&clks 115>, <&clks 115>;
163 clock-names = "ipg", "per";
164 status = "disabled";
165 };
166
167 uart1: serial@02020000 {
168 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
169 reg = <0x02020000 0x4000>;
170 interrupts = <0 26 0x04>;
171 clocks = <&clks 160>, <&clks 161>;
172 clock-names = "ipg", "per";
173 status = "disabled";
174 };
175
176 esai: esai@02024000 {
177 reg = <0x02024000 0x4000>;
178 interrupts = <0 51 0x04>;
179 };
180
181 ssi1: ssi@02028000 {
182 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
183 reg = <0x02028000 0x4000>;
184 interrupts = <0 46 0x04>;
185 clocks = <&clks 178>;
186 fsl,fifo-depth = <15>;
187 fsl,ssi-dma-events = <38 37>;
188 status = "disabled";
189 };
190
191 ssi2: ssi@0202c000 {
192 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
193 reg = <0x0202c000 0x4000>;
194 interrupts = <0 47 0x04>;
195 clocks = <&clks 179>;
196 fsl,fifo-depth = <15>;
197 fsl,ssi-dma-events = <42 41>;
198 status = "disabled";
199 };
200
201 ssi3: ssi@02030000 {
202 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
203 reg = <0x02030000 0x4000>;
204 interrupts = <0 48 0x04>;
205 clocks = <&clks 180>;
206 fsl,fifo-depth = <15>;
207 fsl,ssi-dma-events = <46 45>;
208 status = "disabled";
209 };
210
211 asrc: asrc@02034000 {
212 reg = <0x02034000 0x4000>;
213 interrupts = <0 50 0x04>;
214 };
215
216 spba@0203c000 {
217 reg = <0x0203c000 0x4000>;
218 };
219 };
220
221 vpu: vpu@02040000 {
222 reg = <0x02040000 0x3c000>;
223 interrupts = <0 3 0x04 0 12 0x04>;
224 };
225
226 aipstz@0207c000 { /* AIPSTZ1 */
227 reg = <0x0207c000 0x4000>;
228 };
229
230 pwm1: pwm@02080000 {
231 #pwm-cells = <2>;
232 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
233 reg = <0x02080000 0x4000>;
234 interrupts = <0 83 0x04>;
235 clocks = <&clks 62>, <&clks 145>;
236 clock-names = "ipg", "per";
237 };
238
239 pwm2: pwm@02084000 {
240 #pwm-cells = <2>;
241 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
242 reg = <0x02084000 0x4000>;
243 interrupts = <0 84 0x04>;
244 clocks = <&clks 62>, <&clks 146>;
245 clock-names = "ipg", "per";
246 };
247
248 pwm3: pwm@02088000 {
249 #pwm-cells = <2>;
250 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
251 reg = <0x02088000 0x4000>;
252 interrupts = <0 85 0x04>;
253 clocks = <&clks 62>, <&clks 147>;
254 clock-names = "ipg", "per";
255 };
256
257 pwm4: pwm@0208c000 {
258 #pwm-cells = <2>;
259 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
260 reg = <0x0208c000 0x4000>;
261 interrupts = <0 86 0x04>;
262 clocks = <&clks 62>, <&clks 148>;
263 clock-names = "ipg", "per";
264 };
265
266 can1: flexcan@02090000 {
267 reg = <0x02090000 0x4000>;
268 interrupts = <0 110 0x04>;
269 };
270
271 can2: flexcan@02094000 {
272 reg = <0x02094000 0x4000>;
273 interrupts = <0 111 0x04>;
274 };
275
276 gpt: gpt@02098000 {
277 compatible = "fsl,imx6q-gpt";
278 reg = <0x02098000 0x4000>;
279 interrupts = <0 55 0x04>;
280 };
281
282 gpio1: gpio@0209c000 {
283 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
284 reg = <0x0209c000 0x4000>;
285 interrupts = <0 66 0x04 0 67 0x04>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 gpio2: gpio@020a0000 {
293 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
294 reg = <0x020a0000 0x4000>;
295 interrupts = <0 68 0x04 0 69 0x04>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
300 };
301
302 gpio3: gpio@020a4000 {
303 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
304 reg = <0x020a4000 0x4000>;
305 interrupts = <0 70 0x04 0 71 0x04>;
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
310 };
311
312 gpio4: gpio@020a8000 {
313 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
314 reg = <0x020a8000 0x4000>;
315 interrupts = <0 72 0x04 0 73 0x04>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
321
322 gpio5: gpio@020ac000 {
323 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
324 reg = <0x020ac000 0x4000>;
325 interrupts = <0 74 0x04 0 75 0x04>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
330 };
331
332 gpio6: gpio@020b0000 {
333 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
334 reg = <0x020b0000 0x4000>;
335 interrupts = <0 76 0x04 0 77 0x04>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 };
341
342 gpio7: gpio@020b4000 {
343 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
344 reg = <0x020b4000 0x4000>;
345 interrupts = <0 78 0x04 0 79 0x04>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 };
351
352 kpp: kpp@020b8000 {
353 reg = <0x020b8000 0x4000>;
354 interrupts = <0 82 0x04>;
355 };
356
357 wdog1: wdog@020bc000 {
358 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
359 reg = <0x020bc000 0x4000>;
360 interrupts = <0 80 0x04>;
361 clocks = <&clks 0>;
362 };
363
364 wdog2: wdog@020c0000 {
365 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
366 reg = <0x020c0000 0x4000>;
367 interrupts = <0 81 0x04>;
368 clocks = <&clks 0>;
369 status = "disabled";
370 };
371
372 clks: ccm@020c4000 {
373 compatible = "fsl,imx6q-ccm";
374 reg = <0x020c4000 0x4000>;
375 interrupts = <0 87 0x04 0 88 0x04>;
376 #clock-cells = <1>;
377 };
378
379 anatop: anatop@020c8000 {
380 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
381 reg = <0x020c8000 0x1000>;
382 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
383
384 regulator-1p1@110 {
385 compatible = "fsl,anatop-regulator";
386 regulator-name = "vdd1p1";
387 regulator-min-microvolt = <800000>;
388 regulator-max-microvolt = <1375000>;
389 regulator-always-on;
390 anatop-reg-offset = <0x110>;
391 anatop-vol-bit-shift = <8>;
392 anatop-vol-bit-width = <5>;
393 anatop-min-bit-val = <4>;
394 anatop-min-voltage = <800000>;
395 anatop-max-voltage = <1375000>;
396 };
397
398 regulator-3p0@120 {
399 compatible = "fsl,anatop-regulator";
400 regulator-name = "vdd3p0";
401 regulator-min-microvolt = <2800000>;
402 regulator-max-microvolt = <3150000>;
403 regulator-always-on;
404 anatop-reg-offset = <0x120>;
405 anatop-vol-bit-shift = <8>;
406 anatop-vol-bit-width = <5>;
407 anatop-min-bit-val = <0>;
408 anatop-min-voltage = <2625000>;
409 anatop-max-voltage = <3400000>;
410 };
411
412 regulator-2p5@130 {
413 compatible = "fsl,anatop-regulator";
414 regulator-name = "vdd2p5";
415 regulator-min-microvolt = <2000000>;
416 regulator-max-microvolt = <2750000>;
417 regulator-always-on;
418 anatop-reg-offset = <0x130>;
419 anatop-vol-bit-shift = <8>;
420 anatop-vol-bit-width = <5>;
421 anatop-min-bit-val = <0>;
422 anatop-min-voltage = <2000000>;
423 anatop-max-voltage = <2750000>;
424 };
425
426 reg_arm: regulator-vddcore@140 {
427 compatible = "fsl,anatop-regulator";
428 regulator-name = "cpu";
429 regulator-min-microvolt = <725000>;
430 regulator-max-microvolt = <1450000>;
431 regulator-always-on;
432 anatop-reg-offset = <0x140>;
433 anatop-vol-bit-shift = <0>;
434 anatop-vol-bit-width = <5>;
435 anatop-delay-reg-offset = <0x170>;
436 anatop-delay-bit-shift = <24>;
437 anatop-delay-bit-width = <2>;
438 anatop-min-bit-val = <1>;
439 anatop-min-voltage = <725000>;
440 anatop-max-voltage = <1450000>;
441 };
442
443 reg_pu: regulator-vddpu@140 {
444 compatible = "fsl,anatop-regulator";
445 regulator-name = "vddpu";
446 regulator-min-microvolt = <725000>;
447 regulator-max-microvolt = <1450000>;
448 regulator-always-on;
449 anatop-reg-offset = <0x140>;
450 anatop-vol-bit-shift = <9>;
451 anatop-vol-bit-width = <5>;
452 anatop-delay-reg-offset = <0x170>;
453 anatop-delay-bit-shift = <26>;
454 anatop-delay-bit-width = <2>;
455 anatop-min-bit-val = <1>;
456 anatop-min-voltage = <725000>;
457 anatop-max-voltage = <1450000>;
458 };
459
460 reg_soc: regulator-vddsoc@140 {
461 compatible = "fsl,anatop-regulator";
462 regulator-name = "vddsoc";
463 regulator-min-microvolt = <725000>;
464 regulator-max-microvolt = <1450000>;
465 regulator-always-on;
466 anatop-reg-offset = <0x140>;
467 anatop-vol-bit-shift = <18>;
468 anatop-vol-bit-width = <5>;
469 anatop-delay-reg-offset = <0x170>;
470 anatop-delay-bit-shift = <28>;
471 anatop-delay-bit-width = <2>;
472 anatop-min-bit-val = <1>;
473 anatop-min-voltage = <725000>;
474 anatop-max-voltage = <1450000>;
475 };
476 };
477
478 usbphy1: usbphy@020c9000 {
479 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
480 reg = <0x020c9000 0x1000>;
481 interrupts = <0 44 0x04>;
482 clocks = <&clks 182>;
483 };
484
485 usbphy2: usbphy@020ca000 {
486 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
487 reg = <0x020ca000 0x1000>;
488 interrupts = <0 45 0x04>;
489 clocks = <&clks 183>;
490 };
491
492 snvs@020cc000 {
493 compatible = "fsl,sec-v4.0-mon", "simple-bus";
494 #address-cells = <1>;
495 #size-cells = <1>;
496 ranges = <0 0x020cc000 0x4000>;
497
498 snvs-rtc-lp@34 {
499 compatible = "fsl,sec-v4.0-mon-rtc-lp";
500 reg = <0x34 0x58>;
501 interrupts = <0 19 0x04 0 20 0x04>;
502 };
503 };
504
505 epit1: epit@020d0000 { /* EPIT1 */
506 reg = <0x020d0000 0x4000>;
507 interrupts = <0 56 0x04>;
508 };
509
510 epit2: epit@020d4000 { /* EPIT2 */
511 reg = <0x020d4000 0x4000>;
512 interrupts = <0 57 0x04>;
513 };
514
515 src: src@020d8000 {
516 compatible = "fsl,imx6q-src";
517 reg = <0x020d8000 0x4000>;
518 interrupts = <0 91 0x04 0 96 0x04>;
519 };
520
521 gpc: gpc@020dc000 {
522 compatible = "fsl,imx6q-gpc";
523 reg = <0x020dc000 0x4000>;
524 interrupts = <0 89 0x04 0 90 0x04>;
525 };
526
527 gpr: iomuxc-gpr@020e0000 {
528 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
529 reg = <0x020e0000 0x38>;
530 };
531
532 dcic1: dcic@020e4000 {
533 reg = <0x020e4000 0x4000>;
534 interrupts = <0 124 0x04>;
535 };
536
537 dcic2: dcic@020e8000 {
538 reg = <0x020e8000 0x4000>;
539 interrupts = <0 125 0x04>;
540 };
541
542 sdma: sdma@020ec000 {
543 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
544 reg = <0x020ec000 0x4000>;
545 interrupts = <0 2 0x04>;
546 clocks = <&clks 155>, <&clks 155>;
547 clock-names = "ipg", "ahb";
548 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
549 };
550 };
551
552 aips-bus@02100000 { /* AIPS2 */
553 compatible = "fsl,aips-bus", "simple-bus";
554 #address-cells = <1>;
555 #size-cells = <1>;
556 reg = <0x02100000 0x100000>;
557 ranges;
558
559 caam@02100000 {
560 reg = <0x02100000 0x40000>;
561 interrupts = <0 105 0x04 0 106 0x04>;
562 };
563
564 aipstz@0217c000 { /* AIPSTZ2 */
565 reg = <0x0217c000 0x4000>;
566 };
567
568 usbotg: usb@02184000 {
569 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
570 reg = <0x02184000 0x200>;
571 interrupts = <0 43 0x04>;
572 clocks = <&clks 162>;
573 fsl,usbphy = <&usbphy1>;
574 fsl,usbmisc = <&usbmisc 0>;
575 status = "disabled";
576 };
577
578 usbh1: usb@02184200 {
579 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
580 reg = <0x02184200 0x200>;
581 interrupts = <0 40 0x04>;
582 clocks = <&clks 162>;
583 fsl,usbphy = <&usbphy2>;
584 fsl,usbmisc = <&usbmisc 1>;
585 status = "disabled";
586 };
587
588 usbh2: usb@02184400 {
589 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
590 reg = <0x02184400 0x200>;
591 interrupts = <0 41 0x04>;
592 clocks = <&clks 162>;
593 fsl,usbmisc = <&usbmisc 2>;
594 status = "disabled";
595 };
596
597 usbh3: usb@02184600 {
598 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
599 reg = <0x02184600 0x200>;
600 interrupts = <0 42 0x04>;
601 clocks = <&clks 162>;
602 fsl,usbmisc = <&usbmisc 3>;
603 status = "disabled";
604 };
605
606 usbmisc: usbmisc: usbmisc@02184800 {
607 #index-cells = <1>;
608 compatible = "fsl,imx6q-usbmisc";
609 reg = <0x02184800 0x200>;
610 clocks = <&clks 162>;
611 };
612
613 fec: ethernet@02188000 {
614 compatible = "fsl,imx6q-fec";
615 reg = <0x02188000 0x4000>;
616 interrupts = <0 118 0x04 0 119 0x04>;
617 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
618 clock-names = "ipg", "ahb", "ptp";
619 status = "disabled";
620 };
621
622 mlb@0218c000 {
623 reg = <0x0218c000 0x4000>;
624 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
625 };
626
627 usdhc1: usdhc@02190000 {
628 compatible = "fsl,imx6q-usdhc";
629 reg = <0x02190000 0x4000>;
630 interrupts = <0 22 0x04>;
631 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
632 clock-names = "ipg", "ahb", "per";
633 bus-width = <4>;
634 status = "disabled";
635 };
636
637 usdhc2: usdhc@02194000 {
638 compatible = "fsl,imx6q-usdhc";
639 reg = <0x02194000 0x4000>;
640 interrupts = <0 23 0x04>;
641 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
642 clock-names = "ipg", "ahb", "per";
643 bus-width = <4>;
644 status = "disabled";
645 };
646
647 usdhc3: usdhc@02198000 {
648 compatible = "fsl,imx6q-usdhc";
649 reg = <0x02198000 0x4000>;
650 interrupts = <0 24 0x04>;
651 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
652 clock-names = "ipg", "ahb", "per";
653 bus-width = <4>;
654 status = "disabled";
655 };
656
657 usdhc4: usdhc@0219c000 {
658 compatible = "fsl,imx6q-usdhc";
659 reg = <0x0219c000 0x4000>;
660 interrupts = <0 25 0x04>;
661 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
662 clock-names = "ipg", "ahb", "per";
663 bus-width = <4>;
664 status = "disabled";
665 };
666
667 i2c1: i2c@021a0000 {
668 #address-cells = <1>;
669 #size-cells = <0>;
670 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
671 reg = <0x021a0000 0x4000>;
672 interrupts = <0 36 0x04>;
673 clocks = <&clks 125>;
674 status = "disabled";
675 };
676
677 i2c2: i2c@021a4000 {
678 #address-cells = <1>;
679 #size-cells = <0>;
680 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
681 reg = <0x021a4000 0x4000>;
682 interrupts = <0 37 0x04>;
683 clocks = <&clks 126>;
684 status = "disabled";
685 };
686
687 i2c3: i2c@021a8000 {
688 #address-cells = <1>;
689 #size-cells = <0>;
690 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
691 reg = <0x021a8000 0x4000>;
692 interrupts = <0 38 0x04>;
693 clocks = <&clks 127>;
694 status = "disabled";
695 };
696
697 romcp@021ac000 {
698 reg = <0x021ac000 0x4000>;
699 };
700
701 mmdc0: mmdc@021b0000 { /* MMDC0 */
702 compatible = "fsl,imx6q-mmdc";
703 reg = <0x021b0000 0x4000>;
704 };
705
706 mmdc1: mmdc@021b4000 { /* MMDC1 */
707 reg = <0x021b4000 0x4000>;
708 };
709
710 weim@021b8000 {
711 reg = <0x021b8000 0x4000>;
712 interrupts = <0 14 0x04>;
713 };
714
715 ocotp@021bc000 {
716 compatible = "fsl,imx6q-ocotp";
717 reg = <0x021bc000 0x4000>;
718 };
719
720 ocotp@021c0000 {
721 reg = <0x021c0000 0x4000>;
722 interrupts = <0 21 0x04>;
723 };
724
725 tzasc@021d0000 { /* TZASC1 */
726 reg = <0x021d0000 0x4000>;
727 interrupts = <0 108 0x04>;
728 };
729
730 tzasc@021d4000 { /* TZASC2 */
731 reg = <0x021d4000 0x4000>;
732 interrupts = <0 109 0x04>;
733 };
734
735 audmux: audmux@021d8000 {
736 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
737 reg = <0x021d8000 0x4000>;
738 status = "disabled";
739 };
740
741 mipi@021dc000 { /* MIPI-CSI */
742 reg = <0x021dc000 0x4000>;
743 };
744
745 mipi@021e0000 { /* MIPI-DSI */
746 reg = <0x021e0000 0x4000>;
747 };
748
749 vdoa@021e4000 {
750 reg = <0x021e4000 0x4000>;
751 interrupts = <0 18 0x04>;
752 };
753
754 uart2: serial@021e8000 {
755 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
756 reg = <0x021e8000 0x4000>;
757 interrupts = <0 27 0x04>;
758 clocks = <&clks 160>, <&clks 161>;
759 clock-names = "ipg", "per";
760 status = "disabled";
761 };
762
763 uart3: serial@021ec000 {
764 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
765 reg = <0x021ec000 0x4000>;
766 interrupts = <0 28 0x04>;
767 clocks = <&clks 160>, <&clks 161>;
768 clock-names = "ipg", "per";
769 status = "disabled";
770 };
771
772 uart4: serial@021f0000 {
773 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
774 reg = <0x021f0000 0x4000>;
775 interrupts = <0 29 0x04>;
776 clocks = <&clks 160>, <&clks 161>;
777 clock-names = "ipg", "per";
778 status = "disabled";
779 };
780
781 uart5: serial@021f4000 {
782 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
783 reg = <0x021f4000 0x4000>;
784 interrupts = <0 30 0x04>;
785 clocks = <&clks 160>, <&clks 161>;
786 clock-names = "ipg", "per";
787 status = "disabled";
788 };
789 };
790
791 ipu1: ipu@02400000 {
792 #crtc-cells = <1>;
793 compatible = "fsl,imx6q-ipu";
794 reg = <0x02400000 0x400000>;
795 interrupts = <0 6 0x4 0 5 0x4>;
796 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
797 clock-names = "bus", "di0", "di1";
798 };
799 };
800};
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index fb7cb841b64c..0f39f8c93b94 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -83,6 +83,7 @@ enum imx5_clks {
83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, 83 ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, 84 epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
85 can_sel, can1_serial_gate, can1_ipg_gate, 85 can_sel, can1_serial_gate, can1_ipg_gate,
86 owire_gate,
86 clk_max 87 clk_max
87}; 88};
88 89
@@ -233,12 +234,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
233 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); 234 clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
234 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); 235 clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
235 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); 236 clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
237 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
236 238
237 for (i = 0; i < ARRAY_SIZE(clk); i++) 239 for (i = 0; i < ARRAY_SIZE(clk); i++)
238 if (IS_ERR(clk[i])) 240 if (IS_ERR(clk[i]))
239 pr_err("i.MX5 clk %d: register failed with %ld\n", 241 pr_err("i.MX5 clk %d: register failed with %ld\n",
240 i, PTR_ERR(clk[i])); 242 i, PTR_ERR(clk[i]));
241 243
242 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); 244 clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
243 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); 245 clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
244 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0"); 246 clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 540138c4606c..7b025ee528a5 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -164,8 +164,8 @@ enum mx6q_clks {
164 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, 164 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
165 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 165 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
166 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 166 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
167 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, 167 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
168 clk_max 168 usbphy2_gate, clk_max
169}; 169};
170 170
171static struct clk *clk[clk_max]; 171static struct clk *clk[clk_max];
@@ -218,8 +218,21 @@ int __init mx6q_clocks_init(void)
218 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 218 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
219 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0); 219 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
220 220
221 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); 221 /*
222 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); 222 * Bit 20 is the reserved and read-only bit, we do this only for:
223 * - Do nothing for usbphy clk_enable/disable
224 * - Keep refcount when do usbphy clk_enable/disable, in that case,
225 * the clk framework may need to enable/disable usbphy's parent
226 */
227 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
228 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
229
230 /*
231 * usbphy*_gate needs to be on after system boots up, and software
232 * never needs to control it anymore.
233 */
234 clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
235 clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
223 236
224 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); 237 clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
225 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); 238 clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
@@ -446,6 +459,11 @@ int __init mx6q_clocks_init(void)
446 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 459 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
447 clk_prepare_enable(clk[clks_init_on[i]]); 460 clk_prepare_enable(clk[clks_init_on[i]]);
448 461
462 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
463 clk_prepare_enable(clk[usbphy1_gate]);
464 clk_prepare_enable(clk[usbphy2_gate]);
465 }
466
449 /* Set initial power mode */ 467 /* Set initial power mode */
450 imx6q_set_lpm(WAIT_CLOCKED); 468 imx6q_set_lpm(WAIT_CLOCKED);
451 469
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 1786b2d1257e..9ffd103b27e4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clkdev.h> 14#include <linux/clkdev.h>
15#include <linux/cpu.h>
15#include <linux/delay.h> 16#include <linux/delay.h>
16#include <linux/export.h> 17#include <linux/export.h>
17#include <linux/init.h> 18#include <linux/init.h>
@@ -22,6 +23,7 @@
22#include <linux/of_address.h> 23#include <linux/of_address.h>
23#include <linux/of_irq.h> 24#include <linux/of_irq.h>
24#include <linux/of_platform.h> 25#include <linux/of_platform.h>
26#include <linux/opp.h>
25#include <linux/phy.h> 27#include <linux/phy.h>
26#include <linux/regmap.h> 28#include <linux/regmap.h>
27#include <linux/micrel_phy.h> 29#include <linux/micrel_phy.h>
@@ -200,6 +202,64 @@ static void __init imx6q_init_machine(void)
200 imx6q_1588_init(); 202 imx6q_1588_init();
201} 203}
202 204
205#define OCOTP_CFG3 0x440
206#define OCOTP_CFG3_SPEED_SHIFT 16
207#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
208
209static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
210{
211 struct device_node *np;
212 void __iomem *base;
213 u32 val;
214
215 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
216 if (!np) {
217 pr_warn("failed to find ocotp node\n");
218 return;
219 }
220
221 base = of_iomap(np, 0);
222 if (!base) {
223 pr_warn("failed to map ocotp\n");
224 goto put_node;
225 }
226
227 val = readl_relaxed(base + OCOTP_CFG3);
228 val >>= OCOTP_CFG3_SPEED_SHIFT;
229 if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
230 if (opp_disable(cpu_dev, 1200000000))
231 pr_warn("failed to disable 1.2 GHz OPP\n");
232
233put_node:
234 of_node_put(np);
235}
236
237static void __init imx6q_opp_init(struct device *cpu_dev)
238{
239 struct device_node *np;
240
241 np = of_find_node_by_path("/cpus/cpu@0");
242 if (!np) {
243 pr_warn("failed to find cpu0 node\n");
244 return;
245 }
246
247 cpu_dev->of_node = np;
248 if (of_init_opp_table(cpu_dev)) {
249 pr_warn("failed to init OPP table\n");
250 goto put_node;
251 }
252
253 imx6q_opp_check_1p2ghz(cpu_dev);
254
255put_node:
256 of_node_put(np);
257}
258
259struct platform_device imx6q_cpufreq_pdev = {
260 .name = "imx6q-cpufreq",
261};
262
203static void __init imx6q_init_late(void) 263static void __init imx6q_init_late(void)
204{ 264{
205 /* 265 /*
@@ -208,6 +268,11 @@ static void __init imx6q_init_late(void)
208 */ 268 */
209 if (imx6q_revision() > IMX_CHIP_REVISION_1_1) 269 if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
210 imx6q_cpuidle_init(); 270 imx6q_cpuidle_init();
271
272 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
273 imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
274 platform_device_register(&imx6q_cpufreq_pdev);
275 }
211} 276}
212 277
213static void __init imx6q_map_io(void) 278static void __init imx6q_map_io(void)
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c
index 372c8c0d54a0..950d354d50e2 100644
--- a/drivers/w1/masters/mxc_w1.c
+++ b/drivers/w1/masters/mxc_w1.c
@@ -157,9 +157,16 @@ static int mxc_w1_remove(struct platform_device *pdev)
157 return 0; 157 return 0;
158} 158}
159 159
160static struct of_device_id mxc_w1_dt_ids[] = {
161 { .compatible = "fsl,imx21-owire" },
162 { /* sentinel */ }
163};
164MODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
165
160static struct platform_driver mxc_w1_driver = { 166static struct platform_driver mxc_w1_driver = {
161 .driver = { 167 .driver = {
162 .name = "mxc_w1", 168 .name = "mxc_w1",
169 .of_match_table = mxc_w1_dt_ids,
163 }, 170 },
164 .probe = mxc_w1_probe, 171 .probe = mxc_w1_probe,
165 .remove = mxc_w1_remove, 172 .remove = mxc_w1_remove,
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 09:49:37 -0500