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-rw-r--r--drivers/gpu/drm/exynos/exynos5433_drm_decon.c92
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c2
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_g2d.c2
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c80
-rw-r--r--include/video/exynos5433_decon.h2
5 files changed, 137 insertions, 41 deletions
diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index d69af00bdd6a..0fd6f7a18364 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -13,9 +13,11 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/component.h> 15#include <linux/component.h>
16#include <linux/mfd/syscon.h>
16#include <linux/of_device.h> 17#include <linux/of_device.h>
17#include <linux/of_gpio.h> 18#include <linux/of_gpio.h>
18#include <linux/pm_runtime.h> 19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
19 21
20#include <video/exynos5433_decon.h> 22#include <video/exynos5433_decon.h>
21 23
@@ -25,6 +27,9 @@
25#include "exynos_drm_plane.h" 27#include "exynos_drm_plane.h"
26#include "exynos_drm_iommu.h" 28#include "exynos_drm_iommu.h"
27 29
30#define DSD_CFG_MUX 0x1004
31#define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
32
28#define WINDOWS_NR 3 33#define WINDOWS_NR 3
29#define MIN_FB_WIDTH_FOR_16WORD_BURST 128 34#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
30 35
@@ -57,6 +62,7 @@ struct decon_context {
57 struct exynos_drm_plane planes[WINDOWS_NR]; 62 struct exynos_drm_plane planes[WINDOWS_NR];
58 struct exynos_drm_plane_config configs[WINDOWS_NR]; 63 struct exynos_drm_plane_config configs[WINDOWS_NR];
59 void __iomem *addr; 64 void __iomem *addr;
65 struct regmap *sysreg;
60 struct clk *clks[ARRAY_SIZE(decon_clks_name)]; 66 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
61 int pipe; 67 int pipe;
62 unsigned long flags; 68 unsigned long flags;
@@ -118,18 +124,29 @@ static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
118 124
119static void decon_setup_trigger(struct decon_context *ctx) 125static void decon_setup_trigger(struct decon_context *ctx)
120{ 126{
121 u32 val = !(ctx->out_type & I80_HW_TRG) 127 if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
122 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 128 return;
123 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN 129
124 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 130 if (!(ctx->out_type & I80_HW_TRG)) {
125 TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN; 131 writel(TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
126 writel(val, ctx->addr + DECON_TRIGCON); 132 | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
133 ctx->addr + DECON_TRIGCON);
134 return;
135 }
136
137 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
138 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
139
140 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
141 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
142 DRM_ERROR("Cannot update sysreg.\n");
127} 143}
128 144
129static void decon_commit(struct exynos_drm_crtc *crtc) 145static void decon_commit(struct exynos_drm_crtc *crtc)
130{ 146{
131 struct decon_context *ctx = crtc->ctx; 147 struct decon_context *ctx = crtc->ctx;
132 struct drm_display_mode *m = &crtc->base.mode; 148 struct drm_display_mode *m = &crtc->base.mode;
149 bool interlaced = false;
133 u32 val; 150 u32 val;
134 151
135 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 152 if (test_bit(BIT_SUSPENDED, &ctx->flags))
@@ -140,13 +157,16 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
140 m->crtc_hsync_end = m->crtc_htotal - 92; 157 m->crtc_hsync_end = m->crtc_htotal - 92;
141 m->crtc_vsync_start = m->crtc_vdisplay + 1; 158 m->crtc_vsync_start = m->crtc_vdisplay + 1;
142 m->crtc_vsync_end = m->crtc_vsync_start + 1; 159 m->crtc_vsync_end = m->crtc_vsync_start + 1;
160 if (m->flags & DRM_MODE_FLAG_INTERLACE)
161 interlaced = true;
143 } 162 }
144 163
145 if (ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)) 164 decon_setup_trigger(ctx);
146 decon_setup_trigger(ctx);
147 165
148 /* lcd on and use command if */ 166 /* lcd on and use command if */
149 val = VIDOUT_LCD_ON; 167 val = VIDOUT_LCD_ON;
168 if (interlaced)
169 val |= VIDOUT_INTERLACE_EN_F;
150 if (ctx->out_type & IFTYPE_I80) { 170 if (ctx->out_type & IFTYPE_I80) {
151 val |= VIDOUT_COMMAND_IF; 171 val |= VIDOUT_COMMAND_IF;
152 } else { 172 } else {
@@ -155,15 +175,21 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
155 175
156 writel(val, ctx->addr + DECON_VIDOUTCON0); 176 writel(val, ctx->addr + DECON_VIDOUTCON0);
157 177
158 val = VIDTCON2_LINEVAL(m->vdisplay - 1) | 178 if (interlaced)
159 VIDTCON2_HOZVAL(m->hdisplay - 1); 179 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
180 VIDTCON2_HOZVAL(m->hdisplay - 1);
181 else
182 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
183 VIDTCON2_HOZVAL(m->hdisplay - 1);
160 writel(val, ctx->addr + DECON_VIDTCON2); 184 writel(val, ctx->addr + DECON_VIDTCON2);
161 185
162 if (!(ctx->out_type & IFTYPE_I80)) { 186 if (!(ctx->out_type & IFTYPE_I80)) {
163 val = VIDTCON00_VBPD_F( 187 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
164 m->crtc_vtotal - m->crtc_vsync_end - 1) | 188 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
165 VIDTCON00_VFPD_F( 189
166 m->crtc_vsync_start - m->crtc_vdisplay - 1); 190 if (interlaced)
191 vbp = vbp / 2 - 1;
192 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
167 writel(val, ctx->addr + DECON_VIDTCON00); 193 writel(val, ctx->addr + DECON_VIDTCON00);
168 194
169 val = VIDTCON01_VSPW_F( 195 val = VIDTCON01_VSPW_F(
@@ -278,12 +304,22 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc,
278 if (test_bit(BIT_SUSPENDED, &ctx->flags)) 304 if (test_bit(BIT_SUSPENDED, &ctx->flags))
279 return; 305 return;
280 306
281 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); 307 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
282 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 308 val = COORDINATE_X(state->crtc.x) |
309 COORDINATE_Y(state->crtc.y / 2);
310 writel(val, ctx->addr + DECON_VIDOSDxA(win));
311
312 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
313 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
314 writel(val, ctx->addr + DECON_VIDOSDxB(win));
315 } else {
316 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
317 writel(val, ctx->addr + DECON_VIDOSDxA(win));
283 318
284 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 319 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
285 COORDINATE_Y(state->crtc.y + state->crtc.h - 1); 320 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
286 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 321 writel(val, ctx->addr + DECON_VIDOSDxB(win));
322 }
287 323
288 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 324 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
289 VIDOSD_Wx_ALPHA_B_F(0x0); 325 VIDOSD_Wx_ALPHA_B_F(0x0);
@@ -355,8 +391,6 @@ static void decon_swreset(struct decon_context *ctx)
355 udelay(10); 391 udelay(10);
356 } 392 }
357 393
358 WARN(tries == 0, "failed to disable DECON\n");
359
360 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); 394 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
361 for (tries = 2000; tries; --tries) { 395 for (tries = 2000; tries; --tries) {
362 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) 396 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
@@ -557,6 +591,13 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id)
557 591
558 if (val) { 592 if (val) {
559 writel(val, ctx->addr + DECON_VIDINTCON1); 593 writel(val, ctx->addr + DECON_VIDINTCON1);
594 if (ctx->out_type & IFTYPE_HDMI) {
595 val = readl(ctx->addr + DECON_VIDOUTCON0);
596 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
597 if (val ==
598 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
599 return IRQ_HANDLED;
600 }
560 drm_crtc_handle_vblank(&ctx->crtc->base); 601 drm_crtc_handle_vblank(&ctx->crtc->base);
561 } 602 }
562 603
@@ -637,6 +678,15 @@ static int exynos5433_decon_probe(struct platform_device *pdev)
637 ctx->out_type |= IFTYPE_I80; 678 ctx->out_type |= IFTYPE_I80;
638 } 679 }
639 680
681 if (ctx->out_type | I80_HW_TRG) {
682 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
683 "samsung,disp-sysreg");
684 if (IS_ERR(ctx->sysreg)) {
685 dev_err(dev, "failed to get system register\n");
686 return PTR_ERR(ctx->sysreg);
687 }
688 }
689
640 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 690 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
641 struct clk *clk; 691 struct clk *clk;
642 692
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 745cfbdf6b39..a9fa444c6053 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -125,10 +125,8 @@ static struct fimd_driver_data exynos3_fimd_driver_data = {
125 .timing_base = 0x20000, 125 .timing_base = 0x20000,
126 .lcdblk_offset = 0x210, 126 .lcdblk_offset = 0x210,
127 .lcdblk_bypass_shift = 1, 127 .lcdblk_bypass_shift = 1,
128 .trg_type = I80_HW_TRG,
129 .has_shadowcon = 1, 128 .has_shadowcon = 1,
130 .has_vidoutcon = 1, 129 .has_vidoutcon = 1,
131 .has_trigger_per_te = 1,
132}; 130};
133 131
134static struct fimd_driver_data exynos4_fimd_driver_data = { 132static struct fimd_driver_data exynos4_fimd_driver_data = {
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 603d8425cca6..2b8bf2dd6387 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -1683,7 +1683,7 @@ struct platform_driver g2d_driver = {
1683 .probe = g2d_probe, 1683 .probe = g2d_probe,
1684 .remove = g2d_remove, 1684 .remove = g2d_remove,
1685 .driver = { 1685 .driver = {
1686 .name = "s5p-g2d", 1686 .name = "exynos-drm-g2d",
1687 .owner = THIS_MODULE, 1687 .owner = THIS_MODULE,
1688 .pm = &g2d_pm_ops, 1688 .pm = &g2d_pm_ops,
1689 .of_match_table = exynos_g2d_match, 1689 .of_match_table = exynos_g2d_match,
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 5ed8b1effe71..88ccc0469316 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -35,6 +35,7 @@
35#include <linux/io.h> 35#include <linux/io.h>
36#include <linux/of_address.h> 36#include <linux/of_address.h>
37#include <linux/of_device.h> 37#include <linux/of_device.h>
38#include <linux/of_graph.h>
38#include <linux/hdmi.h> 39#include <linux/hdmi.h>
39#include <linux/component.h> 40#include <linux/component.h>
40#include <linux/mfd/syscon.h> 41#include <linux/mfd/syscon.h>
@@ -133,6 +134,7 @@ struct hdmi_context {
133 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; 134 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)];
134 struct regulator *reg_hdmi_en; 135 struct regulator *reg_hdmi_en;
135 struct exynos_drm_clk phy_clk; 136 struct exynos_drm_clk phy_clk;
137 struct drm_bridge *bridge;
136}; 138};
137 139
138static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) 140static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
@@ -509,9 +511,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
509 { 511 {
510 .pixel_clock = 27000000, 512 .pixel_clock = 27000000,
511 .conf = { 513 .conf = {
512 0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46, 514 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02,
513 0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5, 515 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
514 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30, 516 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
515 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 517 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
516 }, 518 },
517 }, 519 },
@@ -519,9 +521,9 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
519 .pixel_clock = 27027000, 521 .pixel_clock = 27027000,
520 .conf = { 522 .conf = {
521 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3, 523 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
522 0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5, 524 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac,
523 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30, 525 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
524 0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 526 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
525 }, 527 },
526 }, 528 },
527 { 529 {
@@ -587,6 +589,15 @@ static const struct hdmiphy_config hdmiphy_5433_configs[] = {
587 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, 589 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
588 }, 590 },
589 }, 591 },
592 {
593 .pixel_clock = 297000000,
594 .conf = {
595 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2,
596 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
597 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
598 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
599 },
600 },
590}; 601};
591 602
592static const char * const hdmi_clk_gates4[] = { 603static const char * const hdmi_clk_gates4[] = {
@@ -788,7 +799,8 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata)
788 sizeof(buf)); 799 sizeof(buf));
789 if (ret > 0) { 800 if (ret > 0) {
790 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC); 801 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
791 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, ret); 802 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3);
803 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3);
792 } 804 }
793 805
794 ret = hdmi_audio_infoframe_init(&frm.audio); 806 ret = hdmi_audio_infoframe_init(&frm.audio);
@@ -912,7 +924,15 @@ static int hdmi_create_connector(struct drm_encoder *encoder)
912 drm_connector_register(connector); 924 drm_connector_register(connector);
913 drm_mode_connector_attach_encoder(connector, encoder); 925 drm_mode_connector_attach_encoder(connector, encoder);
914 926
915 return 0; 927 if (hdata->bridge) {
928 encoder->bridge = hdata->bridge;
929 hdata->bridge->encoder = encoder;
930 ret = drm_bridge_attach(encoder, hdata->bridge, NULL);
931 if (ret)
932 DRM_ERROR("Failed to attach bridge\n");
933 }
934
935 return ret;
916} 936}
917 937
918static bool hdmi_mode_fixup(struct drm_encoder *encoder, 938static bool hdmi_mode_fixup(struct drm_encoder *encoder,
@@ -1581,6 +1601,31 @@ static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable)
1581 hdmiphy_disable(hdata); 1601 hdmiphy_disable(hdata);
1582} 1602}
1583 1603
1604static int hdmi_bridge_init(struct hdmi_context *hdata)
1605{
1606 struct device *dev = hdata->dev;
1607 struct device_node *ep, *np;
1608
1609 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1);
1610 if (!ep)
1611 return 0;
1612
1613 np = of_graph_get_remote_port_parent(ep);
1614 of_node_put(ep);
1615 if (!np) {
1616 DRM_ERROR("failed to get remote port parent");
1617 return -EINVAL;
1618 }
1619
1620 hdata->bridge = of_drm_find_bridge(np);
1621 of_node_put(np);
1622
1623 if (!hdata->bridge)
1624 return -EPROBE_DEFER;
1625
1626 return 0;
1627}
1628
1584static int hdmi_resources_init(struct hdmi_context *hdata) 1629static int hdmi_resources_init(struct hdmi_context *hdata)
1585{ 1630{
1586 struct device *dev = hdata->dev; 1631 struct device *dev = hdata->dev;
@@ -1620,17 +1665,18 @@ static int hdmi_resources_init(struct hdmi_context *hdata)
1620 1665
1621 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en"); 1666 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1622 1667
1623 if (PTR_ERR(hdata->reg_hdmi_en) == -ENODEV) 1668 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) {
1624 return 0; 1669 if (IS_ERR(hdata->reg_hdmi_en))
1670 return PTR_ERR(hdata->reg_hdmi_en);
1625 1671
1626 if (IS_ERR(hdata->reg_hdmi_en)) 1672 ret = regulator_enable(hdata->reg_hdmi_en);
1627 return PTR_ERR(hdata->reg_hdmi_en); 1673 if (ret) {
1628 1674 DRM_ERROR("failed to enable hdmi-en regulator\n");
1629 ret = regulator_enable(hdata->reg_hdmi_en); 1675 return ret;
1630 if (ret) 1676 }
1631 DRM_ERROR("failed to enable hdmi-en regulator\n"); 1677 }
1632 1678
1633 return ret; 1679 return hdmi_bridge_init(hdata);
1634} 1680}
1635 1681
1636static struct of_device_id hdmi_match_types[] = { 1682static struct of_device_id hdmi_match_types[] = {
diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
index 0098a522d9f4..ef8e2a8ad0af 100644
--- a/include/video/exynos5433_decon.h
+++ b/include/video/exynos5433_decon.h
@@ -89,6 +89,8 @@
89#define VIDCON0_ENVID_F (1 << 0) 89#define VIDCON0_ENVID_F (1 << 0)
90 90
91/* VIDOUTCON0 */ 91/* VIDOUTCON0 */
92#define VIDOUT_INTERLACE_FIELD_F (1 << 29)
93#define VIDOUT_INTERLACE_EN_F (1 << 28)
92#define VIDOUT_LCD_ON (1 << 24) 94#define VIDOUT_LCD_ON (1 << 24)
93#define VIDOUT_IF_F_MASK (0x3 << 20) 95#define VIDOUT_IF_F_MASK (0x3 << 20)
94#define VIDOUT_RGB_IF (0x0 << 20) 96#define VIDOUT_RGB_IF (0x0 << 20)