3 files changed, 5 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a0f8913a76f8..7a0e4d6c71e2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1601,6 +1601,9 @@ static int intel_runtime_resume(struct device *device)
         if (IS_BROXTON(dev)) {
                 bxt_disable_dc9(dev_priv);
                 bxt_display_core_init(dev_priv, true);
+                if (dev_priv->csr.dmc_payload &&
+                    (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+                        gen9_enable_dc5(dev_priv);
         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
                 hsw_disable_pc8(dev_priv);
         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5464632d466c..b9f1304439e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1238,6 +1238,7 @@ void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
+void gen9_enable_dc5(struct drm_i915_private *dev_priv);
 void skl_init_cdclk(struct drm_i915_private *dev_priv);
 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8fff0800b4ed..7fb1da4e7fc3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -582,7 +582,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
         assert_csr_loaded(dev_priv);
 }
 
-static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
+void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
         assert_can_enable_dc5(dev_priv);