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-rw-r--r--arch/parisc/include/asm/cacheflush.h2
-rw-r--r--arch/parisc/include/asm/uaccess.h6
-rw-r--r--arch/parisc/kernel/cache.c18
-rw-r--r--arch/parisc/kernel/signal.c13
-rw-r--r--arch/parisc/mm/fault.c4
-rw-r--r--drivers/parisc/ccio-dma.c6
-rw-r--r--drivers/parisc/eisa.c122
7 files changed, 83 insertions, 88 deletions
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index 7bd69bd43a01..19c9c3c5f267 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -27,8 +27,6 @@ void flush_user_dcache_range_asm(unsigned long, unsigned long);
27void flush_kernel_dcache_range_asm(unsigned long, unsigned long); 27void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
28void flush_kernel_dcache_page_asm(void *); 28void flush_kernel_dcache_page_asm(void *);
29void flush_kernel_icache_page(void *); 29void flush_kernel_icache_page(void *);
30void flush_user_dcache_range(unsigned long, unsigned long);
31void flush_user_icache_range(unsigned long, unsigned long);
32 30
33/* Cache flush operations */ 31/* Cache flush operations */
34 32
diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h
index 9a2aee1b90fc..fb4382c28259 100644
--- a/arch/parisc/include/asm/uaccess.h
+++ b/arch/parisc/include/asm/uaccess.h
@@ -32,11 +32,7 @@
32 * that put_user is the same as __put_user, etc. 32 * that put_user is the same as __put_user, etc.
33 */ 33 */
34 34
35static inline long access_ok(int type, const void __user * addr, 35#define access_ok(type, uaddr, size) (1)
36 unsigned long size)
37{
38 return 1;
39}
40 36
41#define put_user __put_user 37#define put_user __put_user
42#define get_user __get_user 38#define get_user __get_user
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index 7820b864de1a..0dc72d5de861 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -574,24 +574,6 @@ void flush_cache_mm(struct mm_struct *mm)
574 } 574 }
575} 575}
576 576
577void
578flush_user_dcache_range(unsigned long start, unsigned long end)
579{
580 if ((end - start) < parisc_cache_flush_threshold)
581 flush_user_dcache_range_asm(start,end);
582 else
583 flush_data_cache();
584}
585
586void
587flush_user_icache_range(unsigned long start, unsigned long end)
588{
589 if ((end - start) < parisc_cache_flush_threshold)
590 flush_user_icache_range_asm(start,end);
591 else
592 flush_instruction_cache();
593}
594
595void flush_cache_range(struct vm_area_struct *vma, 577void flush_cache_range(struct vm_area_struct *vma,
596 unsigned long start, unsigned long end) 578 unsigned long start, unsigned long end)
597{ 579{
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index 9e03296641d7..26f12f45b4bb 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -233,6 +233,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs,
233 struct rt_sigframe __user *frame; 233 struct rt_sigframe __user *frame;
234 unsigned long rp, usp; 234 unsigned long rp, usp;
235 unsigned long haddr, sigframe_size; 235 unsigned long haddr, sigframe_size;
236 unsigned long start, end;
236 int err = 0; 237 int err = 0;
237#ifdef CONFIG_64BIT 238#ifdef CONFIG_64BIT
238 struct compat_rt_sigframe __user * compat_frame; 239 struct compat_rt_sigframe __user * compat_frame;
@@ -300,10 +301,10 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs,
300 } 301 }
301#endif 302#endif
302 303
303 flush_user_dcache_range((unsigned long) &frame->tramp[0], 304 start = (unsigned long) &frame->tramp[0];
304 (unsigned long) &frame->tramp[TRAMP_SIZE]); 305 end = (unsigned long) &frame->tramp[TRAMP_SIZE];
305 flush_user_icache_range((unsigned long) &frame->tramp[0], 306 flush_user_dcache_range_asm(start, end);
306 (unsigned long) &frame->tramp[TRAMP_SIZE]); 307 flush_user_icache_range_asm(start, end);
307 308
308 /* TRAMP Words 0-4, Length 5 = SIGRESTARTBLOCK_TRAMP 309 /* TRAMP Words 0-4, Length 5 = SIGRESTARTBLOCK_TRAMP
309 * TRAMP Words 5-9, Length 4 = SIGRETURN_TRAMP 310 * TRAMP Words 5-9, Length 4 = SIGRETURN_TRAMP
@@ -549,8 +550,8 @@ insert_restart_trampoline(struct pt_regs *regs)
549 WARN_ON(err); 550 WARN_ON(err);
550 551
551 /* flush data/instruction cache for new insns */ 552 /* flush data/instruction cache for new insns */
552 flush_user_dcache_range(start, end); 553 flush_user_dcache_range_asm(start, end);
553 flush_user_icache_range(start, end); 554 flush_user_icache_range_asm(start, end);
554 555
555 regs->gr[31] = regs->gr[30] + 8; 556 regs->gr[31] = regs->gr[30] + 8;
556 return; 557 return;
diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c
index c3cac4ddfe9c..deab89a8915a 100644
--- a/arch/parisc/mm/fault.c
+++ b/arch/parisc/mm/fault.c
@@ -239,8 +239,8 @@ show_signal_msg(struct pt_regs *regs, unsigned long code,
239 vma ? ',':'\n'); 239 vma ? ',':'\n');
240 240
241 if (vma) 241 if (vma)
242 pr_warn(KERN_CONT " vm_start = 0x%08lx, vm_end = 0x%08lx\n", 242 pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
243 vma->vm_start, vma->vm_end); 243 vma->vm_start, vma->vm_end);
244 244
245 show_regs(regs); 245 show_regs(regs);
246} 246}
diff --git a/drivers/parisc/ccio-dma.c b/drivers/parisc/ccio-dma.c
index aeb073b5fe16..e32ca2ef9e54 100644
--- a/drivers/parisc/ccio-dma.c
+++ b/drivers/parisc/ccio-dma.c
@@ -1539,7 +1539,7 @@ static int __init ccio_probe(struct parisc_device *dev)
1539 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL); 1539 ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL);
1540 if (ioc == NULL) { 1540 if (ioc == NULL) {
1541 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n"); 1541 printk(KERN_ERR MODULE_NAME ": memory allocation failure\n");
1542 return 1; 1542 return -ENOMEM;
1543 } 1543 }
1544 1544
1545 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn"; 1545 ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn";
@@ -1554,6 +1554,10 @@ static int __init ccio_probe(struct parisc_device *dev)
1554 1554
1555 ioc->hw_path = dev->hw_path; 1555 ioc->hw_path = dev->hw_path;
1556 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096); 1556 ioc->ioc_regs = ioremap_nocache(dev->hpa.start, 4096);
1557 if (!ioc->ioc_regs) {
1558 kfree(ioc);
1559 return -ENOMEM;
1560 }
1557 ccio_ioc_init(ioc); 1561 ccio_ioc_init(ioc);
1558 ccio_init_resources(ioc); 1562 ccio_init_resources(ioc);
1559 hppa_dma_ops = &ccio_ops; 1563 hppa_dma_ops = &ccio_ops;
diff --git a/drivers/parisc/eisa.c b/drivers/parisc/eisa.c
index 103095bbe8c0..7e2f6d5a6aaf 100644
--- a/drivers/parisc/eisa.c
+++ b/drivers/parisc/eisa.c
@@ -14,16 +14,16 @@
14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are 14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * dealt with elsewhere; this file is concerned only with the EISA portions 15 * dealt with elsewhere; this file is concerned only with the EISA portions
16 * of Wax. 16 * of Wax.
17 * 17 *
18 * 18 *
19 * HINT: 19 * HINT:
20 * ----- 20 * -----
21 * To allow an ISA card to work properly in the EISA slot you need to 21 * To allow an ISA card to work properly in the EISA slot you need to
22 * set an edge trigger level. This may be done on the palo command line 22 * set an edge trigger level. This may be done on the palo command line
23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with 23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24 * n and n2 as the irq levels you want to use. 24 * n and n2 as the irq levels you want to use.
25 * 25 *
26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at 26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27 * irq levels 10 and 11. 27 * irq levels 10 and 11.
28 */ 28 */
29 29
@@ -46,9 +46,9 @@
46#include <asm/eisa_eeprom.h> 46#include <asm/eisa_eeprom.h>
47 47
48#if 0 48#if 0
49#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg ) 49#define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg)
50#else 50#else
51#define EISA_DBG(msg, arg... ) 51#define EISA_DBG(msg, arg...)
52#endif 52#endif
53 53
54#define SNAKES_EEPROM_BASE_ADDR 0xF0810400 54#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
@@ -108,7 +108,7 @@ void eisa_out8(unsigned char data, unsigned short port)
108 108
109void eisa_out16(unsigned short data, unsigned short port) 109void eisa_out16(unsigned short data, unsigned short port)
110{ 110{
111 if (EISA_bus) 111 if (EISA_bus)
112 gsc_writew(cpu_to_le16(data), eisa_permute(port)); 112 gsc_writew(cpu_to_le16(data), eisa_permute(port));
113} 113}
114 114
@@ -135,9 +135,9 @@ static int master_mask;
135static int slave_mask; 135static int slave_mask;
136 136
137/* the trig level can be set with the 137/* the trig level can be set with the
138 * eisa_irq_edge=n,n,n commandline parameter 138 * eisa_irq_edge=n,n,n commandline parameter
139 * We should really read this from the EEPROM 139 * We should really read this from the EEPROM
140 * in the furure. 140 * in the furure.
141 */ 141 */
142/* irq 13,8,2,1,0 must be edge */ 142/* irq 13,8,2,1,0 must be edge */
143static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */ 143static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */
@@ -170,7 +170,7 @@ static void eisa_unmask_irq(struct irq_data *d)
170 unsigned int irq = d->irq; 170 unsigned int irq = d->irq;
171 unsigned long flags; 171 unsigned long flags;
172 EISA_DBG("enable irq %d\n", irq); 172 EISA_DBG("enable irq %d\n", irq);
173 173
174 spin_lock_irqsave(&eisa_irq_lock, flags); 174 spin_lock_irqsave(&eisa_irq_lock, flags);
175 if (irq & 8) { 175 if (irq & 8) {
176 slave_mask &= ~(1 << (irq&7)); 176 slave_mask &= ~(1 << (irq&7));
@@ -194,7 +194,7 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
194{ 194{
195 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */ 195 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
196 unsigned long flags; 196 unsigned long flags;
197 197
198 spin_lock_irqsave(&eisa_irq_lock, flags); 198 spin_lock_irqsave(&eisa_irq_lock, flags);
199 /* read IRR command */ 199 /* read IRR command */
200 eisa_out8(0x0a, 0x20); 200 eisa_out8(0x0a, 0x20);
@@ -202,31 +202,31 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
202 202
203 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n", 203 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
204 irq, eisa_in8(0x20), eisa_in8(0xa0)); 204 irq, eisa_in8(0x20), eisa_in8(0xa0));
205 205
206 /* read ISR command */ 206 /* read ISR command */
207 eisa_out8(0x0a, 0x20); 207 eisa_out8(0x0a, 0x20);
208 eisa_out8(0x0a, 0xa0); 208 eisa_out8(0x0a, 0xa0);
209 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n", 209 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
210 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1)); 210 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
211 211
212 irq &= 0xf; 212 irq &= 0xf;
213 213
214 /* mask irq and write eoi */ 214 /* mask irq and write eoi */
215 if (irq & 8) { 215 if (irq & 8) {
216 slave_mask |= (1 << (irq&7)); 216 slave_mask |= (1 << (irq&7));
217 eisa_out8(slave_mask, 0xa1); 217 eisa_out8(slave_mask, 0xa1);
218 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */ 218 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
219 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 219 eisa_out8(0x62, 0x20); /* 'Specific EOI' to master-IRQ2 */
220 220
221 } else { 221 } else {
222 master_mask |= (1 << (irq&7)); 222 master_mask |= (1 << (irq&7));
223 eisa_out8(master_mask, 0x21); 223 eisa_out8(master_mask, 0x21);
224 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */ 224 eisa_out8(0x60|irq, 0x20); /* 'Specific EOI' to master */
225 } 225 }
226 spin_unlock_irqrestore(&eisa_irq_lock, flags); 226 spin_unlock_irqrestore(&eisa_irq_lock, flags);
227 227
228 generic_handle_irq(irq); 228 generic_handle_irq(irq);
229 229
230 spin_lock_irqsave(&eisa_irq_lock, flags); 230 spin_lock_irqsave(&eisa_irq_lock, flags);
231 /* unmask */ 231 /* unmask */
232 if (irq & 8) { 232 if (irq & 8) {
@@ -254,44 +254,44 @@ static struct irqaction irq2_action = {
254static void init_eisa_pic(void) 254static void init_eisa_pic(void)
255{ 255{
256 unsigned long flags; 256 unsigned long flags;
257 257
258 spin_lock_irqsave(&eisa_irq_lock, flags); 258 spin_lock_irqsave(&eisa_irq_lock, flags);
259 259
260 eisa_out8(0xff, 0x21); /* mask during init */ 260 eisa_out8(0xff, 0x21); /* mask during init */
261 eisa_out8(0xff, 0xa1); /* mask during init */ 261 eisa_out8(0xff, 0xa1); /* mask during init */
262 262
263 /* master pic */ 263 /* master pic */
264 eisa_out8(0x11,0x20); /* ICW1 */ 264 eisa_out8(0x11, 0x20); /* ICW1 */
265 eisa_out8(0x00,0x21); /* ICW2 */ 265 eisa_out8(0x00, 0x21); /* ICW2 */
266 eisa_out8(0x04,0x21); /* ICW3 */ 266 eisa_out8(0x04, 0x21); /* ICW3 */
267 eisa_out8(0x01,0x21); /* ICW4 */ 267 eisa_out8(0x01, 0x21); /* ICW4 */
268 eisa_out8(0x40,0x20); /* OCW2 */ 268 eisa_out8(0x40, 0x20); /* OCW2 */
269 269
270 /* slave pic */ 270 /* slave pic */
271 eisa_out8(0x11,0xa0); /* ICW1 */ 271 eisa_out8(0x11, 0xa0); /* ICW1 */
272 eisa_out8(0x08,0xa1); /* ICW2 */ 272 eisa_out8(0x08, 0xa1); /* ICW2 */
273 eisa_out8(0x02,0xa1); /* ICW3 */ 273 eisa_out8(0x02, 0xa1); /* ICW3 */
274 eisa_out8(0x01,0xa1); /* ICW4 */ 274 eisa_out8(0x01, 0xa1); /* ICW4 */
275 eisa_out8(0x40,0xa0); /* OCW2 */ 275 eisa_out8(0x40, 0xa0); /* OCW2 */
276 276
277 udelay(100); 277 udelay(100);
278 278
279 slave_mask = 0xff; 279 slave_mask = 0xff;
280 master_mask = 0xfb; 280 master_mask = 0xfb;
281 eisa_out8(slave_mask, 0xa1); /* OCW1 */ 281 eisa_out8(slave_mask, 0xa1); /* OCW1 */
282 eisa_out8(master_mask, 0x21); /* OCW1 */ 282 eisa_out8(master_mask, 0x21); /* OCW1 */
283 283
284 /* setup trig level */ 284 /* setup trig level */
285 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level); 285 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
286 286
287 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */ 287 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
288 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1); 288 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
289 289
290 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21)); 290 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
291 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1)); 291 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
292 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0)); 292 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
293 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1)); 293 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
294 294
295 spin_unlock_irqrestore(&eisa_irq_lock, flags); 295 spin_unlock_irqrestore(&eisa_irq_lock, flags);
296} 296}
297 297
@@ -305,7 +305,7 @@ static int __init eisa_probe(struct parisc_device *dev)
305 305
306 char *name = is_mongoose(dev) ? "Mongoose" : "Wax"; 306 char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
307 307
308 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n", 308 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
309 name, (unsigned long)dev->hpa.start); 309 name, (unsigned long)dev->hpa.start);
310 310
311 eisa_dev.hba.dev = dev; 311 eisa_dev.hba.dev = dev;
@@ -334,16 +334,16 @@ static int __init eisa_probe(struct parisc_device *dev)
334 result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev); 334 result = request_irq(dev->irq, eisa_irq, IRQF_SHARED, "EISA", &eisa_dev);
335 if (result) { 335 if (result) {
336 printk(KERN_ERR "EISA: request_irq failed!\n"); 336 printk(KERN_ERR "EISA: request_irq failed!\n");
337 return result; 337 goto error_release;
338 } 338 }
339 339
340 /* Reserve IRQ2 */ 340 /* Reserve IRQ2 */
341 setup_irq(2, &irq2_action); 341 setup_irq(2, &irq2_action);
342 for (i = 0; i < 16; i++) { 342 for (i = 0; i < 16; i++) {
343 irq_set_chip_and_handler(i, &eisa_interrupt_type, 343 irq_set_chip_and_handler(i, &eisa_interrupt_type,
344 handle_simple_irq); 344 handle_simple_irq);
345 } 345 }
346 346
347 EISA_bus = 1; 347 EISA_bus = 1;
348 348
349 if (dev->num_addrs) { 349 if (dev->num_addrs) {
@@ -358,6 +358,11 @@ static int __init eisa_probe(struct parisc_device *dev)
358 } 358 }
359 } 359 }
360 eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH); 360 eisa_eeprom_addr = ioremap_nocache(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
361 if (!eisa_eeprom_addr) {
362 result = -ENOMEM;
363 printk(KERN_ERR "EISA: ioremap_nocache failed!\n");
364 goto error_free_irq;
365 }
361 result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, 366 result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
362 &eisa_dev.hba.lmmio_space); 367 &eisa_dev.hba.lmmio_space);
363 init_eisa_pic(); 368 init_eisa_pic();
@@ -372,11 +377,20 @@ static int __init eisa_probe(struct parisc_device *dev)
372 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */ 377 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
373 if (eisa_root_register (&eisa_dev.root)) { 378 if (eisa_root_register (&eisa_dev.root)) {
374 printk(KERN_ERR "EISA: Failed to register EISA root\n"); 379 printk(KERN_ERR "EISA: Failed to register EISA root\n");
375 return -1; 380 result = -ENOMEM;
381 goto error_iounmap;
376 } 382 }
377 } 383 }
378 384
379 return 0; 385 return 0;
386
387error_iounmap:
388 iounmap(eisa_eeprom_addr);
389error_free_irq:
390 free_irq(dev->irq, &eisa_dev);
391error_release:
392 release_resource(&eisa_dev.hba.io_space);
393 return result;
380} 394}
381 395
382static const struct parisc_device_id eisa_tbl[] = { 396static const struct parisc_device_id eisa_tbl[] = {
@@ -404,7 +418,7 @@ void eisa_make_irq_level(int num)
404{ 418{
405 if (eisa_irq_configured& (1<<num)) { 419 if (eisa_irq_configured& (1<<num)) {
406 printk(KERN_WARNING 420 printk(KERN_WARNING
407 "IRQ %d polarity configured twice (last to level)\n", 421 "IRQ %d polarity configured twice (last to level)\n",
408 num); 422 num);
409 } 423 }
410 eisa_irq_level |= (1<<num); /* set the corresponding bit */ 424 eisa_irq_level |= (1<<num); /* set the corresponding bit */
@@ -414,7 +428,7 @@ void eisa_make_irq_level(int num)
414void eisa_make_irq_edge(int num) 428void eisa_make_irq_edge(int num)
415{ 429{
416 if (eisa_irq_configured& (1<<num)) { 430 if (eisa_irq_configured& (1<<num)) {
417 printk(KERN_WARNING 431 printk(KERN_WARNING
418 "IRQ %d polarity configured twice (last to edge)\n", 432 "IRQ %d polarity configured twice (last to edge)\n",
419 num); 433 num);
420 } 434 }
@@ -430,18 +444,18 @@ static int __init eisa_irq_setup(char *str)
430 EISA_DBG("IRQ setup\n"); 444 EISA_DBG("IRQ setup\n");
431 while (cur != NULL) { 445 while (cur != NULL) {
432 char *pe; 446 char *pe;
433 447
434 val = (int) simple_strtoul(cur, &pe, 0); 448 val = (int) simple_strtoul(cur, &pe, 0);
435 if (val > 15 || val < 0) { 449 if (val > 15 || val < 0) {
436 printk(KERN_ERR "eisa: EISA irq value are 0-15\n"); 450 printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
437 continue; 451 continue;
438 } 452 }
439 if (val == 2) { 453 if (val == 2) {
440 val = 9; 454 val = 9;
441 } 455 }
442 eisa_make_irq_edge(val); /* clear the corresponding bit */ 456 eisa_make_irq_edge(val); /* clear the corresponding bit */
443 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val); 457 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
444 458
445 if ((cur = strchr(cur, ','))) { 459 if ((cur = strchr(cur, ','))) {
446 cur++; 460 cur++;
447 } else { 461 } else {