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-rw-r--r--drivers/gpu/drm/radeon/r100.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
-rw-r--r--drivers/gpu/drm/radeon/rs600.c25
-rw-r--r--drivers/gpu/drm/radeon/rs600d.h53
-rw-r--r--drivers/gpu/drm/radeon/rs690.c35
-rw-r--r--drivers/gpu/drm/radeon/rs690d.h3
-rw-r--r--drivers/gpu/drm/radeon/rv515.c35
9 files changed, 155 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 739a44783ef5..138ddd49dfc5 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2389,6 +2389,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2389 uint32_t pixel_bytes1 = 0; 2389 uint32_t pixel_bytes1 = 0;
2390 uint32_t pixel_bytes2 = 0; 2390 uint32_t pixel_bytes2 = 0;
2391 2391
2392 radeon_update_display_priority(rdev);
2393
2392 if (rdev->mode_info.crtcs[0]->base.enabled) { 2394 if (rdev->mode_info.crtcs[0]->base.enabled) {
2393 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2395 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2394 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2396 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 4ee5cb98956d..1710b9e3ef7d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -91,6 +91,7 @@ extern int radeon_tv;
91extern int radeon_new_pll; 91extern int radeon_new_pll;
92extern int radeon_dynpm; 92extern int radeon_dynpm;
93extern int radeon_audio; 93extern int radeon_audio;
94extern int radeon_disp_priority;
94 95
95/* 96/*
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting 97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -1181,6 +1182,7 @@ extern int radeon_modeset_init(struct radeon_device *rdev);
1181extern void radeon_modeset_fini(struct radeon_device *rdev); 1182extern void radeon_modeset_fini(struct radeon_device *rdev);
1182extern bool radeon_card_posted(struct radeon_device *rdev); 1183extern bool radeon_card_posted(struct radeon_device *rdev);
1183extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1184extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1185extern void radeon_update_display_priority(struct radeon_device *rdev);
1184extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1186extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1185extern int radeon_clocks_init(struct radeon_device *rdev); 1187extern int radeon_clocks_init(struct radeon_device *rdev);
1186extern void radeon_clocks_fini(struct radeon_device *rdev); 1188extern void radeon_clocks_fini(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index eca714c381de..b8d672828246 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -971,6 +971,23 @@ static int radeon_modeset_create_props(struct radeon_device *rdev)
971 return 0; 971 return 0;
972} 972}
973 973
974void radeon_update_display_priority(struct radeon_device *rdev)
975{
976 /* adjustment options for the display watermarks */
977 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
978 /* set display priority to high for r3xx, rv515 chips
979 * this avoids flickering due to underflow to the
980 * display controllers during heavy acceleration.
981 */
982 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515))
983 rdev->disp_priority = 2;
984 else
985 rdev->disp_priority = 0;
986 } else
987 rdev->disp_priority = radeon_disp_priority;
988
989}
990
974int radeon_modeset_init(struct radeon_device *rdev) 991int radeon_modeset_init(struct radeon_device *rdev)
975{ 992{
976 int i; 993 int i;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 54ec04928d9f..6fd511eec96c 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -92,6 +92,7 @@ int radeon_tv = 1;
92int radeon_new_pll = -1; 92int radeon_new_pll = -1;
93int radeon_dynpm = -1; 93int radeon_dynpm = -1;
94int radeon_audio = 1; 94int radeon_audio = 1;
95int radeon_disp_priority = 0;
95 96
96MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 97MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
97module_param_named(no_wb, radeon_no_wb, int, 0444); 98module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -135,6 +136,9 @@ module_param_named(dynpm, radeon_dynpm, int, 0444);
135MODULE_PARM_DESC(audio, "Audio enable (0 = disable)"); 136MODULE_PARM_DESC(audio, "Audio enable (0 = disable)");
136module_param_named(audio, radeon_audio, int, 0444); 137module_param_named(audio, radeon_audio, int, 0444);
137 138
139MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
140module_param_named(disp_priority, radeon_disp_priority, int, 0444);
141
138static int radeon_suspend(struct drm_device *dev, pm_message_t state) 142static int radeon_suspend(struct drm_device *dev, pm_message_t state)
139{ 143{
140 drm_radeon_private_t *dev_priv = dev->dev_private; 144 drm_radeon_private_t *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 30c4b46f3521..abf824c2123d 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -483,7 +483,30 @@ void rs600_mc_init(struct radeon_device *rdev)
483 483
484void rs600_bandwidth_update(struct radeon_device *rdev) 484void rs600_bandwidth_update(struct radeon_device *rdev)
485{ 485{
486 /* FIXME: implement, should this be like rs690 ? */ 486 struct drm_display_mode *mode0 = NULL;
487 struct drm_display_mode *mode1 = NULL;
488 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
489 /* FIXME: implement full support */
490
491 radeon_update_display_priority(rdev);
492
493 if (rdev->mode_info.crtcs[0]->base.enabled)
494 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
495 if (rdev->mode_info.crtcs[1]->base.enabled)
496 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
497
498 rs690_line_buffer_adjust(rdev, mode0, mode1);
499
500 if (rdev->disp_priority == 2) {
501 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
502 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
503 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
504 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
505 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
506 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
507 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
508 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
509 }
487} 510}
488 511
489uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 512uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
diff --git a/drivers/gpu/drm/radeon/rs600d.h b/drivers/gpu/drm/radeon/rs600d.h
index c1c8f5885cbb..e52d2695510b 100644
--- a/drivers/gpu/drm/radeon/rs600d.h
+++ b/drivers/gpu/drm/radeon/rs600d.h
@@ -535,4 +535,57 @@
535#define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) 535#define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1)
536#define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF 536#define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF
537 537
538#define R_006548_D1MODE_PRIORITY_A_CNT 0x006548
539#define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0)
540#define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF)
541#define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000
542#define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)
543#define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)
544#define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF
545#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)
546#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)
547#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF
548#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)
549#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)
550#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF
551#define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C
552#define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0)
553#define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF)
554#define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000
555#define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16)
556#define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1)
557#define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF
558#define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20)
559#define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1)
560#define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF
561#define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24)
562#define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1)
563#define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF
564#define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48
565#define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0)
566#define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF)
567#define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000
568#define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)
569#define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)
570#define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF
571#define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)
572#define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)
573#define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF
574#define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)
575#define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)
576#define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF
577#define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C
578#define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0)
579#define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF)
580#define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000
581#define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16)
582#define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1)
583#define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF
584#define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20)
585#define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1)
586#define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF
587#define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24)
588#define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1)
589#define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF
590
538#endif 591#endif
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index f758d5cc1160..bbf3da790fd5 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -400,10 +400,12 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
400 struct drm_display_mode *mode1 = NULL; 400 struct drm_display_mode *mode1 = NULL;
401 struct rs690_watermark wm0; 401 struct rs690_watermark wm0;
402 struct rs690_watermark wm1; 402 struct rs690_watermark wm1;
403 u32 tmp; 403 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
404 fixed20_12 priority_mark02, priority_mark12, fill_rate; 404 fixed20_12 priority_mark02, priority_mark12, fill_rate;
405 fixed20_12 a, b; 405 fixed20_12 a, b;
406 406
407 radeon_update_display_priority(rdev);
408
407 if (rdev->mode_info.crtcs[0]->base.enabled) 409 if (rdev->mode_info.crtcs[0]->base.enabled)
408 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 410 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
409 if (rdev->mode_info.crtcs[1]->base.enabled) 411 if (rdev->mode_info.crtcs[1]->base.enabled)
@@ -413,7 +415,8 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
413 * modes if the user specifies HIGH for displaypriority 415 * modes if the user specifies HIGH for displaypriority
414 * option. 416 * option.
415 */ 417 */
416 if (rdev->disp_priority == 2) { 418 if ((rdev->disp_priority == 2) &&
419 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
417 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 420 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
418 tmp &= C_000104_MC_DISP0R_INIT_LAT; 421 tmp &= C_000104_MC_DISP0R_INIT_LAT;
419 tmp &= C_000104_MC_DISP1R_INIT_LAT; 422 tmp &= C_000104_MC_DISP1R_INIT_LAT;
@@ -488,10 +491,16 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
488 priority_mark12.full = 0; 491 priority_mark12.full = 0;
489 if (wm1.priority_mark_max.full > priority_mark12.full) 492 if (wm1.priority_mark_max.full > priority_mark12.full)
490 priority_mark12.full = wm1.priority_mark_max.full; 493 priority_mark12.full = wm1.priority_mark_max.full;
491 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 494 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
492 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 495 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
493 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 496 if (rdev->disp_priority == 2) {
494 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 497 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
498 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
499 }
500 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
501 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
502 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
503 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
495 } else if (mode0) { 504 } else if (mode0) {
496 if (rfixed_trunc(wm0.dbpp) > 64) 505 if (rfixed_trunc(wm0.dbpp) > 64)
497 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair); 506 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
@@ -518,8 +527,11 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
518 priority_mark02.full = 0; 527 priority_mark02.full = 0;
519 if (wm0.priority_mark_max.full > priority_mark02.full) 528 if (wm0.priority_mark_max.full > priority_mark02.full)
520 priority_mark02.full = wm0.priority_mark_max.full; 529 priority_mark02.full = wm0.priority_mark_max.full;
521 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 530 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
522 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 531 if (rdev->disp_priority == 2)
532 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
533 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
534 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
523 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, 535 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
524 S_006D48_D2MODE_PRIORITY_A_OFF(1)); 536 S_006D48_D2MODE_PRIORITY_A_OFF(1));
525 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, 537 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
@@ -550,12 +562,15 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
550 priority_mark12.full = 0; 562 priority_mark12.full = 0;
551 if (wm1.priority_mark_max.full > priority_mark12.full) 563 if (wm1.priority_mark_max.full > priority_mark12.full)
552 priority_mark12.full = wm1.priority_mark_max.full; 564 priority_mark12.full = wm1.priority_mark_max.full;
565 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
566 if (rdev->disp_priority == 2)
567 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
553 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, 568 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
554 S_006548_D1MODE_PRIORITY_A_OFF(1)); 569 S_006548_D1MODE_PRIORITY_A_OFF(1));
555 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, 570 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
556 S_00654C_D1MODE_PRIORITY_B_OFF(1)); 571 S_00654C_D1MODE_PRIORITY_B_OFF(1));
557 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 572 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
558 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 573 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
559 } 574 }
560} 575}
561 576
diff --git a/drivers/gpu/drm/radeon/rs690d.h b/drivers/gpu/drm/radeon/rs690d.h
index 62d31e7a897f..36e6398a98ae 100644
--- a/drivers/gpu/drm/radeon/rs690d.h
+++ b/drivers/gpu/drm/radeon/rs690d.h
@@ -182,6 +182,9 @@
182#define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 182#define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16)
183#define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 183#define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1)
184#define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF 184#define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF
185#define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20)
186#define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1)
187#define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF
185#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 188#define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24)
186#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 189#define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1)
187#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 190#define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index d94291add6db..1cf233f7e516 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -1016,7 +1016,7 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1016 struct drm_display_mode *mode1 = NULL; 1016 struct drm_display_mode *mode1 = NULL;
1017 struct rv515_watermark wm0; 1017 struct rv515_watermark wm0;
1018 struct rv515_watermark wm1; 1018 struct rv515_watermark wm1;
1019 u32 tmp; 1019 u32 tmp, d1mode_priority_a_cnt, d2mode_priority_a_cnt;
1020 fixed20_12 priority_mark02, priority_mark12, fill_rate; 1020 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1021 fixed20_12 a, b; 1021 fixed20_12 a, b;
1022 1022
@@ -1084,10 +1084,16 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1084 priority_mark12.full = 0; 1084 priority_mark12.full = 0;
1085 if (wm1.priority_mark_max.full > priority_mark12.full) 1085 if (wm1.priority_mark_max.full > priority_mark12.full)
1086 priority_mark12.full = wm1.priority_mark_max.full; 1086 priority_mark12.full = wm1.priority_mark_max.full;
1087 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 1087 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
1088 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 1088 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
1089 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 1089 if (rdev->disp_priority == 2) {
1090 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 1090 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1091 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1092 }
1093 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1094 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1095 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1096 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1091 } else if (mode0) { 1097 } else if (mode0) {
1092 if (rfixed_trunc(wm0.dbpp) > 64) 1098 if (rfixed_trunc(wm0.dbpp) > 64)
1093 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair); 1099 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
@@ -1114,8 +1120,11 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1114 priority_mark02.full = 0; 1120 priority_mark02.full = 0;
1115 if (wm0.priority_mark_max.full > priority_mark02.full) 1121 if (wm0.priority_mark_max.full > priority_mark02.full)
1116 priority_mark02.full = wm0.priority_mark_max.full; 1122 priority_mark02.full = wm0.priority_mark_max.full;
1117 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02)); 1123 d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
1118 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02)); 1124 if (rdev->disp_priority == 2)
1125 d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1126 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1127 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1119 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); 1128 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1120 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); 1129 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1121 } else { 1130 } else {
@@ -1144,10 +1153,13 @@ void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1144 priority_mark12.full = 0; 1153 priority_mark12.full = 0;
1145 if (wm1.priority_mark_max.full > priority_mark12.full) 1154 if (wm1.priority_mark_max.full > priority_mark12.full)
1146 priority_mark12.full = wm1.priority_mark_max.full; 1155 priority_mark12.full = wm1.priority_mark_max.full;
1156 d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
1157 if (rdev->disp_priority == 2)
1158 d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1147 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF); 1159 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1148 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF); 1160 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1149 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12)); 1161 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1150 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12)); 1162 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1151 } 1163 }
1152} 1164}
1153 1165
@@ -1157,6 +1169,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
1157 struct drm_display_mode *mode0 = NULL; 1169 struct drm_display_mode *mode0 = NULL;
1158 struct drm_display_mode *mode1 = NULL; 1170 struct drm_display_mode *mode1 = NULL;
1159 1171
1172 radeon_update_display_priority(rdev);
1173
1160 if (rdev->mode_info.crtcs[0]->base.enabled) 1174 if (rdev->mode_info.crtcs[0]->base.enabled)
1161 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 1175 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1162 if (rdev->mode_info.crtcs[1]->base.enabled) 1176 if (rdev->mode_info.crtcs[1]->base.enabled)
@@ -1166,7 +1180,8 @@ void rv515_bandwidth_update(struct radeon_device *rdev)
1166 * modes if the user specifies HIGH for displaypriority 1180 * modes if the user specifies HIGH for displaypriority
1167 * option. 1181 * option.
1168 */ 1182 */
1169 if (rdev->disp_priority == 2) { 1183 if ((rdev->disp_priority == 2) &&
1184 (rdev->family == CHIP_RV515)) {
1170 tmp = RREG32_MC(MC_MISC_LAT_TIMER); 1185 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1171 tmp &= ~MC_DISP1R_INIT_LAT_MASK; 1186 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1172 tmp &= ~MC_DISP0R_INIT_LAT_MASK; 1187 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-03 19:38:10 -0500