2 files changed, 4 insertions, 24 deletions

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d2bb03..2d49aa949fa1 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -83,7 +83,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
                 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
                 /* Required by the SDM */
-                sync_core();
+                native_cpuid_eax(1);
                 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
         }
 
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index b624b54912e1..f79249fab389 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -368,26 +368,6 @@ next:
         return patch;
 }
 
-static void cpuid_1(void)
-{
-        /*
-         * According to the Intel SDM, Volume 3, 9.11.7:
-         *
-         *   CPUID returns a value in a model specific register in
-         *   addition to its usual register return values. The
-         *   semantics of CPUID cause it to deposit an update ID value
-         *   in the 64-bit model-specific register at address 08BH
-         *   (IA32_BIOS_SIGN_ID). If no update is present in the
-         *   processor, the value in the MSR remains unmodified.
-         *
-         * Use native_cpuid -- this code runs very early and we don't
-         * want to mess with paravirt.
-         */
-        unsigned int eax = 1, ebx, ecx = 0, edx;
-
-        native_cpuid(&eax, &ebx, &ecx, &edx);
-}
-
 static int collect_cpu_info_early(struct ucode_cpu_info *uci)
 {
         unsigned int val[2];
@@ -413,7 +393,7 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci)
         native_wrmsrl(MSR_IA32_UCODE_REV, 0);
 
         /* As documented in the SDM: Do a CPUID 1 here */
-        cpuid_1();
+        native_cpuid_eax(1);
 
         /* get the current revision from MSR 0x8B */
         native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
@@ -613,7 +593,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
         native_wrmsrl(MSR_IA32_UCODE_REV, 0);
 
         /* As documented in the SDM: Do a CPUID 1 here */
-        cpuid_1();
+        native_cpuid_eax(1);
 
         /* get the current revision from MSR 0x8B */
         native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
@@ -825,7 +805,7 @@ static int apply_microcode_intel(int cpu)
         wrmsrl(MSR_IA32_UCODE_REV, 0);
 
         /* As documented in the SDM: Do a CPUID 1 here */
-        cpuid_1();
+        native_cpuid_eax(1);
 
         /* get the current revision from MSR 0x8B */
         rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);