diff options
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/disp.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/head.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drm.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 60 | ||||
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c | 11 |
7 files changed, 75 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.h b/drivers/gpu/drm/nouveau/dispnv50/disp.h index 2216c58620c2..7c41b0599d1a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.h | |||
| @@ -41,6 +41,7 @@ struct nv50_disp_interlock { | |||
| 41 | NV50_DISP_INTERLOCK__SIZE | 41 | NV50_DISP_INTERLOCK__SIZE |
| 42 | } type; | 42 | } type; |
| 43 | u32 data; | 43 | u32 data; |
| 44 | u32 wimm; | ||
| 44 | }; | 45 | }; |
| 45 | 46 | ||
| 46 | void corec37d_ntfy_init(struct nouveau_bo *, u32); | 47 | void corec37d_ntfy_init(struct nouveau_bo *, u32); |
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 2e7a0c347ddb..06ee23823a68 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c | |||
| @@ -306,7 +306,7 @@ nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) | |||
| 306 | asyh->set.or = head->func->or != NULL; | 306 | asyh->set.or = head->func->or != NULL; |
| 307 | } | 307 | } |
| 308 | 308 | ||
| 309 | if (asyh->state.mode_changed) | 309 | if (asyh->state.mode_changed || asyh->state.connectors_changed) |
| 310 | nv50_head_atomic_check_mode(head, asyh); | 310 | nv50_head_atomic_check_mode(head, asyh); |
| 311 | 311 | ||
| 312 | if (asyh->state.color_mgmt_changed || | 312 | if (asyh->state.color_mgmt_changed || |
| @@ -413,6 +413,7 @@ nv50_head_atomic_duplicate_state(struct drm_crtc *crtc) | |||
| 413 | asyh->ovly = armh->ovly; | 413 | asyh->ovly = armh->ovly; |
| 414 | asyh->dither = armh->dither; | 414 | asyh->dither = armh->dither; |
| 415 | asyh->procamp = armh->procamp; | 415 | asyh->procamp = armh->procamp; |
| 416 | asyh->or = armh->or; | ||
| 416 | asyh->dp = armh->dp; | 417 | asyh->dp = armh->dp; |
| 417 | asyh->clr.mask = 0; | 418 | asyh->clr.mask = 0; |
| 418 | asyh->set.mask = 0; | 419 | asyh->set.mask = 0; |
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c index 9103b8494279..f7dbd965e4e7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c | |||
| @@ -75,6 +75,7 @@ wimmc37b_init_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, | |||
| 75 | return ret; | 75 | return ret; |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | wndw->interlock.wimm = wndw->interlock.data; | ||
| 78 | wndw->immd = func; | 79 | wndw->immd = func; |
| 79 | return 0; | 80 | return 0; |
| 80 | } | 81 | } |
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index b95181027b31..283ff690350e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c | |||
| @@ -127,7 +127,7 @@ void | |||
| 127 | nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, | 127 | nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, |
| 128 | struct nv50_wndw_atom *asyw) | 128 | struct nv50_wndw_atom *asyw) |
| 129 | { | 129 | { |
| 130 | if (interlock) { | 130 | if (interlock[NV50_DISP_INTERLOCK_CORE]) { |
| 131 | asyw->image.mode = 0; | 131 | asyw->image.mode = 0; |
| 132 | asyw->image.interval = 1; | 132 | asyw->image.interval = 1; |
| 133 | } | 133 | } |
| @@ -149,7 +149,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, | |||
| 149 | if (asyw->set.point) { | 149 | if (asyw->set.point) { |
| 150 | if (asyw->set.point = false, asyw->set.mask) | 150 | if (asyw->set.point = false, asyw->set.mask) |
| 151 | interlock[wndw->interlock.type] |= wndw->interlock.data; | 151 | interlock[wndw->interlock.type] |= wndw->interlock.data; |
| 152 | interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.data; | 152 | interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm; |
| 153 | 153 | ||
| 154 | wndw->immd->point(wndw, asyw); | 154 | wndw->immd->point(wndw, asyw); |
| 155 | wndw->immd->update(wndw, interlock); | 155 | wndw->immd->update(wndw, interlock); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 22cd45845e07..7c2fcaba42d6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c | |||
| @@ -631,7 +631,8 @@ static int nouveau_drm_probe(struct pci_dev *pdev, | |||
| 631 | /* We need to check that the chipset is supported before booting | 631 | /* We need to check that the chipset is supported before booting |
| 632 | * fbdev off the hardware, as there's no way to put it back. | 632 | * fbdev off the hardware, as there's no way to put it back. |
| 633 | */ | 633 | */ |
| 634 | ret = nvkm_device_pci_new(pdev, NULL, "error", true, false, 0, &device); | 634 | ret = nvkm_device_pci_new(pdev, nouveau_config, "error", |
| 635 | true, false, 0, &device); | ||
| 635 | if (ret) | 636 | if (ret) |
| 636 | return ret; | 637 | return ret; |
| 637 | 638 | ||
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7971096b6767..10d91e8bbb94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | |||
| @@ -2540,6 +2540,41 @@ nv166_chipset = { | |||
| 2540 | .sec2 = tu102_sec2_new, | 2540 | .sec2 = tu102_sec2_new, |
| 2541 | }; | 2541 | }; |
| 2542 | 2542 | ||
| 2543 | static const struct nvkm_device_chip | ||
| 2544 | nv167_chipset = { | ||
| 2545 | .name = "TU117", | ||
| 2546 | .bar = tu102_bar_new, | ||
| 2547 | .bios = nvkm_bios_new, | ||
| 2548 | .bus = gf100_bus_new, | ||
| 2549 | .devinit = tu102_devinit_new, | ||
| 2550 | .fault = tu102_fault_new, | ||
| 2551 | .fb = gv100_fb_new, | ||
| 2552 | .fuse = gm107_fuse_new, | ||
| 2553 | .gpio = gk104_gpio_new, | ||
| 2554 | .gsp = gv100_gsp_new, | ||
| 2555 | .i2c = gm200_i2c_new, | ||
| 2556 | .ibus = gm200_ibus_new, | ||
| 2557 | .imem = nv50_instmem_new, | ||
| 2558 | .ltc = gp102_ltc_new, | ||
| 2559 | .mc = tu102_mc_new, | ||
| 2560 | .mmu = tu102_mmu_new, | ||
| 2561 | .pci = gp100_pci_new, | ||
| 2562 | .pmu = gp102_pmu_new, | ||
| 2563 | .therm = gp100_therm_new, | ||
| 2564 | .timer = gk20a_timer_new, | ||
| 2565 | .top = gk104_top_new, | ||
| 2566 | .ce[0] = tu102_ce_new, | ||
| 2567 | .ce[1] = tu102_ce_new, | ||
| 2568 | .ce[2] = tu102_ce_new, | ||
| 2569 | .ce[3] = tu102_ce_new, | ||
| 2570 | .ce[4] = tu102_ce_new, | ||
| 2571 | .disp = tu102_disp_new, | ||
| 2572 | .dma = gv100_dma_new, | ||
| 2573 | .fifo = tu102_fifo_new, | ||
| 2574 | .nvdec[0] = gp102_nvdec_new, | ||
| 2575 | .sec2 = tu102_sec2_new, | ||
| 2576 | }; | ||
| 2577 | |||
| 2543 | static int | 2578 | static int |
| 2544 | nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, | 2579 | nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, |
| 2545 | struct nvkm_notify *notify) | 2580 | struct nvkm_notify *notify) |
| @@ -2824,8 +2859,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, | |||
| 2824 | u64 mmio_base, mmio_size; | 2859 | u64 mmio_base, mmio_size; |
| 2825 | u32 boot0, strap; | 2860 | u32 boot0, strap; |
| 2826 | void __iomem *map; | 2861 | void __iomem *map; |
| 2827 | int ret = -EEXIST; | 2862 | int ret = -EEXIST, i; |
| 2828 | int i; | 2863 | unsigned chipset; |
| 2829 | 2864 | ||
| 2830 | mutex_lock(&nv_devices_mutex); | 2865 | mutex_lock(&nv_devices_mutex); |
| 2831 | if (nvkm_device_find_locked(handle)) | 2866 | if (nvkm_device_find_locked(handle)) |
| @@ -2870,6 +2905,26 @@ nvkm_device_ctor(const struct nvkm_device_func *func, | |||
| 2870 | strap = ioread32_native(map + 0x101000); | 2905 | strap = ioread32_native(map + 0x101000); |
| 2871 | iounmap(map); | 2906 | iounmap(map); |
| 2872 | 2907 | ||
| 2908 | /* chipset can be overridden for devel/testing purposes */ | ||
| 2909 | chipset = nvkm_longopt(device->cfgopt, "NvChipset", 0); | ||
| 2910 | if (chipset) { | ||
| 2911 | u32 override_boot0; | ||
| 2912 | |||
| 2913 | if (chipset >= 0x10) { | ||
| 2914 | override_boot0 = ((chipset & 0x1ff) << 20); | ||
| 2915 | override_boot0 |= 0x000000a1; | ||
| 2916 | } else { | ||
| 2917 | if (chipset != 0x04) | ||
| 2918 | override_boot0 = 0x20104000; | ||
| 2919 | else | ||
| 2920 | override_boot0 = 0x20004000; | ||
| 2921 | } | ||
| 2922 | |||
| 2923 | nvdev_warn(device, "CHIPSET OVERRIDE: %08x -> %08x\n", | ||
| 2924 | boot0, override_boot0); | ||
| 2925 | boot0 = override_boot0; | ||
| 2926 | } | ||
| 2927 | |||
| 2873 | /* determine chipset and derive architecture from it */ | 2928 | /* determine chipset and derive architecture from it */ |
| 2874 | if ((boot0 & 0x1f000000) > 0) { | 2929 | if ((boot0 & 0x1f000000) > 0) { |
| 2875 | device->chipset = (boot0 & 0x1ff00000) >> 20; | 2930 | device->chipset = (boot0 & 0x1ff00000) >> 20; |
| @@ -2996,6 +3051,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, | |||
| 2996 | case 0x162: device->chip = &nv162_chipset; break; | 3051 | case 0x162: device->chip = &nv162_chipset; break; |
| 2997 | case 0x164: device->chip = &nv164_chipset; break; | 3052 | case 0x164: device->chip = &nv164_chipset; break; |
| 2998 | case 0x166: device->chip = &nv166_chipset; break; | 3053 | case 0x166: device->chip = &nv166_chipset; break; |
| 3054 | case 0x167: device->chip = &nv167_chipset; break; | ||
| 2999 | default: | 3055 | default: |
| 3000 | nvdev_error(device, "unknown chipset (%08x)\n", boot0); | 3056 | nvdev_error(device, "unknown chipset (%08x)\n", boot0); |
| 3001 | goto done; | 3057 | goto done; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c index 5f301e632599..818d21bd28d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c | |||
| @@ -365,8 +365,15 @@ nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps) | |||
| 365 | * and it's better to have a failed modeset than that. | 365 | * and it's better to have a failed modeset than that. |
| 366 | */ | 366 | */ |
| 367 | for (cfg = nvkm_dp_rates; cfg->rate; cfg++) { | 367 | for (cfg = nvkm_dp_rates; cfg->rate; cfg++) { |
| 368 | if (cfg->nr <= outp_nr && cfg->nr <= outp_bw) | 368 | if (cfg->nr <= outp_nr && cfg->nr <= outp_bw) { |
| 369 | failsafe = cfg; | 369 | /* Try to respect sink limits too when selecting |
| 370 | * lowest link configuration. | ||
| 371 | */ | ||
| 372 | if (!failsafe || | ||
| 373 | (cfg->nr <= sink_nr && cfg->bw <= sink_bw)) | ||
| 374 | failsafe = cfg; | ||
| 375 | } | ||
| 376 | |||
| 370 | if (failsafe && cfg[1].rate < dataKBps) | 377 | if (failsafe && cfg[1].rate < dataKBps) |
| 371 | break; | 378 | break; |
| 372 | } | 379 | } |
